CN112542996A - High-order synchronous integral demodulation circuit and method for gyro digital signal - Google Patents
High-order synchronous integral demodulation circuit and method for gyro digital signal Download PDFInfo
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Abstract
The invention provides a high-order synchronous integral demodulation circuit of a gyro digital signal, which comprises: a signal source; the output interface is connected with the input interface of the fourth-order integrating circuit through the signal source switch and used for outputting signals to the fourth-order integrating circuit; the output interface of the fourth-order integration circuit is connected with the input interface of the differential amplification module and used for performing fourth-order integration on the output signal of the signal source and outputting the output signal to the differential amplification circuit; the input interface of the differential amplification module is connected with the output interface of the fourth-order integrating circuit and is used for amplifying the output signal of the fourth-order integrating circuit; and the switch control module controls the switch to switch a conduction path, and the switching frequency of the switch is the same as the output signal frequency of the signal source. The invention can inhibit the noise of the signal source and extract the signal information.
Description
Technical Field
The invention relates to the technical field of digital circuit demodulation, in particular to a high-order synchronous integral demodulation circuit and a high-order synchronous integral demodulation method for a gyroscope digital signal.
Background
In the existing demodulation algorithm, the application of multiplication demodulation is the most extensive, the method is simple, but the anti-noise capability is weak, the detection precision is low, a high-order filter needs to be configured in a circuit, the occupied resources are more, and the cost is not favorably reduced. The synchronous integral demodulation is a more preferable item in the aspects of noise resistance and resource occupation because an R-C circuit is adopted.
Disclosure of Invention
The high-order synchronous integral demodulation circuit and the method for the gyroscope digital signal can improve the anti-noise capability.
In a first aspect, the present invention provides a high-order synchronous integral demodulation circuit for a gyro digital signal, including:
the signal source is used for generating signals and outputting the signals;
the input interface of the fourth-order integrating circuit is connected with the output interface of the signal source through a signal source switch, and the fourth-order integrating circuit is used for carrying out fourth-order integration on the output signal of the signal source and outputting the output signal;
the input interface of the differential amplification module is connected with the output interface of the fourth-order integrating circuit and is used for amplifying the output signal of the fourth-order integrating circuit;
and the switch control module controls the signal source switch to switch a conduction path, and the switching frequency of the switch is the same as the output signal frequency of the signal source.
Optionally, the fourth-order integrating circuit includes four integrating circuits cascaded through an integrating circuit switch, an input interface of the first integrating circuit is connected to an output interface of the signal source through a signal source switch, and an output interface of the last integrating circuit is connected to the differential amplifying module;
and the switching of the switch state of the integration circuit is controlled by the switch control module.
Optionally, the integration circuit comprises two integrators, and the integration circuit switch has two conducting states, one of the conducting states of the integration circuit switch corresponds to the conduction of one of the integrators, and the other conducting state of the integration circuit switch corresponds to the conduction of the other integrator.
Optionally, four of the integration circuits are the same integration circuit.
Optionally, the integration circuit comprises a resistor and two capacitors; one end of the capacitor is grounded, when the switch of the integration circuit is in one conducting state, the resistor is connected with one capacitor in series to form one integrator, and when the switch of the integration circuit is in the other conducting state, the resistor is connected with the other capacitor in series to form the other integrator.
The invention provides a high-order synchronous integral demodulation method of a gyro digital signal, which comprises the steps of inputting a signal of a signal source into a fourth-order integral circuit through a signal source switch to carry out integral operation, and inputting the operated signal into a differential amplifier to carry out amplification operation;
the control signal of the signal source switch is a square wave signal with the same signal frequency as the signal frequency of the signal source.
Optionally, the fourth order integration circuit comprises four cascaded integration circuits;
the integration circuit receives the output signal of the previous integration circuit through the integration circuit switch and carries out integration operation, and then the signal is output to the next integration circuit through the integration circuit switch;
and the control signal of the integrating circuit switch is a square wave signal with the same signal frequency as the signal frequency of the signal source.
Optionally, four same integration circuits are used to perform stepwise integration operation on the signal.
Optionally, the integration circuit includes two integrators, and the two integrators are controlled by switching of the conduction state of the integration circuit switch to perform integration operation on the positive half cycle and the negative half cycle of the signal respectively.
Optionally, the integration circuit includes two capacitors and a resistor, one end of the capacitor is grounded, and the capacitor connected in series with the resistor is switched by the integration circuit switch to form an integrator for performing an integration operation on a positive half cycle of a signal or an integrator for performing an integration operation on a negative half cycle of a signal.
The invention is used for gyro digital signal high-order synchronous integration demodulation circuit and method, because the frequency and phase place of the noise are random, can't be synchronous with the switch, therefore the noise is mostly filtered out while the electric capacity is charged, only a very small part can pass, the value after integrating is very small, if there is interference signal still, as long as this interference frequency is not exactly in the transmission passband of the synchronous integrator, the synchronous integrator can filter these interferences too, therefore the synchronous integrator has stronger noise suppression ability. Since noise can be suppressed every time the signal is synchronously integrated, noise can be basically eliminated after four times of synchronous integration. And when the frequency of the input modulation signal is equal to that of the square wave switching signal, the effective output voltage of the cascaded synchronous integrator is not attenuated, and the integrity of the signal can be ensured.
Drawings
FIG. 1 is a first-order synchronous integration circuit diagram of an embodiment of the gyro digital signal high-order synchronous integration demodulation circuit and method of the present invention;
FIG. 2 is a diagram of a fourth-order synchronous integration circuit of an embodiment of the gyro digital signal high-order synchronous integration demodulation circuit and method of the present invention;
FIG. 3 is a block diagram of a synchronous integrator according to an embodiment of the present invention;
FIG. 4 shows the simulation results of the first, third and fourth order synchronous integrator-demodulators according to an embodiment of the gyro digital signal high-order synchronous integrator-demodulator circuit and method of the present invention;
fig. 5 is a simulation result of the noise suppression capability of the fourth-order synchronous integral demodulator according to the embodiment of the gyro digital signal high-order synchronous integral demodulation circuit and method of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
As shown in fig. 1 to 5, the present embodiment provides a high-order synchronous integral demodulation circuit for a gyro digital signal, including:
a signal source; the output interface is connected with the input interface of the fourth-order integrating circuit through the signal source switch and used for outputting signals to the fourth-order integrating circuit;
in this embodiment, a signal modulation module is used as a signal source, and a switch signal of a common-frequency square wave switch drives a signal source switch to introduce a modulation signal into a fourth-order integrating circuit.
The output interface of the fourth-order integration circuit is connected with the input interface of the differential amplification module and used for performing fourth-order integration on the output signal of the signal source and outputting the output signal to the differential amplification circuit;
two different integrator branches of each order of integration circuit are respectively a positive integration branch and a negative integration branch, wherein the positive integration branch receives and integrates positive half cycles (phase is 0-180 degrees, and the following description is given by using the positive half cycle), and the negative integration branch receives and integrates negative half cycles (phase is 180-360 degrees, and the following description is given by using the negative half cycle) of the sine wave. The square wave switching signal and the sine wave signal can only have two states in one period: 0-180 DEG forward output and 180 DEG reverse output. Therefore, the input signal is led to the two integrators through the same-frequency square wave switch signal, when the signal is in the positive half cycle, the square wave switch signal is positive, the signal enters the positive integration branch, when the signal is in the negative half cycle, the square wave switch signal is negative, and the signal enters the negative integration branch. The signal which is integrated enters the input end of the second-order integration circuit.
The same-frequency square wave switch signal guides the input signal into two integrators of a second-order integrating circuit; the input of the step is a positive and negative integral signal after first-order integral processing through two paths, the output is a positive and negative integral signal after second-order integral processing, and the process is the same as that of the first-order integral circuit. The signal that has completed the integration enters the input of the third order integration circuit.
The same-frequency square wave switch signal guides the input signal into two different integrators of a third-order integration circuit; the input of the step is a positive and negative integral signal after two paths of integral processing in the second order, the output is a positive and negative integral signal after three-order integral processing, and the process is the same as the processing process of the first-order integral circuit. The integrated signal enters the input of the fourth stage circuit.
Step four: the same-frequency square wave switch signal guides the input signal into two different integrating circuits of a fourth-order demodulation algorithm; the input of the step is a positive and negative integral signal after three-order integral processing, the output is a positive and negative integral signal after four-order integral processing, and the process is the same as the processing process of the first-order integral circuit. And outputting the integrated signal to a differential amplification module.
The input interface of the differential amplification module is connected with the output interface of the fourth-order integrating circuit and is used for amplifying the output signal of the fourth-order integrating circuit;
the input signal of the differential amplification module is a positive and negative integral signal after two paths of four-order integration processing, the output is a voltage signal amplified by the differential amplifier, the output signals of the positive and negative two paths of integrators simultaneously contain the amplitude information and the phase information of the input signal, and in practical application, the capacitor C is connected with the differential amplifier1、C2And carrying out differential output on the voltage value to obtain final output voltage.
And the switch control module controls the switch to switch a conduction path, and the switching frequency of the switch is the same as the output signal frequency of the signal source. The working process of the switch module is already described in detail in the process of inputting the signal source to the fourth-order integrating circuit, and is not described herein again.
Optionally, the fourth-order integrating circuit includes four integrating circuits cascaded through an integrating circuit switch, an input interface of the first integrating circuit is connected to an output interface of the signal source through a signal source switch, and an output interface of the last integrating circuit is connected to the differential amplifying module;
and the switching of the switch state is controlled by the switch control module.
Optionally, the integration circuit includes two integrators, and the integration circuit switch includes two conducting states, where the two conducting states of the integration circuit switch correspond to the conducting states of the two integrators, respectively.
Optionally, four of the integration circuits are the same integration circuit.
Optionally, the integration circuit comprises a resistor and two capacitors; one end of the capacitor is grounded, and the capacitor connected with the resistor in series is switched through the integrating circuit switch to form an integrator.
In this embodiment, a block schematic as shown in fig. 3 may be used to accumulate the signals. The signal has only two states and only two integrators are needed. The square wave synchronous switch is adopted to synchronously connect the signals to the two integrators, and the synchronous switch is also used to connect the integrators with the load so as to synchronously output the signals.
A simplified form of synchronous integrator is shown in figure 1. Switch S at frequency fRAlternately will C1And C2To R, an output voltage VoIs an input current Ii(t)＝Vi(t)/R are alternately RC1And RC2The result of the integration. Usually we consider the signal of switch S as the reference signal, fRIs the frequency of the reference signal. The switch S is typically an electronic switch. The voltage waveform of the excitation switch is a square wave signal with the same frequency as the input signal. And the overall processing result of the fourth order integrator circuit is shown in fig. 2.
Due to control of switch S, make C1Charging during half cycle of the switchWhile during the other half period the charging power is cut off, pair C1The charging current is 0. For C2And C1As such. The switches of the synchronous integrators alternately integrate the capacitors, Ic1And R is each C1Input current and integrating resistance of integrator, Ic2And R is each C2The input current of the integrator and the integrating resistor. The detailed working process of the first-order synchronous integrator is described above, and the fourth-order synchronous integrator is a cascade of four and one orders, and has the same working mode as the first order.
Based on a Simulink simulation platform in MATLAB, a four-order cascade synchronous integration circuit simulation is set up, and the first-order output, the third-order output and the fourth-order output of the four-order cascade synchronous integration circuit simulation are observed. When the frequency of the input signal is equal to the frequency of the switching control signal, the simulation results are shown in fig. 4 and 5.
In the simulation process, 8 capacitors of the fourth-order integrating circuit are all set to be 10 nF; the four resistors are each set to 20k omega. The input signal is set to be a sine wave signal with the frequency of 11567Hz and the amplitude of 2V, the square wave switch signal is set to be a square wave signal with the frequency of 11567Hz and the amplitude of 2V, the simulation time is set to be 2s, and the noise module is set to be 0V firstly to verify the amplitude attenuation condition of the noise module; and then set to 0.1V to verify its noise immunity. The simulation output of the first-order, third-order and fourth-order synchronous integral demodulators is shown in figure 4, and the simulation output of the anti-noise capability is shown in figure 5.
As can be seen from fig. 4, when the frequency of the input signal is equal to the frequency of the square wave switching signal, the output amplitudes of the cascade synchronous integration circuits of the orders are completely equal, and the conclusion that the output amplitudes of the cascade synchronous integration circuits are not attenuated is verified. As can be seen from fig. 5, the synchronous integration circuit of the fourth-order cascade has a stronger noise suppression capability.
The synchronous integrator is controlled by a square wave synchronous switch, so that the same-frequency signals respectively charge two capacitors, and the charging potential on the capacitors is the integral value of the signals in the charging time. Since the frequency and phase of the noise are random and cannot be synchronized with the switch, most of the noise is filtered when the capacitor is charged, only a very small part of the noise can pass through the capacitor, the value after integration is very small, if interference signals exist, the synchronous integrator can also filter the interference if the interference frequency is not exactly in the transmission pass band of the synchronous integrator, and therefore the synchronous integrator has strong noise suppression capability.
Example 2
As shown in fig. 1-5, in the present embodiment, a high-order synchronous integral demodulation method for a digital signal of a gyroscope is provided, where a signal of a signal source is input to a fourth-order integrating circuit through a signal source switch to perform an integral operation, and the signal after the operation is input to a differential amplifier to perform an amplification operation;
and adopting a square wave signal with the same signal frequency as the signal frequency of the signal source as a control signal of the signal source switch.
The embodiment specifically comprises the following steps:
the method comprises the following steps: the same-frequency square wave switch signal guides the input modulation signal into two integrating circuits of a first-order demodulation algorithm; the signal source of the step is the input of the output signal of the gyroscope detection end, and the control signal adopts a switching square wave signal with the same frequency as the signal source, wherein the signal of the signal source is a standard sine wave, and the frequency is the driving frequency of the gyroscope. When the phase of the digital signal is 0-180 degrees, the square wave switching signal is equal to '1', and when the phase is 180 degrees, the square wave switching signal is equal to '0', the two paths of positive and negative integration signals after integration processing are output. The signal processing diagram of the first step is shown in fig. 1.
The integration processing in the demodulation step includes two different integration branches, namely a positive integration branch and a negative integration branch, wherein the positive integration branch receives and integrates the positive half cycle (phase is 0-180 °, and hereinafter, the positive half cycle is collectively described) of the sine wave, and the negative integration branch receives and integrates the negative half cycle (phase is 180-360 °, and hereinafter, the negative half cycle is collectively described) of the sine wave. The square wave switching signal and the sine wave signal can only have two states in one period: 0-180 DEG forward output and 180 DEG reverse output. Therefore, the input signal is led to the two integrators through the same-frequency square wave switch signal, when the signal is in the positive half cycle, the square wave switch signal is positive, the signal enters the positive integration branch, when the signal is in the negative half cycle, the square wave switch signal is negative, and the signal enters the negative integration branch. And (4) the integrated signal enters the input end of the next-stage circuit to be processed in the second step.
Step two: the same-frequency square wave switch signal guides the input signal into two integrating circuits of a second-order demodulation algorithm; the input of the step is a positive and negative integral signal after first-order integral processing through two paths, the output is a positive and negative integral signal after second-order integral processing, and the process is the same as the step one. And (4) the integrated signal enters the input end of the next-stage circuit to be processed in the third step.
Step three: the same-frequency square wave switch signal guides the input signal into two different integrating circuits of a third-order demodulation algorithm; the input of the step is a positive and negative integral signal after two paths of integral processing in the second order, the output is a positive and negative integral signal after three-order integral processing, and the process is the same as the step one. And (4) the integrated signal enters the input end of the next-stage circuit to be processed in the fourth step.
Step four: the same-frequency square wave switch signal guides the input signal into two different integrating circuits of a fourth-order demodulation algorithm; the input of the step is a positive and negative integral signal after three-order integral processing, the output is a positive and negative integral signal after four-order integral processing, and the process is the same as the step one. And (4) the integrated signal enters the input end of the next-stage circuit, and the processing of the step five is carried out.
Step five: differential amplification output; the input of the step is positive and negative integral signals after four-stage integral processing by two paths, the output is voltage signals amplified by a differential amplifier, the output signals of the positive and negative two paths of integrators simultaneously contain amplitude information and phase information of the input signals, and in practical application, a capacitor C is connected with a capacitor C1、C2And carrying out differential output on the voltage value to obtain final output voltage. The overall signal processing is shown in fig. 2.
Optionally, the fourth order integration circuit comprises four cascaded integration circuits;
the integration circuit receives the output signal of the previous integration circuit through the integration circuit switch and carries out integration operation, and then the signal is output to the next integration circuit through the integration circuit switch;
and adopting a square wave signal with the same signal frequency as the signal frequency of the signal source as a control signal of the switch of the integrating circuit.
Optionally, four same integration circuits are used to perform stepwise integration operation on the signal.
Optionally, the integration circuit includes two integrators, and the two integrators are controlled by switching of the conduction state of the integration circuit switch to perform integration operation on the positive half cycle and the negative half cycle of the signal respectively.
Optionally, the integration circuit includes two capacitors and a resistor, one end of the capacitor is grounded, and the capacitor connected in series with the resistor is switched by the integration circuit switch to form an integrator for performing an integration operation on a positive half cycle of a signal or an integrator for performing an integration operation on a negative half cycle of a signal.
In this embodiment, the output of the first-order synchronous integrator is used as the input of the second-order synchronous integrator; and so on, the output of the third order synchronous integrator is used as the input of the fourth order synchronous integrator. The fourth order cascaded synchronous integrator is similar to the fourth order R-C low pass filter. When the frequency of the input modulation signal is equal to that of the square wave switching signal, the effective output voltage of the cascaded synchronous integrators cannot be attenuated, and the noise suppression capability is far better than that of a single first-order synchronous integrator.
The synchronous integrator is controlled by a square wave synchronous switch, so that the same-frequency signals respectively charge two capacitors, and the charging potential on the capacitors is the integral value of the signals in the charging time. Since the frequency and phase of the noise are random and cannot be synchronized with the switch, most of the noise is filtered when the capacitor is charged, only a very small part of the noise can pass through the capacitor, the value after integration is very small, if interference signals exist, the synchronous integrator can also filter the interference if the interference frequency is not exactly in the transmission pass band of the synchronous integrator, and therefore the synchronous integrator has strong noise suppression capability.
In this embodiment, a block schematic as shown in fig. 3 may be used to accumulate the signals. The signal has only two states and only two integrators are needed. The square wave synchronous switch is adopted to synchronously connect the signals to the two integrators, and the synchronous switch is also used to connect the integrators with the load so as to synchronously output the signals.
A simplified form of synchronous integrator is shown in figure 1. Switch S at frequency fRAlternately will C1And C2To R, an output voltage VoIs an input current Ii(t)＝Vi(t)/R are alternately RC1And RC2The result of the integration. Usually we consider the signal of switch S as the reference signal, fRIs the frequency of the reference signal. The switch S is typically an electronic switch. The voltage waveform of the excitation switch is a square wave signal with the same frequency as the input signal.
Due to control of switch S, make C1Charging during one half cycle of the switch and cutting off the power supply during the other half cycle, pair C1The charging current is 0. For C2And C1As such. The switches of the synchronous integrators alternately integrate the capacitors, Ic1And R is each C1Input current and integrating resistance of integrator, Ic2And R is each C2The input current of the integrator and the integrating resistor. The detailed working process of the first-order synchronous integrator is described above, and the fourth-order synchronous integrator is a cascade of four and one orders, and has the same working mode as the first order. The following part is a circuit simulation.
Based on a Simulink simulation platform in MATLAB, a four-order cascade synchronous integration circuit simulation is set up, and the first-order output, the third-order output and the fourth-order output of the four-order cascade synchronous integration circuit simulation are observed. When the frequency of the input signal is equal to the frequency of the switching control signal, the simulation results are shown in fig. 4 and 5. In the simulation process, 8 capacitors of the fourth-order integrating circuit are all set to be 10 nF; the four resistors are each set to 20k omega. The input signal is set to be a sine wave signal with the frequency of 11567Hz and the amplitude of 2V, the square wave switch signal is set to be a square wave signal with the frequency of 11567Hz and the amplitude of 2V, the simulation time is set to be 2s, and the noise module is set to be 0V firstly to verify the amplitude attenuation condition of the noise module; and then set to 0.1V to verify its noise immunity. The simulation output of the first-order, third-order and fourth-order synchronous integral demodulators is shown in fig. 4, and the simulation output of the noise-resistant capability of the fourth-order synchronous integrators is shown in fig. 5.
As can be seen from fig. 4, when the frequency of the input signal is equal to the frequency of the square wave switching signal, the output amplitudes of the cascade synchronous integration circuits of the orders are completely equal, and the conclusion that the output amplitudes of the cascade synchronous integration circuits are not attenuated is verified. As can be seen from fig. 5, the synchronous integration circuit of the fourth-order cascade has a stronger noise suppression capability.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A high-order synchronous integral demodulation circuit of a gyro digital signal is characterized in that: the method comprises the following steps:
the signal source is used for generating signals and outputting the signals;
the input interface of the fourth-order integrating circuit is connected with the output interface of the signal source through a signal source switch, and the fourth-order integrating circuit is used for carrying out fourth-order integration on the output signal of the signal source and outputting the output signal;
the input interface of the differential amplification module is connected with the output interface of the fourth-order integrating circuit and is used for amplifying the output signal of the fourth-order integrating circuit;
and the switch control module controls the signal source switch to switch a conduction path, and the switching frequency of the switch is the same as the output signal frequency of the signal source.
2. The high order synchronous integral demodulation circuit of gyro digital signal as claimed in claim 1, characterized by that: the fourth-order integrating circuit comprises four integrating circuits which are cascaded through an integrating circuit switch, an input interface of the first integrating circuit is connected with an output interface of the signal source through a signal source switch, and an output interface of the last integrating circuit is connected with the differential amplification module;
and the switching of the switch state of the integration circuit is controlled by the switch control module.
3. The high order synchronous integral demodulation circuit of gyro digital signal as claimed in claim 2, characterized in that: the integration circuit comprises two integrators, the integration circuit switch has two conducting states, one conducting state of the integration circuit switch corresponds to the conduction of one integrator, and the other conducting state of the integration circuit switch corresponds to the conduction of the other integrator.
4. The high order synchronous integral demodulation circuit of gyro digital signal as claimed in claim 2, characterized in that: the four integration circuits are the same integration circuit.
5. The high order synchronous integral demodulation circuit of gyro digital signal as claimed in claim 3, characterized in that: the integrating circuit comprises a resistor and two capacitors; one end of the capacitor is grounded, when the switch of the integration circuit is in one conducting state, the resistor is connected with one capacitor in series to form one integrator, and when the switch of the integration circuit is in the other conducting state, the resistor is connected with the other capacitor in series to form the other integrator.
6. A high-order synchronous integral demodulation method of a gyro digital signal is characterized in that: inputting a signal of a signal source into a fourth-order integrating circuit through a signal source switch to perform integration operation, and inputting the operated signal into a differential amplifier to perform amplification operation;
the control signal of the signal source switch is a square wave signal with the same signal frequency as the signal frequency of the signal source.
7. The method of higher order synchronous integral demodulation of a gyro digital signal as claimed in claim 6, characterized by: the fourth-order integrating circuit comprises four cascaded integrating circuits;
the integration circuit receives the output signal of the previous integration circuit through the integration circuit switch and carries out integration operation, and then the signal is output to the next integration circuit through the integration circuit switch;
and the control signal of the integrating circuit switch is a square wave signal with the same signal frequency as the signal frequency of the signal source.
8. The method of higher order synchronous integral demodulation of a gyro digital signal as claimed in claim 7, characterized by: and performing stepwise integration operation on the signals by adopting four same integration circuits.
9. The method of higher order synchronous integral demodulation of a gyro digital signal as claimed in claim 7, characterized by: the integration circuit comprises two integrators, and the two integrators are controlled to respectively perform integration operation on the positive half cycle and the negative half cycle of the signal through switching of the conduction state of the switch of the integration circuit.
10. The method for higher order synchronous integral demodulation of a gyro digital signal as claimed in claim 9, characterized by: the integration circuit comprises two capacitors and a resistor, one end of each capacitor is grounded, and the capacitors connected with the resistors in series are switched through an integration circuit switch to form an integrator for performing integration operation on the positive half cycle of a signal or an integrator for performing integration operation on the negative half cycle of the signal.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1139507A (en) * | 1993-12-29 | 1997-01-01 | 齐尼思电子公司 | Circuit for the acquisition of a carrier signal by applying a substitute pilot to a synchronous demodulator |
| CN1162868A (en) * | 1995-12-08 | 1997-10-22 | 日本电气株式会社 | Demodulator circuit using gyrator circuit |
| CN1279854A (en) * | 1997-10-01 | 2001-01-10 | 罗斯蒙德公司 | FSK demodulator using a super linear integrator |
| CN101331678A (en) * | 2005-11-03 | 2008-12-24 | 联发科技股份有限公司 | Switching circuit, and a modulator, demodulator or mixer including such a circuit |
| CN102822693A (en) * | 2010-01-06 | 2012-12-12 | 美萨影像股份公司 | Demodulation Sensor with Separate Pixel and Storage Arrays |
-
2019
- 2019-09-20 CN CN201910897884.8A patent/CN112542996A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1139507A (en) * | 1993-12-29 | 1997-01-01 | 齐尼思电子公司 | Circuit for the acquisition of a carrier signal by applying a substitute pilot to a synchronous demodulator |
| CN1162868A (en) * | 1995-12-08 | 1997-10-22 | 日本电气株式会社 | Demodulator circuit using gyrator circuit |
| CN1279854A (en) * | 1997-10-01 | 2001-01-10 | 罗斯蒙德公司 | FSK demodulator using a super linear integrator |
| CN101331678A (en) * | 2005-11-03 | 2008-12-24 | 联发科技股份有限公司 | Switching circuit, and a modulator, demodulator or mixer including such a circuit |
| CN102822693A (en) * | 2010-01-06 | 2012-12-12 | 美萨影像股份公司 | Demodulation Sensor with Separate Pixel and Storage Arrays |
Non-Patent Citations (1)
| Title |
|---|
| 杨成: "陀螺数字信号的高阶同步积分解调电路和方法", 中国博士学位论文全文数据库（信息科技辑）, no. 2, pages 136 - 186 * |
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