CN112542953A - Synchronous rectification control circuit compatible with CCM and DCM working modes - Google Patents

Synchronous rectification control circuit compatible with CCM and DCM working modes Download PDF

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CN112542953A
CN112542953A CN202011446994.1A CN202011446994A CN112542953A CN 112542953 A CN112542953 A CN 112542953A CN 202011446994 A CN202011446994 A CN 202011446994A CN 112542953 A CN112542953 A CN 112542953A
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ccm
synchronous rectification
output end
input end
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王石武
艾育林
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Shenzhen Rui Zhi Chen Technology Co ltd
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Shenzhen Rui Zhi Chen Technology Co ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
    • H02M3/33592—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/38—Means for preventing simultaneous conduction of switches
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)
  • Rectifiers (AREA)

Abstract

The invention discloses a synchronous rectification control circuit compatible with CCM and DCM working modes, which comprises a CCM control module, a first negative pressure comparator, a second negative pressure comparator and a logic control module, wherein the CCM control module is connected with the output end of the second negative pressure comparator, the first input end of the first negative pressure comparator and the second input end of the second negative pressure comparator are used as the input ends of the synchronous rectification control circuit, the output end of the first negative pressure comparator is connected with the first input end of a first AND gate, the output end of the first AND gate is connected with the first input end of the logic control module, the output end of the second negative pressure comparator is connected with the first input end of a first OR gate, the output end of the first OR gate is connected with the first input end of a second AND gate, the output end of the CCM control module and the output end of the second negative pressure comparator are respectively connected with the first input end and the second input end of a modulation module, the output end of the second AND gate is connected with the second input end of the logic control module.

Description

Synchronous rectification control circuit compatible with CCM and DCM working modes
Technical Field
The invention relates to the technical field of power management, in particular to a synchronous rectification control circuit compatible with CCM and DCM working modes.
Background
With the rapid development of electronic technology in recent years, the size of large-scale integrated circuits is continuously reduced, the power consumption is continuously reduced, the required circuit working voltage is lower and lower, and the working current is larger and larger. The loss of the output end rectifying tube is a part of the loss of the switching power supply which is not negligible, the conduction voltage drop of the traditional rectifying diode is high, even if a low-voltage-drop Schottky diode is adopted, the voltage drop of more than 0.4V can be generated, the conduction loss is large, and the power supply efficiency is low.
Therefore, it is necessary to provide a synchronous rectification control circuit compatible with CCM and DCM operation modes to effectively reduce the rectification conduction loss and improve the efficiency of implementing synchronous rectification.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a synchronous rectification control circuit compatible with CCM and DCM working modes so as to effectively reduce rectification conduction loss and improve the efficiency of realizing synchronous rectification.
In order to solve the technical problems, the invention adopts the following technical scheme: a synchronous rectification control circuit compatible with CCM and DCM working modes comprises a CCM control module, a first negative pressure comparator, a second negative pressure comparator and a logic control module, wherein the CCM control module is connected with the output end of the second negative pressure comparator, the first input end of the first negative pressure comparator and the second input end of the second negative pressure comparator are used as the input ends of the synchronous rectification control circuit, the output end of the first negative pressure comparator is connected with the first input end of a first AND gate, the output end of the first AND gate is connected with the first input end of the logic control module, the output end of the second negative pressure comparator is connected with the first input end of a first OR gate, the output end of the first OR gate is connected with the first input end of a second AND gate, the output end of the control module and the output end of the second negative pressure comparator are respectively connected with the first input end and the second input end of a modulation module, the output end of the modulation module is connected with the second input end of the second AND gate, and the output end of the second AND gate is connected with the second input end of the logic control module.
The further technical scheme is as follows: the synchronous rectification control circuit further comprises an LDO power supply module and a voltage and current bias module, wherein the voltage and current bias module is connected with the LDO power supply module to generate reference voltage and bias current.
The further technical scheme is as follows: the CCM control module comprises a conduction signal modulation unit, the conduction signal modulation unit comprises a third negative pressure comparator, a first NMOS tube, a second NMOS tube, a first PMOS tube and a fifth PMOS tube, the drain electrode of the first NMOS tube is connected with a first current source, the grid electrode of the first NMOS tube is connected with the output end of a NOR gate, the output end of the modulation module is connected with the first input end of the NOR gate through a first delayer, the output end of the modulation module is connected with the second input end of the NOR gate, the source electrode of the first NMOS tube is connected with the second input end of the third negative pressure comparator, the output end of the third negative pressure comparator is used as the output end of the CCM control module, the first input end of the third negative pressure comparator is connected with the drain electrode of the second NMOS tube, the source electrode of the second NMOS tube is grounded, the grid electrode of the third NMOS tube is connected with the output end of an inverting amplifier, and the input end of the inverting amplifier is connected with the output end of the second negative pressure comparator, a second capacitor is connected in parallel between the source and the drain of the second NMOS transistor, the source of the first PMOS transistor is connected to a second current source, the drain of the first PMOS transistor is connected to the drain of the second NMOS transistor, the gate of the first PMOS transistor is connected to the output of the inverting amplifier, the source of the fifth PMOS transistor is connected to the source of the first NMOS transistor, the drain of the fifth PMOS transistor is connected to the output of a second operational amplifier, a first capacitor is connected between the source and the drain of the fifth PMOS transistor, and the inverting input of the second operational amplifier is connected to the drain of the fifth PMOS transistor.
The further technical scheme is as follows: the CCM control module also comprises an abnormal shielding unit, the abnormal shielding unit is connected with the conducting signal modulation unit and comprises a D trigger, a pulse modulator, a second delayer, a third NMOS tube and a second PMOS tube, the grid electrode of the fifth PMOS tube is connected with the reset input end of the D trigger through the second delayer, the clock input end of the D trigger is connected with the output end of the second negative pressure comparator, the first input end of the D trigger is connected with the output end of the modulation module, the first output end of the D trigger is connected with the grid electrode of the fifth PMOS tube through the pulse modulator, the grid electrode of the second PMOS tube is connected with the grid electrode of the fifth PMOS tube, the source electrode of the second PMOS tube is connected with the non-inverting input end of the second operational amplifier, the drain electrode of the second PMOS tube is connected with the drain electrode of the third NMOS tube, and a grounding capacitor is connected between the source electrode of the second PMOS tube and the non-inverting input end of the second operational amplifier in parallel, the grid electrode of the third NMOS tube is connected with the grid electrode of the fifth PMOS tube, the source electrode of the third NMOS tube is grounded, and a fourth capacitor is connected between the drain electrode and the source electrode of the third NMOS tube.
The further technical scheme is as follows: the CCM control module also comprises an abnormal shielding unit, the abnormal shielding unit is connected with the conducting signal modulation unit and comprises a D trigger, a pulse modulator, a second delayer, a third delayer, a first operational amplifier, a third PMOS tube, a fourth PMOS tube and a fourth NMOS tube, the grid electrode of the fifth PMOS tube is connected with the reset input end of the D trigger through the second delayer, the clock input end of the D trigger is connected with the output end of the second negative pressure comparator, the first input end of the D trigger is connected with the output end of the modulation module, the first output end of the D trigger is connected with the grid electrode of the third PMOS tube through the pulse modulator, the drain electrode of the third PMOS tube is connected with the non-inverting input end of the first operational amplifier, the output end of the first operational amplifier is connected with the source electrode of the fourth PMOS tube, the drain electrode of the fourth PMOS tube is connected with the non-inverting input end of the second operational amplifier, the grid electrode of the fourth PMOS tube is connected with the grid electrode of the fifth PMOS tube, a grounding capacitor is connected between the drain electrode of the fourth PMOS tube and the non-inverting input end of the second operational amplifier in parallel, the inverting input end of the first operational amplifier is connected with the output end of the first operational amplifier, the source electrode of the third PMOS tube is connected with the source electrode of the fourth NMOS tube, a fifth capacitor with one grounded end is connected between the source electrode of the third PMOS tube and the source electrode of the fourth NMOS tube in parallel, the drain electrode of the fourth NMOS tube is connected with a third current source, the grid electrode of the fourth NMOS tube is connected with the output end of a third AND gate, the output end of the second negative voltage comparator is connected with the first input end of the third AND gate, and the output end of the second negative voltage comparator is connected with the second input end of the third AND gate through the third delay timer.
The further technical scheme is as follows: when the synchronous rectification control circuit is used for a flyback switching power supply, the output voltage of the flyback switching power supply is used as the power supply voltage of the synchronous rectification control circuit, the input end of the synchronous rectification control circuit is connected with the drain electrode of a synchronous rectification MOS tube of the flyback switching power supply, the output end of the logic control module is connected with the grid electrode of the synchronous rectification MOS tube, and the source electrode of the synchronous rectification MOS tube is grounded.
The invention has the beneficial technical effects that: the synchronous rectification control circuit compatible with the CCM and DCM working modes, disclosed by the invention, has the advantages that the first negative pressure comparator is matched with the first AND gate and the second negative pressure comparator is matched with the first OR gate and the second AND gate, the CCM control module and the modulation module are combined to regulate signal output, the maximum conduction time of a signal is expanded, the control of extremely small dead time is realized, the logic control module is utilized for logic control, the rectification conduction loss is effectively reduced, the high efficiency of synchronous rectification is realized, and the synchronous rectification under the current continuous conduction mode CCM is also realized.
Drawings
Fig. 1 is a topology diagram of the application of the synchronous rectification control circuit compatible with CCM and DCM operation modes according to the present invention.
Fig. 2 is a signal timing diagram of the synchronous rectification control circuit operating in the DCM compatible with CCM and DCM operation modes according to the present invention.
Fig. 3 is a signal timing diagram of the synchronous rectification control circuit operating in the current interrupted CCM according to the present invention compatible with CCM and DCM operation modes.
Fig. 4 is a schematic circuit diagram of a CCM control module of a synchronous rectification control circuit compatible with CCM and DCM operation modes according to an embodiment of the present invention.
FIG. 5 is a schematic circuit diagram of a CCM control module of a synchronous rectification control circuit compatible with CCM and DCM operation modes according to another embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly understood by those skilled in the art, the present invention is further described with reference to the accompanying drawings and examples.
Referring to fig. 1 to 5, fig. 1 shows a topology structure diagram of a flyback switching power supply including a transformer T and an input terminal V, wherein the synchronous rectification control circuit 10 compatible with CCM and DCM operation modes according to the present invention is applied to the flyback switching power supplyinVoltage output terminal VoutAn input capacitor CinPrimary MOS transistor MNSampling resistor RsenseSynchronous rectification MOS tube M0 and output capacitor CoutSaid input terminal VinThe anode of the transformer T is connected with one end of the primary side of the transformer T, the cathode of the transformer T is grounded, and the other end of the primary side of the transformer T is connected with the primary MOS tube MNIs connected with the drain electrode of the primary MOS transistor MNVia the sampling resistor RsenseBack grounded, the primary MOS transistor MNFor receiving a primary control signal Duty, said input capacitance CinAre respectively connected with the input end VinIs connected with the positive and negative poles of the transformer T, and one end of the secondary side of the transformer T is connected with the voltage output terminal VoutThe other end of the positive electrode of the voltage output end V is connected with the drain electrode of the synchronous rectification MOS tube M0outNegative pole of (2) via the output capacitor CoutAnd then grounded. The synchronous rectification CONTROL circuit 10 compatible with the CCM and DCM working modes includes a CCM CONTROL module CCM _ CONTROL, a first negative voltage comparator CM1, a second negative voltage comparator CM2 and a LOGIC CONTROL module LOGIC, wherein the CCM CONTROL module CCM _ CONTROL is connected with an output end of the second negative voltage comparator CM2 and is used for adjusting and controlling a maximum on-time signal TONMAXFor adjusting the maximum on-time of the synchronous rectification MOS transistor M0, a first input terminal of the first negative voltage comparator CM1 AND a second input terminal of the second negative voltage comparator CM2 are used as input terminals of the synchronous rectification CONTROL circuit 10, an output terminal of the first negative voltage comparator CM1 is connected to a first input terminal of a first AND gate AND1, an output terminal of the first AND gate AND1 is connected to a first input terminal of the LOGIC CONTROL module LOGIC, an output terminal of the second negative voltage comparator CM2 is connected to a first input terminal of a first OR gate OR1, an output terminal of the first OR gate OR1 is connected to a first input terminal of a second AND gate AND2, AND an output terminal of the CCM CONTROL module CCM _ CONTROL AND a second negative voltage comparator CM1 are connected to a first input terminal of the LOGIC CONTROL moduleThe output terminal of the voltage comparator CM2 is connected to the first input terminal AND the second input terminal of a modulation block 12, respectively, the output terminal of the modulation block 12 is connected to the second input terminal of the second AND gate AND2, AND the output terminal of the second AND gate AND2 is connected to the second input terminal of the LOGIC control block LOGIC. The output voltage of the flyback switching power supply is used as the power supply voltage Vdd of the synchronous rectification control circuit 10, the input end of the synchronous rectification control circuit 10 is connected with the drain of a synchronous rectification MOS transistor M0 of the flyback switching power supply, the first input end of the first negative voltage comparator CM1 and the second input end of the second negative voltage comparator CM2 are connected with the drain of a synchronous rectification MOS transistor M0, the output end of the LOGIC control module LOGIC is connected with the gate of the synchronous rectification MOS transistor M0, and the source of the synchronous rectification MOS transistor M0 is grounded.
A second input terminal of the first OR gate OR1 receives a minimum on-time signal TONMINA second input terminal of the first AND gate AND1 receives the minimum off-time signal TOFFMINA second input terminal of the second AND gate AND2 receives the maximum on-time signal TCONMAXAND the synchronous rectification CONTROL circuit 10 compatible with the CCM AND DCM working modes is matched with the first AND gate AND1 AND the second negative voltage comparator CM2 AND the first OR gate OR1 AND the second AND gate AND2 through the first negative voltage comparator CM1, is combined with the CCM CONTROL module CCM _ CONTROL AND the modulation module 12 to regulate signal output, enlarges the maximum conduction time of the signal to realize the CONTROL of the minimum dead time, AND then utilizes the LOGIC CONTROL module LOGIC to perform LOGIC CONTROL, thereby effectively reducing the rectification conduction loss, realizing the high efficiency of synchronous rectification, AND further realizing the synchronous rectification under the current continuous conduction mode CCM. Wherein the maximum on-time signal TONMAXIs an output signal of a CCM CONTROL module CCM _ CONTROL for controlling the maximum time of conduction of a synchronous rectification MOS tube M0, and is compared with an output signal T of the second negative voltage comparator CM2BObtaining the maximum continuous conduction time signal TC through modulation of a modulation module 12ONMAXTo adjust the maximum continuous conduction time of the synchronous rectification MOS tube M0 and effectively adjust the dead time TDEAD. When the maximum on-time signal TONMAXIs highMaximum continuous conducting time signal TC when the level is reduced to low levelONMAXFalls to a low level if the output signal T of the second negative voltage comparator CM2 is presentBIs lowered to a low level, the maximum continuous conduction time signal TCONMAXWill rise to a high level, the maximum on-time signal TCONMAXThe time for changing to the low level is a dead time TDEAD. The minimum on-time signal TONMINThe minimum turn-off time signal T is used for limiting the synchronous rectification MOS tube M0 to be turned on at least for corresponding time to be turned off and cut offOFFMINThe minimum on-time signal T is used for limiting the synchronous rectification MOS tube M0 to be at least cut off for corresponding time to be closed and conductedONMINAnd the minimum off-time signal TOFFMINAll controlled by an internal chip setting, preferably, in this embodiment, the minimum on-time signal TONMINThe limitation of the turn-off of the synchronous rectification MOS tube M0 is released when the high level is reduced to the low level, and the minimum turn-off time signal TOFFMINWhen the low level is raised to the high level, the conduction limit of the synchronous rectification MOS tube M0 is released, and the maximum continuous conduction time signal TCONMAXWhen the high level is lowered to the low level, the limitation of the turn-off of the synchronous rectification MOS tube M0 is released.
Specifically, in this embodiment, the synchronous rectification control circuit 10 further includes an LDO power supply module LDO1 and a voltage and current bias module 11, wherein the input end and the voltage output end V of the LDO power supply module LDO1outConnected to generate a power supply voltage Vdd, the voltage and current bias module 11 is connected to an output terminal of the LDO power supply module LDO1 to generate a reference voltage V using an output voltage of the flyback switching power supply as the power supply voltage Vdd of the synchronous rectification control circuit 10refAnd a bias current Ibias。
Referring to fig. 2, fig. 2 shows a signal timing diagram of the synchronous rectification control circuit 10 operating in the discontinuous current conduction mode DCM, when operating, the primary MOS transistor MNOff, secondary current ISThe drain voltage V of the MOS tube M0 is linearly decreased and synchronously rectifiedDRapidly decrease when VDIs lower thanOutput signal T of the first negative voltage comparator CM1 at-80 mVATurning from low to high, and turning on the synchronous rectification MOS tube M0 after internal transmission delay delta T, at the moment, the grid voltage V of the synchronous rectification MOS tube M0GIs Vdd. Due to the existence of the turn-on delay, the drain voltage V of the synchronous rectification MOS tube M0DThe signal is maintained for a small section-VFAfter a level rise, VFThe body diode conduction value of the synchronous rectification MOS tube M0 is obtained. When the drain voltage V of the synchronous rectification MOS transistor M0DWhen the voltage rises to minus 30mV, the LOGIC control module LOGIC controls the grid voltage V of the synchronous rectification MOS tube M0GDropping the drain voltage V of the synchronous rectification MOS transistor M0DCan be maintained at slightly lower than-30 mV for a long time, and the output signal T of the first negative voltage comparator CM1AThen goes high after a low pulse and the output signal T of the second negative voltage comparator CM2BThe drain voltage V of the synchronous rectification MOS transistor M0DHigher values below-4 mV are always obtained. With ISThe drain voltage V of the synchronous rectification MOS transistor M0 is continuously reduced to be close to 0DOutput signal T of the first negative voltage comparator CM1 higher than-4 mVAAnd the output signal T of the second negative voltage comparator CM2BThen the voltage is turned to be low, and the grid voltage V of the MOS tube M0 is synchronously rectifiedGIs pulled down to 0, and the synchronous rectification MOS tube M0 is turned off. In the whole DCM working process, the CCM CONTROL module CCM _ CONTROL outputs the maximum conduction time signal TONMAXIs always high and the maximum continuous conduction time signal TCONMAXThe voltage is always high and does not play any control role, wherein, 80mV, -30mV and-4 mV are optimized values of reference voltage, and in DCM mode, the dead time T isDEADIs the output signal T of the first negative voltage comparator CM1AAnd the output signal T of the second negative voltage comparator CM2BAll starting from high level to low levelSA time period that ends when the drop is 0.
Referring to fig. 3, fig. 3 shows a signal timing diagram of the synchronous rectification control circuit 10 operating in the current continuous conduction mode CCM, in operation, the primary MOS transistor MNOff, secondary current ISThe drain voltage V of the MOS tube M0 is linearly decreased and synchronously rectifiedDThe temperature of the molten steel rapidly drops down,when V isDBelow-80 mV, the output signal T of the first negative voltage comparator CM1ATurning from low to high, and turning on the synchronous rectification MOS tube M0 after internal transmission delay delta T, at the moment, the grid voltage V of the synchronous rectification MOS tube M0GIs Vdd. Due to the existence of the turn-on delay, the drain voltage V of the synchronous rectification MOS tube M0DThe signal is maintained for a small section-VFAfter a level rise, VFThe body diode conduction value of the synchronous rectification MOS tube M0 is obtained. When the drain voltage V of the synchronous rectification MOS transistor M0DWhen the voltage rises to minus 30mV, the LOGIC control module LOGIC controls the grid voltage V of the synchronous rectification MOS tube M0GDropping the drain voltage V of the synchronous rectification MOS transistor M0DCan be maintained at slightly lower than-30 mV for a long time, and the output signal T of the first negative voltage comparator CM1AThen goes high after a low pulse and the output signal T of the second negative voltage comparator CM2BThe drain voltage V of the synchronous rectification MOS transistor M0DHigh all the time after being lower than-4 mV, and maximum continuous conduction time signal TCONMAXAt the initially set maximum on-time
Figure BDA0002825141670000091
Maximum on-time signal T output by CCM CONTROL module CCM _ CONTROLONMAXThe grid voltage V of the synchronous rectification MOS tube M0 is inverted to be low and immediately pulled downGWhen the voltage reaches 0 ℃, the synchronous rectification MOS tube M0 is turned off, and the first dead time is passed
Figure BDA0002825141670000092
Rear, primary MOS transistor MNOn, the secondary current ISTurn-off, drain voltage V of synchronous rectification MOS tube M0DRises rapidly and is greater than-4 mV, the output signal T of the first negative comparator CM1AWith the output signal T of the second negative voltage comparator CM2BAll turn low to send the maximum continuous conduction time signal TCONMAXPulling up to complete the primary MOS transistor M of the periodNAnd waits for the next cycle. The CCM CONTROL module CCM _ CONTROL plays a role in adaptively increasing the maximum signal conduction time in the CCM working mode
Figure BDA0002825141670000093
When the system works stably, the demagnetization time is fixed, and the maximum signal conduction time is
Figure BDA0002825141670000094
Increasing the dead time
Figure BDA0002825141670000095
And decreases. Wherein, N represents a primary MOS transistor MNThe number of cycles of state change of (1), i.e. the primary MOS transistor MNThe period from first off to on is one period,
Figure BDA0002825141670000096
the reference voltage is preferably-80 mV, -30mV and-4 mV. Dead time
Figure BDA0002825141670000097
Is the maximum continuous conduction time signal TCONMAXTime of low level.
Referring to fig. 4, fig. 4 shows a schematic circuit diagram of an embodiment of the CCM control module. The CCM CONTROL module 11 includes a conduction signal modulation unit BLOCKA, the conduction signal modulation unit BLOCKA includes a third negative voltage comparator CM3, a first NMOS transistor MN1, a second NMOS transistor MN2, a first PMOS transistor MP1 and a fifth PMOS transistor MP5, a drain of the first NMOS transistor MN1 is connected to a first current source I1, a gate thereof is connected to an output terminal of a NOR gate NOR1, an output terminal of the modulation module 12 is connected to a first input terminal of the NOR gate NOR1 through a first Delay1, an output terminal of the modulation module 12 is connected to a second input terminal of the NOR gate NOR1, a source of the first NMOS transistor MN1 is connected to a second input terminal of the third negative voltage comparator CM3, and an output terminal of the third negative voltage comparator CM3 is used as an output terminal of the CCM CONTROL module _ contol to output a maximum conduction time signal T _ CONTROLONMAXA first input terminal of the third negative voltage comparator CM3 is connected to the drain of the second NMOS transistor MN2, the source of the second NMOS transistor MN2 is grounded, the gate thereof is connected to the output terminal of an inverting amplifier INV1, and the inverting amplifier INV1 is connected to the source of the second negative voltage comparator CM 8926An input end of the phase amplifier INV1 is connected to an output end of the second negative voltage comparator CM2, a second capacitor C2 is connected in parallel between a source and a drain of the second NMOS transistor MN2, a source of the first PMOS transistor MP1 is connected to a second current source I2, a drain of the first PMOS transistor MP1 is connected to a drain of the second NMOS transistor MN2, a gate of the first PMOS transistor MP1 is connected to an output end of the inverting amplifier INV1, a source of the fifth PMOS transistor MP5 is connected to a source of the first NMOS transistor MN1, a drain of the fifth PMOS transistor MP2 is connected to an output end of the second operational amplifier OP2, a first capacitor C1 is connected between a source and a drain of the fifth PMOS transistor MP5, and an inverting input end of the second operational amplifier OP2 is connected to a drain of the fifth PMOS transistor MP 5.
The CCM CONTROL module CCM _ CONTROL further includes an abnormal shielding unit BLOCKB connected to the on-signal modulation unit BLOCKA, and including a D flip-flop DFF1, a Pulse modulator Pulse1, a second Delay2, a third NMOS transistor MN3, and a second PMOS transistor MP2, a gate of the fifth PMOS transistor MP5 is connected to a reset input terminal of the D flip-flop DFF1 through the second Delay, a clock input terminal of the D flip-flop DFF1 is connected to an output terminal of the second negative voltage comparator CM2, a first input terminal of the D flip-flop DFF1 is connected to an output terminal of the modulation module 12, a first output terminal of the D flip-flop DFF1 is connected to a gate of the fifth PMOS transistor MP5 through the Pulse modulator Pulse1, a gate of the second PMOS transistor 2 is connected to a gate of the fifth PMOS transistor, a source of the second PMOS transistor MP5 is connected to a drain of the second NMOS transistor MP2, and a drain of the NMOS transistor MN3 is connected to a drain of the second NMOS transistor MN3, a grounded capacitor C3 is connected in parallel between the source of the second PMOS transistor MP2 and the non-inverting input terminal of the second operational amplifier OP2, the gate of the third NMOS transistor MN3 is connected to the gate of the fifth PMOS transistor MP5, the source thereof is grounded, and a fourth capacitor C4 is connected between the drain and the source of the third NMOS transistor MN 3.
In operation, the input signal at the non-inverting input of the second operational amplifier OP2 is assumed to be VREF1The input signal of the first input terminal of the third negative voltage comparator CM3 is
Figure BDA0002825141670000111
Where n represents the maximum continuous on-time signal TCONMAXThe number of drops from high to low, initially,
Figure BDA0002825141670000112
that is, the input signal of the first input terminal of the third negative voltage comparator CM3 and the input signal of the non-inverting input terminal of the second operational amplifier OP2 are both reference voltages. Input signal of a second input of the third negative voltage comparator CM3
Figure BDA0002825141670000113
n represents the number of times that the output signal of the second negative voltage comparator CM2 falls from high level to low level, and in CCM mode, during the on period of the first synchronous rectification MOS transistor M0, initially, the input signal of the second input terminal of the third negative voltage comparator CM3
Figure BDA0002825141670000114
Can be represented by formula (1):
Figure BDA0002825141670000115
at this time, the output signal of the CCM CONTROL module CCM _ CONTROL
Figure BDA0002825141670000116
Can be represented by equation (2):
Figure BDA0002825141670000117
referring to FIG. 3, the maximum keep-alive signal TCONMAXAnd the output signal T of the second negative voltage comparator CM2BIs dead time
Figure BDA0002825141670000118
Then the first current source I1 charges the first capacitor C1 during the conducting period of the first synchronous rectification MOS transistor M0Duration of electricity
Figure BDA0002825141670000119
Can be represented by equation (3):
Figure BDA00028251416700001110
wherein Td1 represents the Delay time of the first Delay unit Delay1,
Figure BDA0002825141670000121
for the first time the dead time is,
Figure BDA0002825141670000122
indicating the first charge time. At this time, the input signal of the second input terminal of the third negative voltage comparator CM3
Figure BDA0002825141670000123
Can be represented by equation (4):
Figure BDA0002825141670000124
the output signal of the CCM CONTROL module CCM _ CONTROL is in the on period of the second synchronous rectification MOS transistor M0
Figure BDA0002825141670000125
Can be represented by equation (5):
Figure BDA0002825141670000126
when the system works stably, the secondary demagnetization time is kept constant, and the output signal T of the second negative voltage comparator CM2BThe duration of the high level is not changed, so that the dead time can be obtained
Figure BDA0002825141670000127
Can be represented by equation (6):
Figure BDA0002825141670000128
wherein,
Figure BDA0002825141670000129
for the second dead time, Td1 represents the Delay time of the first Delay1,
Figure BDA00028251416700001210
for the first time the dead time is,
Figure BDA00028251416700001211
indicating the first charge time. Suppose that
Figure BDA00028251416700001212
Then the charging time of the first capacitor C1 by the first current source I1 in the conducting period of the second synchronous rectification MOS transistor M0
Figure BDA00028251416700001213
Can be represented by equation (7):
Figure BDA00028251416700001214
wherein Td1 represents the Delay time of the first Delay unit Delay1,
Figure BDA00028251416700001215
for the first time the dead time is,
Figure BDA00028251416700001216
which indicates the time of the first charge,
Figure BDA00028251416700001217
for the second time the dead time is,
Figure BDA00028251416700001218
represents the secondA sub-charging time. At this time, the input signal of the second input terminal of the third negative voltage comparator CM3
Figure BDA00028251416700001219
Can be represented by equation (8):
Figure BDA00028251416700001220
during the conducting period of the third synchronous rectification MOS tube M0, the output signal of the CCM CONTROL module CCM _ CONTROL
Figure BDA00028251416700001221
Can be represented by formula (9):
Figure BDA0002825141670000131
when the system works stably, the secondary demagnetization time is kept constant, and the output signal T of the second negative voltage comparator CM2BThe duration of the high level is not changed, so that the dead time can be obtained
Figure BDA0002825141670000132
Can be expressed by equation (10):
Figure BDA0002825141670000133
wherein,
Figure BDA0002825141670000134
for the third dead time, Td1 represents the Delay time of the first Delay1,
Figure BDA0002825141670000135
the first dead time. In the conducting period of the third synchronous rectification MOS transistor M0, the charging time of the first current source I1 to the first capacitor C1
Figure BDA0002825141670000136
Can be represented by formula (11):
Figure BDA0002825141670000137
wherein Td1 represents the Delay time of the first Delay unit Delay1,
Figure BDA0002825141670000138
for the first time the dead time is,
Figure BDA0002825141670000139
which indicates the time of the first charge,
Figure BDA00028251416700001310
the third dead time.
At this time, the input signal of the second input terminal of the third negative voltage comparator CM3
Figure BDA00028251416700001311
Can be represented by equation (12):
Figure BDA00028251416700001312
wherein,
Figure BDA00028251416700001313
which indicates the time of the first charge,
Figure BDA00028251416700001314
which indicates the time for the second charge,
Figure BDA00028251416700001315
indicating the third charge time.
During the conduction period of the fourth synchronous rectification MOS tube M0, the output signal of the CCM CONTROL module CCM _ CONTROL
Figure BDA00028251416700001316
Can be represented by equation (13):
Figure BDA00028251416700001317
when the system works stably, the secondary demagnetization time is kept constant, and the output signal T of the second negative voltage comparator CM2BThe duration of the high level is not changed, so that the dead time can be obtained
Figure BDA00028251416700001318
Can be represented by equation (14):
Figure BDA00028251416700001319
wherein,
Figure BDA0002825141670000141
for the fourth dead time, Td1 represents the Delay time of the first Delay1,
Figure BDA0002825141670000142
the first dead time.
By analogy, the n +1 th dead time
Figure BDA0002825141670000143
Can be represented by equation (15):
Figure BDA0002825141670000144
wherein, (1-K1)n-1Represents (1-K1) to the power of n-1. The (n + 1) th dead time
Figure BDA0002825141670000145
Can be represented by equation (16):
Figure BDA0002825141670000146
assuming a maximum continuous on-time signal TCONMAXThe time delay from the falling edge to the turn-off of the synchronous rectification MOS tube M0 is TOFF1Primary MOS transistor MNOpen the output signal T to the second negative voltage comparator CM2BHas a falling edge with a delay of TOFF2Then, the turn-off delay of the ordinary synchronous rectification chip can be expressed by equation (17):
TOFF＝TOFF1+TOFF2 (17)
the Delay time Td1 of the first Delay1 of the CCM CONTROL module CCM _ CONTROL of the present invention is controlled to be TOFFTherefore, the turn-off of the synchronous rectification MOS tube M0 and the primary MOS tube M can be realizedNThe high efficiency and high performance are realized by the conducting synchronous action of the switch.
In abnormal conditions, i.e. the output signal T of the second negative comparator CM2BHas a falling edge earlier than a preset maximum continuous conduction time signal TCONMAXThe falling edge of (c) may be in DCM or CCM mode.
Referring to FIG. 4, the maximum on-time signal TCONMAXAt a high level, the output signal T of the second negative voltage comparator CM2BThe falling edge triggers the first output terminal of the D flip-flop DFF1 to be inverted from a low level to a high level, and then a low pulse is generated, the low pulse controls the D flip-flop DFF1 to be reset after the Delay time Td2 of the second Delay unit Delay2, and simultaneously the low pulse enables the third capacitor C3 and the fourth capacitor C4 to be communicated, after the charges on the third capacitor C3 and the fourth capacitor C4 are balanced, the input signal of the non-inverting input terminal of the second operational amplifier OP2
Figure BDA0002825141670000151
Can be expressed by equation (18):
Figure BDA0002825141670000152
then, V is knownREF1First attenuation
Figure BDA0002825141670000153
Multiple, maximum on-time signal TONMAXAlso follows a decay and each anomaly detection will result in VREF1Attenuation of
Figure BDA0002825141670000154
Multiple, up to maximum continuous on time signal TCONMAXBefore the output signal T of the second negative voltage comparator CM2BAnd enters the operating range of the on signal modulation unit BLOCKA. At this time, the synchronous rectification control circuit 10 can operate efficiently in both the CCM mode and the DCM mode.
Referring to fig. 5, fig. 5 shows a circuit schematic of another embodiment of the CCM control module. The abnormal masking unit BLOCKB of the CCM control module 11 is different from the embodiment shown in fig. 4 in that the on-signal modulation unit BLOCKA is the same as the embodiment shown in fig. 4, and in this embodiment, the abnormal masking unit BLOCKB includes a D flip-flop DFF1, a Pulse modulator Pulse1, a second Delay2, a third Delay3, a first operational amplifier OP1, a third PMOS transistor MP3, a fourth PMOS transistor MP4 and a fourth NMOS transistor MN4, the gate of the fifth PMOS transistor MP5 is connected to the reset input terminal of the D flip-flop DFF1 through the second Delay2, the clock input terminal of the D flip-flop DFF 59648 is connected to the output terminal of the second negative voltage comparator CM2, the first DFF 63 1 of the D flip-flop is connected to the output terminal of the modulation module 12, the first output terminal of the D flip-flop DFF1 is connected to the drain terminal 68692 of the third PMOS transistor MP1 through the Pulse modulator Pulse 398, the output end of the first operational amplifier OP1 is connected to the source of a fourth PMOS transistor MP4, the drain of the fourth PMOS transistor MP4 is connected to the non-inverting input end of the second operational amplifier OP2, the gate thereof is connected to the gate of the fifth PMOS transistor MP5, a grounding capacitor C3 is connected in parallel between the drain of the fourth PMOS transistor MP4 AND the non-inverting input end of the second operational amplifier OP2, the inverting input end of the first operational amplifier OP1 is connected to the output end thereof, the source of the third PMOS transistor MP3 is connected to the source of the fourth NMOS transistor MN4, a fifth grounding capacitor C5 is connected in parallel between the source of the third PMOS transistor MP3 AND the source of the fourth NMOS transistor MN4, the drain of the fourth NMOS transistor MN4 is connected to a third current source I3, the gate thereof is connected to the output end of a third AND3, the output end of the second negative voltage comparator CM2 is connected to the third AND3, the output terminal of the second negative voltage comparator CM2 is connected to the second input terminal of the third AND gate AND3 through the third Delay device Delay 3.
Referring to FIG. 5, the maximum on-time signal TCONMAXAt a high level, the output signal T of the second negative voltage comparator CM2BThe falling edge triggers the first output terminal of the D flip-flop DFF1 to be inverted from low level to high level, and then a low pulse is generated, at this time, the third current source I3 charges the fifth capacitor C5, and the charging time is the secondary demagnetization time minus the Delay time Td1 of the first Delay1, that is, the output signal T2 of the second negative voltage comparator CM2BThe Delay time Td1 of the first Delay1 is subtracted from the high level duration, so that the charging time T of the fifth capacitor C5 isCHC5Can be represented by equation (19):
TCHC5＝TBH-Td1 (19)
wherein, TBHRepresenting the output signal T of the second negative voltage comparator CM2BThe duration of the high level. The voltage V across the fifth capacitor C5C5Can be represented by equation (20):
Figure BDA0002825141670000161
and the voltage V across the fifth capacitor C5C5The voltage is transmitted to the non-inverting input terminal of the second operational amplifier OP2 to obtain VREF1＝VC5Let I3 ═ I2, C5 ═ C2; the maximum on-time signal T of the next cycleONMAXCan be represented by equation (21):
TONMAX＝TBH-Td1 (21)
at this time, the synchronous rectification control circuit 10 can work efficiently in CCM mode or DCM mode more quickly by entering the working range of the on-signal modulation unit BLOCKA in one step, and the system efficiency is better.
In summary, the synchronous rectification control circuit compatible with the CCM and DCM working modes of the present invention combines the first negative voltage comparator with the first and gate and the second negative voltage comparator with the first or gate and the second and gate, and combines the CCM control module and the modulation module to adjust the signal output, thereby expanding the maximum on-time of the signal to realize the control of the extremely small dead time, and then uses the logic control module to perform logic control to effectively reduce the rectification conduction loss, realize the high efficiency of synchronous rectification, and further realize the synchronous rectification in the current continuous conduction mode CCM.
The foregoing is considered as illustrative of the preferred embodiments of the invention and is not to be construed as limiting the invention in any way. Various equivalent changes and modifications can be made by those skilled in the art based on the above embodiments, and all equivalent changes and modifications within the scope of the claims should fall within the protection scope of the present invention.

Claims (6)

1. A synchronous rectification control circuit compatible with CCM and DCM working modes is characterized by comprising a CCM control module, a first negative pressure comparator, a second negative pressure comparator and a logic control module, wherein the CCM control module is connected with the output end of the second negative pressure comparator, the first input end of the first negative pressure comparator and the second input end of the second negative pressure comparator are used as the input ends of the synchronous rectification control circuit, the output end of the first negative pressure comparator is connected with the first input end of a first AND gate, the output end of the first AND gate is connected with the first input end of the logic control module, the output end of the second negative pressure comparator is connected with the first input end of a first OR gate, the output end of the first OR gate is connected with the first input end of a second AND gate, the output end of the CCM control module and the output end of the second negative pressure comparator are respectively connected with the first input end and the second input end of a modulation module, the output end of the modulation module is connected with the second input end of the second AND gate, and the output end of the second AND gate is connected with the second input end of the logic control module.
2. The synchronous rectification control circuit with compatible CCM and DCM operation modes of claim 1 further comprising an LDO power module and a voltage and current bias module, the voltage and current bias module being coupled to the LDO power module to generate the reference voltage and the bias current.
3. The synchronous rectification control circuit with the CCM and DCM operation modes compatible as claimed in claim 1, wherein the CCM control module includes a conduction signal modulation unit, the conduction signal modulation unit includes a third negative voltage comparator, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor and a fifth PMOS transistor, the drain of the first NMOS transistor is connected to a first current source, the gate thereof is connected to the output terminal of a NOR gate, the output terminal of the modulation module is connected to the first input terminal of the NOR gate through a first delay, the output terminal of the modulation module is connected to the second input terminal of the NOR gate, the source of the first NMOS transistor is connected to the second input terminal of the third negative voltage comparator, the output terminal of the third negative voltage comparator serves as the output terminal of the CCM control module, and the first input terminal thereof is connected to the drain of the second NMOS transistor, the source electrode of the second NMOS tube is grounded, the grid electrode of the second NMOS tube is connected with the output end of a phase inversion amplifier, the input end of the phase inversion amplifier is connected with the output end of a second negative voltage comparator, a second capacitor is connected between the source electrode and the drain electrode of the second NMOS tube in parallel, the source electrode of the first PMOS tube is connected with a second current source, the drain electrode of the first PMOS tube is connected with the drain electrode of the second NMOS tube, the grid electrode of the first PMOS tube is connected with the output end of the phase inversion amplifier, the source electrode of the fifth PMOS tube is connected with the source electrode of the first NMOS tube, the drain electrode of the fifth PMOS tube is connected with the output end of a second operational amplifier, a first capacitor is connected between the source electrode and the drain electrode of the fifth PMOS tube, and the phase inversion input end of the second operational amplifier.
4. The synchronous rectification control circuit with the CCM and DCM operation modes being compatible as claimed in claim 3, wherein the CCM control module further includes an abnormal shielding unit, the abnormal shielding unit is connected to the conducting signal modulation unit and includes a D flip-flop, a pulse modulator, a second delay, a third NMOS transistor and a second PMOS transistor, the gate of the fifth PMOS transistor is connected to the reset input terminal of the D flip-flop through the second delay, the clock input terminal of the D flip-flop is connected to the output terminal of the second negative voltage comparator, the first input terminal of the D flip-flop is connected to the output terminal of the modulation module, the first output terminal of the D flip-flop is connected to the gate of the fifth PMOS transistor through the pulse modulator, the gate of the second PMOS transistor is connected to the gate of the fifth PMOS transistor, and the source thereof is connected to the non-inverting input terminal of the second operational amplifier, the drain electrode of the third NMOS tube is connected with the drain electrode of the third NMOS tube, a grounding capacitor is connected between the source electrode of the second PMOS tube and the non-inverting input end of the second operational amplifier in parallel, the grid electrode of the third NMOS tube is connected with the grid electrode of the fifth PMOS tube, the source electrode of the third NMOS tube is grounded, and a fourth capacitor is connected between the drain electrode of the third NMOS tube and the source electrode of the third NMOS tube.
5. The synchronous rectification control circuit with the CCM and DCM operation modes being compatible as claimed in claim 3, wherein the CCM control module further includes an abnormal shielding unit, the abnormal shielding unit is connected to the conducting signal modulation unit and includes a D flip-flop, a pulse modulator, a second delay, a third delay, a first operational amplifier, a third PMOS transistor, a fourth PMOS transistor and a fourth NMOS transistor, the gate of the fifth PMOS transistor is connected to the reset input terminal of the D flip-flop through the second delay, the clock input terminal of the D flip-flop is connected to the output terminal of the second negative voltage comparator, the first input terminal of the D flip-flop is connected to the output terminal of the modulation module, the first output terminal of the D flip-flop is connected to the gate of the third PMOS transistor through the pulse modulator, the drain of the third PMOS transistor is connected to the non-inverting input terminal of the first operational amplifier, the output end of the first operational amplifier is connected with the source electrode of a fourth PMOS tube, the drain electrode of the fourth PMOS tube is connected with the non-inverting input end of the second operational amplifier, the grid electrode of the fourth PMOS tube is connected with the grid electrode of the fifth PMOS tube, a grounding capacitor is connected between the drain electrode of the fourth PMOS tube and the non-inverting input end of the second operational amplifier in parallel, the inverting input end of the first operational amplifier is connected with the output end thereof, the source electrode of the third PMOS tube is connected with the source electrode of the fourth NMOS tube, a fifth capacitor with one end grounded is connected in parallel between the source electrode of the third PMOS tube and the source electrode of the fourth NMOS tube, the drain electrode of the fourth NMOS tube is connected with a third current source, the grid electrode of the first negative voltage comparator is connected with the output end of a first AND gate, the output end of the first negative voltage comparator is connected with the first input end of the first AND gate, and the output end of the second negative voltage comparator is connected with the second input end of the third AND gate through the third delayer.
6. The synchronous rectification control circuit with the CCM and DCM compatible operation modes as claimed in claim 1, wherein when the synchronous rectification control circuit is used for a flyback switching power supply, the output voltage of the flyback switching power supply is used as the power supply voltage of the synchronous rectification control circuit, the input end of the synchronous rectification control circuit is connected with the drain electrode of the synchronous rectification MOS transistor of the flyback switching power supply, the output end of the logic control module is connected with the gate electrode of the synchronous rectification MOS transistor, and the source electrode of the synchronous rectification MOS transistor is grounded.
CN202011446994.1A 2020-12-09 2020-12-09 Synchronous rectification control circuit compatible with CCM and DCM working modes Pending CN112542953A (en)

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