CN112542208B - SD NAND testing method and device, storage medium and terminal - Google Patents
SD NAND testing method and device, storage medium and terminal Download PDFInfo
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Abstract
The invention discloses an SD NAND testing method, device, storage medium and terminal, wherein through setting threads with different priorities, SD NAND FLASH is subjected to read-write verification according to the threads so as to realize read-write pressure testing of SD NAND FLASH; because each thread includes fixed data, when SD NAND FLASH has an error during the verification process, the type of error and the address of the error can be accurately located by the verification data to solve the problems that occur when SD NAND FLASH is conventionally read-write stress tested using third party tools.
Description
Technical Field
The invention relates to chip test equipment, in particular to an SD NAND test method, device, storage medium and terminal.
Background
The small capacity SD NAND FLASH (be a low-cost data memory, embedded high-speed SD controller and SLC NAND flash memory of high reliability, be applicable to consumer electronics, such as toy, bluetooth equipment, education electron and wearable equipment etc. use because of built-in SLC wafer, compare mainstream TF card and use MLC and TLC, the performance is more reliable and more stable, and built-in bad block management and ECC correction algorithm, the interface follows the SD agreement, product development cycle has been shortened greatly, wide application in fields such as intelligent audio amplifier, wearable, smart glasses and language module. SD NAND FLASH are generally directly attached to the board card, and once a fault occurs, the board card must be disassembled, so that the performance of SD NAND FLASH in the chip test link before the attachment is important.
In the conventional SD NAND FLASH test, most manufacturers still use a TF card conversion interface, access SD NAND FLASH to a computer through the conversion interface, and then use a third-party tool, such as a BurnInTest (computer stability test tool), a crystaldisk mark (hard Disk detection tool), an ATTO Disk Benchmark (Disk Benchmark test), to perform a read-write pressure test, because it is unclear that data in SD NAND FLASH is written in the third-party tool, once a problem occurs in the read-write pressure test process of SD NAND FLASH, a user cannot verify whether data written in SD NAND FLASH is wrong and the wrong type, and cannot locate SD NAND FLASH wrong addresses, which has a great defect.
Therefore, the prior art still needs to be improved and developed.
Disclosure of Invention
The invention aims to provide an SD NAND testing method, device, storage medium and terminal, and aims to solve the problem that a third-party tool cannot be used for positioning data and error addresses when a problem occurs in SD NAND FLASH in the conventional SD NAND FLASH test for performing read-write pressure test by using the third-party tool.
The technical scheme of the invention is as follows: an SD NAND testing method is disclosed, wherein the whole testing process is completed in a freertos operating system, and the SD NAND testing method specifically comprises the following steps:
s1: presetting a plurality of threads comprising certain data, and setting the priority of each thread;
s2: after a certain thread is successfully preempted, judging whether all data written into the thread in SD NAND FLASH is written, if so, jumping to S3, otherwise, jumping to S4;
s3: delete SD NAND FLASH all data for the thread and then jump to S4;
s4: performing read-write verification on SD NAND FLASH according to the data of the thread to obtain verification data;
s5: outputting the check data;
s6: and judging whether a test completion condition is triggered, if so, SD NAND FLASH finishing the test, and otherwise, jumping to S2.
The SD NAND test method, wherein the total data size of the data of the number of threads added up is equal to SD NAND FLASH capacity.
In the SD NAND test method, in S3, the process of deleting SD NAND FLASH all data of the thread is locked.
In the SD NAND test method, in S4, the process of performing read/write verification on SD NAND FLASH according to the data of the thread is locked.
In the SD NAND test method, the verification data includes a write operation return value, a read-write data comparison result, and SD NAND FLASH read-write verification addresses.
The SD NAND test method, wherein in S4, the specific process is as follows:
s 41: writing SD NAND FLASH the partial data of the thread to obtain the return value of the write operation;
s 42: reading out the data written in SD NAND FLASH in s41 to obtain a read operation return value;
s 43: comparing whether the data written in SD NAND FLASH in s41 is consistent with the data read out from SD NAND FLASH in s42 to obtain a read-write data comparison result;
s 44: and obtaining verification data according to the write operation return value, the read-write data comparison result and the address in SD NAND FLASH for executing the read-write verification.
According to the SD NAND testing method, the testing finish condition comprises that reading and writing verification is wrong or testing time reaches a preset value.
An SD NAND test device, comprising:
the thread presetting module is used for presetting a plurality of threads comprising certain data and setting the priority of each thread;
the data writing judging module is used for judging whether all data of a thread is written in SD NAND FLASH after a certain thread is successfully preempted;
a data delete module to delete SD NAND FLASH all data for the thread;
the read-write checking module is used for performing read-write checking on the SD NAND FLASH according to the data of the thread to obtain checking data;
the check data output module outputs check data;
and the condition triggering judgment module is used for judging whether a testing finishing condition is triggered or not.
A storage medium having stored therein a computer program which, when run on a computer, causes the computer to perform any of the methods described above.
A terminal comprising a processor and a memory, the memory having stored therein a computer program, the processor being adapted to perform the method of any preceding claim by invoking the computer program stored in the memory.
The invention has the beneficial effects that: the invention provides an SD NAND testing method, device, storage medium and terminal, wherein the read-write pressure test of SD NAND FLASH is realized by setting threads with different priorities and performing read-write verification on SD NAND FLASH according to the threads; because each thread includes fixed data, when SD NAND FLASH has an error during the verification process, the type of error and the address of the error can be accurately located by the verification data to solve the problems that occur when SD NAND FLASH is conventionally read-write stress tested using third party tools.
Drawings
FIG. 1 is a flow chart of the steps of the SD NAND test method of the present invention.
FIG. 2 is a schematic diagram of the internal module connection of the SD NAND testing device in the invention.
FIG. 3 is a schematic diagram of the external connection structure of the SD NAND testing device in the invention.
Fig. 4 is a schematic view of the apparatus of the present invention.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
As shown in fig. 1, an SD NAND test method, in which the whole test process is completed in a FreeRTOS (FreeRTOS is a mini real-time operating system kernel) operating system, specifically includes the following steps:
s1: presetting a plurality of threads comprising certain data, and setting the priority of each thread;
s2: after a certain thread is successfully preempted, judging whether all data written into the thread in SD NAND FLASH is written, if so, jumping to S3, otherwise, jumping to S4;
s3: delete SD NAND FLASH all data for the thread and then jump to S4;
s4: performing read-write verification on SD NAND FLASH according to the data of the thread to obtain verification data;
s5: outputting the check data;
s6: and judging whether a test completion condition is triggered, if so, SD NAND FLASH finishing the test, and otherwise, jumping to S2.
In some embodiments, the thread includes certain data, which may be set according to the test requirement, such as 0x00,0x 55, 0xaa, increment (meaning that the data is incremented according to 0x00,0x01,0x02,0x03,0x04,0x05, … …,0xfe,0 xff), decrement (meaning that the data is decremented according to 0xff,0xfe,0xfd,0xfc, … … 0x05,0x04,0x03,0x02,0x01,0x 00), and random number (the random number means that all data can be generated by a random function).
The data of the threads can be set according to actual test needs, for example, 4 threads are created, namely a thread a, a thread B, a thread C and a thread D, wherein the thread a has the highest priority, the thread B has the second priority, and the threads C and D have the same priority and the lowest priority.
To prevent multi-threaded writes from exceeding SD NAND FLASH capacity, the total data size of all threads summed is equal to SD NAND FLASH capacity. Meanwhile, before the SD NAND FLASH is subjected to read-write verification according to the data of the threads, whether all data of the corresponding threads are written in SD NAND FLASH is judged, if yes, locking and deleting are carried out, and SD NAND FLASH overflow is avoided.
In some embodiments, the process of deleting SD NAND FLASH all of the data for the thread is locked in order to avoid preemption by other threads when deleting data.
In some embodiments, to avoid preemption by other threads during read-write verification, the process of performing read-write verification on SD NAND FLASH according to the data of the thread is in a locked state.
In some embodiments, the verification data includes a write operation return value, a read-write data comparison result, SD NAND FLASH a read-write verification address, and the like. The write operation return value refers to whether the operation is normal or not when the data of a certain thread is written into SD NAND FLASH, and an error occurs when the operation is abnormal; the read operation return value indicates whether the operation is normal or not and an error occurs when the operation is not normal when the data written in SD NAND FLASH is read; the read/write data comparison result is a comparison SD NAND FLASH of whether the read data and the written data match each other, and if they do not match each other, an error occurs.
In some specific embodiments, in S4, the specific process is as follows:
s 41: writing SD NAND FLASH the partial data of the thread to obtain the return value of the write operation;
s 42: reading out the data written in SD NAND FLASH in s41 to obtain a read operation return value;
s 43: comparing whether the data written in SD NAND FLASH in s41 is consistent with the data read out from SD NAND FLASH in s42 to obtain a read-write data comparison result;
s 44: and obtaining verification data according to the write operation return value, the read-write data comparison result and the address in SD NAND FLASH for executing the read-write verification.
In some embodiments, the test completion condition may be set according to actual test requirements, for example, if there is an error in the read-write verification process, the SD NAND FLASH test is completed, and if there is no error in the read-write verification process, the SD NAND FLASH test is triggered to be completed after reaching a certain test time, for example, 7 days.
As shown in fig. 2 and 3, an SD NAND test device includes:
a thread presetting module 101 which presets a plurality of threads including certain data and sets priorities of the threads;
the data writing judging module 102, after a certain thread is preempted successfully, judges SD NAND FLASH whether all data of the thread have been written in;
the data deleting module 103 deletes SD NAND FLASH all data of the thread;
the read-write checking module 104 performs read-write checking on the SD NAND FLASH according to the data of the thread to obtain checking data;
a verification data output module 105 that outputs verification data;
the condition triggering and judging module 106 judges whether to trigger the test completion condition.
In some specific embodiments, the thread presetting module 101, the data writing judging module 102, the data deleting module 103, the read-write checking module 104, the verification data output module 105, and the condition triggering judging module 106 are integrated in a main control chip STM32F767, and the SD NAND FLASH is connected to the main control chip STM32F767 in an inserting manner.
In some embodiments, the SD NAND test apparatus further includes a Synchronous Dynamic Random Access Memory (SDRAM) for buffering SD NAND FLASH data for performing read/write verification.
In some embodiments, the SD NAND test device further comprises an LCD display screen for outputting verification data.
In some embodiments, the SD NAND test device further includes a power on/off KEY.
In some embodiments, the SD NAND test apparatus further includes a level shift chip USB-TTL Debug for USB serial port fault debugging.
Referring to fig. 4, an embodiment of the present invention further provides a terminal. As shown, the terminal 300 includes a processor 301 and a memory 302. The processor 301 is electrically connected to the memory 302. The processor 301 is a control center of the terminal 300, connects various parts of the entire terminal using various interfaces and lines, and performs various functions of the terminal and processes data by running or calling a computer program stored in the memory 302 and calling data stored in the memory 302, thereby performing overall monitoring of the terminal 300.
In this embodiment, the processor 301 in the terminal 300 loads instructions corresponding to one or more processes of the computer program into the memory 302 according to the following steps, and the processor 301 runs the computer program stored in the memory 302, so as to implement various functions: s1: presetting a plurality of threads comprising certain data, and setting the priority of each thread; s2: after a certain thread is successfully preempted, judging whether all data written into the thread in SD NAND FLASH is written, if so, jumping to S3, otherwise, jumping to S4; s3: delete SD NAND FLASH all data for the thread and then jump to S4; s4: performing read-write verification on SD NAND FLASH according to the data of the thread to obtain verification data; s5: outputting the check data; s6: and judging whether a test completion condition is triggered, if so, SD NAND FLASH finishing the test, and otherwise, jumping to S2.
Memory 302 may be used to store computer programs and data. The memory 302 stores computer programs containing instructions executable in the processor. The computer program may constitute various functional modules. The processor 301 executes various functional applications and data processing by calling a computer program stored in the memory 302.
An embodiment of the present application provides a storage medium, and when being executed by a processor, the computer program performs a method in any optional implementation manner of the foregoing embodiment to implement the following functions: s1: presetting a plurality of threads comprising certain data, and setting the priority of each thread; s2: after a certain thread is successfully preempted, judging whether all data written into the thread in SD NAND FLASH is written, if so, jumping to S3, otherwise, jumping to S4; s3: delete SD NAND FLASH all data for the thread and then jump to S4; s4: performing read-write verification on SD NAND FLASH according to the data of the thread to obtain verification data; s5: outputting the check data; s6: and judging whether a test completion condition is triggered, if so, SD NAND FLASH finishing the test, and otherwise, jumping to S2. The storage medium may be implemented by any type of volatile or nonvolatile storage device or combination thereof, such as a Static Random Access Memory (SRAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), an Erasable Programmable Read-Only Memory (EPROM), a Programmable Read-Only Memory (PROM), a Read-Only Memory (ROM), a magnetic Memory, a flash Memory, a magnetic disk, or an optical disk.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. An SD NAND testing method is characterized in that the whole testing process is completed in a freertos operating system, and specifically comprises the following steps:
s1: presetting a plurality of threads comprising certain data, and setting the priority of each thread;
s2: after a certain thread is successfully preempted, judging whether all data written into the thread in SD NAND FLASH is written, if so, jumping to S3, otherwise, jumping to S4;
s3: delete SD NAND FLASH all data for the thread and then jump to S4;
s4: performing read-write verification on SD NAND FLASH according to the data of the thread to obtain verification data;
s5: outputting the check data;
s6: and judging whether a test completion condition is triggered, if so, SD NAND FLASH finishing the test, and otherwise, jumping to S2.
2. The SD NAND test method of claim 1 wherein the total data size of the number of threads' data summed is equal to SD NAND FLASH capacity.
3. The SD NAND test method of claim 1 wherein in S3, the process of deleting SD NAND FLASH all data of the thread is locked.
4. The SD NAND test method of claim 1 wherein, in step S4, the process of performing read/write verification on SD NAND FLASH according to the data of the thread is locked.
5. The SD NAND test method of claim 1 wherein the check data comprises a write operation return value, a read-write data comparison result, and SD NAND FLASH read-write check addresses.
6. The SD NAND test method according to claim 5, wherein in the step S4, the specific process is as follows:
s 41: writing SD NAND FLASH the partial data of the thread to obtain the return value of the write operation;
s 42: reading out the data written in SD NAND FLASH in s41 to obtain a read operation return value;
s 43: comparing whether the data written in SD NAND FLASH in s41 is consistent with the data read out from SD NAND FLASH in s42 to obtain a read-write data comparison result;
s 44: and obtaining verification data according to the write operation return value, the read-write data comparison result and the address in SD NAND FLASH for executing the read-write verification.
7. The SD NAND test method of claim 5 wherein the test completion condition comprises a read/write verification error or a test time reaching a preset value.
8. An SD NAND test device, comprising:
the thread presetting module is used for presetting a plurality of threads comprising certain data and setting the priority of each thread;
the data writing judging module is used for judging whether all data of a thread is written in SD NAND FLASH after a certain thread is successfully preempted;
a data delete module to delete SD NAND FLASH all data for the thread;
the read-write checking module is used for performing read-write checking on the SD NAND FLASH according to the data of the thread to obtain checking data;
the check data output module outputs check data;
and the condition triggering judgment module is used for judging whether a testing finishing condition is triggered or not.
9. A storage medium having stored thereon a computer program which, when run on a computer, causes the computer to perform the method of any one of claims 1 to 7.
10. A terminal, characterized in that it comprises a processor and a memory, in which a computer program is stored, the processor being adapted to carry out the method of any one of claims 1 to 7 by calling the computer program stored in the memory.
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| CN106887256A (en) * | 2017-01-03 | 2017-06-23 | 航天科工防御技术研究试验中心 | The optimal inspection method and optimal inspection device of a kind of flash storage |
| CN111143218A (en) * | 2019-12-27 | 2020-05-12 | 深圳市共进电子股份有限公司 | Log debugging method and device suitable for 5G embedded equipment and readable storage medium |
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| CN106887256A (en) * | 2017-01-03 | 2017-06-23 | 航天科工防御技术研究试验中心 | The optimal inspection method and optimal inspection device of a kind of flash storage |
| CN111143218A (en) * | 2019-12-27 | 2020-05-12 | 深圳市共进电子股份有限公司 | Log debugging method and device suitable for 5G embedded equipment and readable storage medium |
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