CN112511120A

CN112511120A - Hall sensor reading circuit and electronic equipment

Info

Publication number: CN112511120A
Application number: CN202011288726.1A
Authority: CN
Inventors: 陈岚
Original assignee: Chip Blooming Corp
Current assignee: Shenzhen Qiuyu Electronic Co
Priority date: 2020-11-17
Filing date: 2020-11-17
Publication date: 2021-03-16
Anticipated expiration: 2040-11-17
Also published as: CN112511120B

Abstract

The invention provides a Hall sensor reading circuit and electronic equipment, wherein the circuit mainly comprises a two-phase rotating current control circuit, a chopper modulation demodulation circuit, a linear transconductance operational amplifier OTA, a gain-adjustable GM-C integrator, a low-pass filter LPF, a magnetic field direction control circuit and an offset voltage adjustable subtracter module, can effectively amplify the output signal of a Hall sensor with high precision, and eliminates offset voltage and interference noise in the output signal of the Hall sensor.

Description

Hall sensor reading circuit and electronic equipment

Technical Field

The invention relates to the technical field of electronic circuits, in particular to a low-noise low-offset linear Hall sensor reading circuit and electronic equipment.

Background

With the development of the fifth generation mobile communication, aircraft, and automobile industries and the development of new materials, the integrated circuit hall sensor has wide application in non-contact detection change of physical quantities such as magnetic field, pressure, position, displacement, velocity, acceleration, angle, angular velocity, current, and automatic control systems. However, in the automotive application field where high accuracy and high reliability are strict criteria, such as: the power system, the vehicle body device, the safety device, the electric power steering system and the like have higher index requirements on the performance of the linear Hall sensor, such as low offset, low noise, strong reliability, high sensitivity and the like.

The Hall sensor manufactured based on BiCMOS (Bipolar and CMOS) and BCD (Bipolar, CMOS and DMOS) processes has good compatibility, and the shallow trench isolation process technology (STI process) is adopted to realize lower temperature drift and stronger anti-noise capability of the Hall sensor. However, the voltage signal generated by the hall sensor is very weak, generally between several hundred microvolts and several millivolts, and a series of factors such as ambient operating temperature, electron hole mobility, design geometry factors, manufacturing process defects, packaging mechanical stress, injection concentration, device mismatch, mask dislocation and crystal face dislocation are added, so that the hall voltage signal is mixed with offset voltage and noise, and in addition, non-ideal factors such as offset voltage, thermal noise, flicker noise and the like introduced by a hall sensor reading circuit cause that the weak hall voltage signal cannot be correctly read. Therefore, the readout circuit is required to have not only a high-precision signal amplification capability but also the capability of eliminating offset voltage and interference noise.

Disclosure of Invention

In view of the above, embodiments of the present invention provide a hall sensor readout circuit and an electronic device, so as to achieve high-precision amplification of a hall sensor output signal and eliminate offset voltage and interference noise in the hall sensor output signal.

In order to achieve the above purpose, the embodiments of the present invention provide the following technical solutions:

a hall sensor readout circuit, comprising:

the input end of the two-phase rotating current control circuit is connected with the output end of the target Hall sensor;

the input end of the chopping modulation circuit is connected with the output end of the target Hall sensor;

the input end of the low-pass filter is connected with the output end of the chopper modulation circuit;

the input end of the magnetic field direction control circuit is connected with the output end of the low-pass filter;

the input end of the offset voltage adjustable subtracter is connected with the output end of the magnetic field direction control circuit;

the chopper modulation circuit comprises a modulation circuit and a demodulation circuit, wherein the input end of the modulation circuit is used as the input end of the chopper modulation circuit, and the output end of the demodulation circuit is used as the output end of the chopper modulation circuit;

the Hall sensor reading circuit further comprises:

and the linear transconductance operational amplifier, the gain-adjustable GM-C integrator and the first source follower are sequentially connected between the output end of the modulation circuit and the input end of the demodulation circuit in series.

Optionally, in the hall sensor readout circuit, the two-phase rotating current control circuit is configured to:

based on a variation period of a preset clock signal, a orthogonally rotated hall bias current from 0 degrees to 90 degrees is generated and supplied to the hall element.

Optionally, in the hall sensor readout circuit, the two-phase rotating current control circuit includes:

the first input end of the first constant current source is connected with an external power supply;

the input end of the first clock signal switch and the input end of the second clock signal switch are connected with the output end of the first constant current source, the output end of the first clock signal switch is connected with the first input interface of the Hall sensor, and the output end of the second clock signal switch is connected with the second input interface of the Hall sensor; the switch state of the first clock signal switch is controlled by a first clock signal, and the switch state of the second clock signal switch is controlled by a second clock signal;

the input end of the third clock signal switch is connected with the output end of the first clock signal switch, and the input end of the fourth clock signal switch is connected with the output end of the second clock signal switch; the switch state of the third clock signal switch is controlled by a first clock signal, and the switch state of the fourth clock signal switch is controlled by a second clock signal;

a first input end of the operational amplifier is connected with output ends of the third clock signal switch and the fourth clock signal switch, a second input end of the operational amplifier is input with a reference voltage, and an output end of the operational amplifier is connected with a second input end of the first constant current source;

the output end of the fifth clock signal switch is connected with the first output interface of the Hall sensor, the output end of the sixth clock signal switch is connected with the second output interface of the Hall sensor, the on-off state of the fifth clock signal switch is controlled by the first clock signal, and the on-off state of the sixth clock signal switch is controlled by the second clock signal.

Optionally, in the hall sensor readout circuit, the modulation circuit includes:

the input end of the first modulation clock switch is connected with the second input end of the Hall sensor, the input end of the second modulation clock switch is connected with the first input end of the Hall sensor, the input end of the third modulation clock switch is connected with the first output end of the Hall sensor, the input end of the fourth modulation clock switch is connected with the second output end of the Hall sensor, the input ends of the first modulation clock switch, the second modulation clock switch, the third modulation clock switch and the fourth modulation clock switch are used as the input end of the modulation circuit, and the output ends of the first modulation clock switch and the second modulation clock switch are used as the first output end of the modulation circuit, the output ends of the third modulation clock switch and the fourth modulation clock switch are used as the second output end of the modulation circuit;

a self-zeroing clock switch, a first input end of the self-zeroing clock switch is connected with output ends of the first modulation clock switch and the second modulation clock switch, and a second input end of the self-zeroing clock switch is connected with output ends of the third modulation clock switch and the fourth modulation clock switch;

and the input end of the first capacitor is connected with the output end of the self-zeroing clock switch, and the output end of the first capacitor is grounded.

Optionally, in the hall sensor readout circuit, the demodulation circuit includes:

the first dummy tube unit, the second dummy tube unit, the third dummy tube unit, the fourth dummy tube unit, the first demodulation clock switch, the second demodulation clock switch, the first RC filter circuit and the second RC filter circuit;

the input ends of the first dummy tube unit and the second dummy tube unit are used as the input ends of the demodulation circuit, the output end of the first dummy tube unit is connected with the input end of the first demodulation clock switch, and the output end of the second dummy tube unit is connected with the input end of the second demodulation clock switch;

the output ends of the third dummy tube unit and the fourth dummy tube unit are used as the output ends of the demodulation circuit, the input end of the third dummy tube unit is connected with the output end of the first demodulation clock switch, and the input end of the fourth dummy tube unit is connected with the output end of the second demodulation clock switch;

the first RC filter circuit is used for filtering the signal output by the output end of the third dummy tube unit, and the second RC filter circuit is used for filtering the signal output by the output end of the fourth dummy tube unit.

Optionally, in the hall sensor readout circuit, the linear transconductance operational amplifier includes:

the control end of the first MOS tube is connected with the first output end of the modulation circuit, and the control end of the second MOS tube is connected with the second output end of the modulation circuit;

the second constant current source is connected with the input end of the first MOS tube, and the third constant current source is connected with the input end of the second MOS tube;

the first end of the source degeneration resistor is connected with the input end of the first MOS tube, and the second end of the source degeneration resistor is connected with the input end of the second MOS tube;

a first input end of the second source follower is connected with an output end of the first MOS transistor, a second end input of the second source follower is connected with an output end of the second MOS transistor, a first output end of the second source follower is used as a first output end of the linear transconductance operational amplifier, and a second output end of the second source follower is used as a second output end of the linear transconductance operational amplifier;

a negative transconductance, a first input end of the negative transconductance being connected to a first output end of the second source follower, a second input end of the negative transconductance being connected to a second output end of the second source follower, a first output end of the negative transconductance being connected to an input end of the first MOS transistor, and a second output end of the negative transconductance being connected to an input end of the second MOS transistor;

the first input end of the fourth constant current source is connected with the output end of the first MOS tube, the first input end of the fifth constant current source is connected with the output end of the second MOS tube, and the output ends of the fourth constant current source and the fifth constant current source are grounded;

a first input end of the first error amplifier is used for obtaining a common-mode feedback signal, a second input end of the first error amplifier is used for obtaining a first reference signal, and an output end of the first error amplifier is connected with the fourth constant current source and a second input end of the fifth direct current source;

and the second capacitor is arranged between the first input end of the fourth constant current source and the output end of the first error amplifier, and the third capacitor is arranged between the first input end of the fifth constant current source and the output end of the first error amplifier.

Optionally, in the hall sensor readout circuit, the gain-adjustable GM-C integrator includes:

the control end of the third MOS tube is connected with the first output end of the modulation circuit, and the input end of the fourth MOS tube is connected with the second output end of the modulation circuit;

the control end of the fifth MOS tube and the control end of the sixth MOS tube are used for inputting preset signals, the output end of the fifth MOS tube is connected with the input end of the third MOS tube, and the output end of the sixth MOS tube is connected with the input end of the fourth MOS tube;

a sixth constant current source and a seventh constant current source, wherein a first output end of the sixth constant current source is connected with an input end of the fifth MOS transistor, a first output end of the seventh constant current source is connected with an input end of the sixth MOS transistor, an output end of the sixth constant current source is used as a first output end of the gain-adjustable GM-C integrator, and an output end of the seventh constant current source is used as a second output end of the gain-adjustable GM-C integrator;

the first resistor and the second resistor are connected between the output ends of the sixth constant current source and the seventh constant current source in series;

a first input end of the second error amplifier is connected with a common end of the first resistor and the second resistor and used for acquiring the common-mode feedback signal, a second input end of the second error amplifier is used for acquiring a second reference signal, and a second output end of the second error amplifier is connected with second input ends of the sixth constant current source and the seventh constant current source;

an input end of the eighth direct current source is connected with output ends of the third MOS tube and the fourth MOS tube, and an output end of the eighth direct current source is grounded;

and the output end of the first booster is connected with the input end of the eighth direct current source.

Optionally, in the hall sensor readout circuit, the magnetic field direction control circuit includes:

the input end of the third source follower is used as the input end of the magnetic field direction control circuit;

the first end of the first direction control switch is connected with the first output end of the third source follower, the first end of the second direction control switch is connected with the second output end of the third source follower, the first end of the third direction control switch is connected with the second end of the second direction control switch, the second end of the third direction control switch is connected with the first end of the first direction control switch, the first end of the fourth direction control switch is connected with the first end of the second direction control switch, and the second end of the fourth direction control switch is connected with the second end of the first direction control switch;

and a fourth source follower, wherein a first input end of the fourth source follower is connected with a second end of the first direction control switch, a second input end of the fourth source follower is connected with a second end of the second direction control switch, and an output end of the third source follower is used as an output end of the magnetic field direction control circuit.

Optionally, in the hall sensor readout circuit, the offset voltage adjustable subtractor includes:

the input end of the first operational amplifier is used as the input end of the offset voltage adjustable subtracter, and the output end of the operational amplifier is used as the output end of the offset voltage adjustable subtracter;

a second op-amp, a first input pad of the second op-amp for inputting a third reference signal,

the output end of the offset voltage trimmer is connected with the second input end of the second operational amplifier;

and the first end of the voltage division circuit is connected with the inverting input end of the first operational amplifier, the second end of the voltage division circuit is connected with the output end of the second operational amplifier, and the third end of the voltage division circuit is connected with the output end of the offset voltage trimmer.

An electronic device to which the hall sensor readout circuit according to any one of the above is applied.

Based on the technical scheme, the circuit provided by the embodiment of the invention mainly comprises a two-phase rotating current control circuit, a chopper modulation demodulation circuit, a linear transconductance operational amplifier OTA, a gain-adjustable GM-C integrator, a low-pass filter LPF, a magnetic field direction control circuit, an offset voltage adjustable subtracter and other modules. By adopting a two-phase rotating current technology and a chopping dynamic offset elimination technology, offset voltage signals and flicker noise can be effectively eliminated. Meanwhile, a high-linearity, low-offset and low-noise OTA (transconductance amplifier) is introduced to be used as the first-stage amplification of the detection circuit, so that the input linear range of the detection circuit is effectively improved; a GM-C integrator (transconductance capacitance integrator) with high gain, wide bandwidth and low offset is introduced to be used as the second-stage amplification of the detection circuit, so that a useful signal is effectively amplified, and a useless higher harmonic signal is filtered out. In addition, a double-channel time-sharing sampling technology is adopted, the positive Hall voltage signal and the negative Hall voltage signal are subjected to time-sharing sampling, and the linearly amplified Hall voltage signal is obtained by utilizing a subtracter, so that the high-precision amplification of the output signal of the Hall sensor is realized, and offset voltage and interference noise can be eliminated.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a hall sensor readout circuit disclosed in an embodiment of the present application;

fig. 2 is a schematic structural diagram of a two-phase rotating current control circuit in a hall sensor readout circuit disclosed in an embodiment of the present application;

fig. 3 is a schematic structural diagram of a modulation circuit in a hall sensor readout circuit disclosed in an embodiment of the present application;

fig. 4 is a schematic structural diagram of a chopper modulation circuit in a hall sensor readout circuit disclosed in an embodiment of the present application;

fig. 5 is a schematic structural diagram of a linear transconductance operational amplifier OTA in a readout circuit of a hall sensor disclosed in an embodiment of the present application;

FIG. 6 is a schematic structural diagram of a gain-adjustable GM-C integrator in a Hall sensor readout circuit disclosed in an embodiment of the present application;

FIG. 7 is a schematic diagram of a first gainer GAIN-TRIM according to an embodiment of the disclosure;

fig. 8 is a schematic structural diagram of a magnetic field direction control circuit in a hall sensor readout circuit disclosed in an embodiment of the present application;

FIG. 9 is a schematic structural diagram of a third source follower disclosed in an embodiment of the present application;

FIG. 10 is a schematic diagram of a fourth source follower according to the disclosure of the present application;

fig. 11 is a schematic structural diagram of an offset voltage adjustable subtractor in a hall sensor readout circuit disclosed in the embodiment of the present application;

fig. 12 is a schematic structural diagram of an OFFSET voltage trimmer OFFSET _ TRIM disclosed in the embodiment of the present application;

FIG. 13 is a schematic diagram of a Hall sensor readout circuit according to another embodiment of the present application;

FIG. 14 is a control timing diagram of clock control signals in a Hall sensor readout circuit;

fig. 15 is a waveform diagram of key signal transients in a hall sensor sensing circuit.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Compared with the traditional amplifier, the low-noise and low-offset chopping operational amplifier is a better choice. The chopper dynamic offset eliminating technology is a continuous time method, and aims to eliminate output offset voltage on a Hall element caused by thermal stress and mechanical pressure of temperature change.

Referring to fig. 1, a hall sensor readout circuit disclosed in an embodiment of the present application may include:

the two-phase rotating current control circuit 100, the chopper modulation circuit, the low pass filter LPF, the magnetic field direction control circuit 300, the offset voltage adjustable subtractor 400, the linear transconductance operational amplifier OTA, the gain adjustable GM-C integrator 500 and the first source follower 600, wherein the first source follower 600 is a double-end to single-end source follower, and a is 0.5;

the input end of the two-phase rotating current control circuit 100 is connected with the output end of the target Hall sensor;

the input end of the low pass filter LPF is connected with the output end of the chopper modulation circuit;

the input end of the magnetic field direction control circuit 300 is connected with the output end of the low pass filter LPF;

the input end of the offset voltage adjustable subtracter 400 is connected with the output end of the magnetic field direction control circuit 300;

the chopper modulation circuit comprises a modulation circuit 201 and a demodulation circuit 202, wherein the input end of the modulation circuit is used as the input end of the chopper modulation circuit, and the output end of the demodulation circuit is used as the output end of the chopper modulation circuit;

the linear transconductance operational amplifier OTA, the gain-adjustable GM-C integrator 500 and the first source follower 600 are sequentially connected in series between the output terminal of the modulation circuit and the input terminal of the demodulation circuit.

As can be seen from the foregoing embodiments, the linear hall sensor readout circuit disclosed in the embodiments of the present application mainly includes modules such as a two-phase rotating current control circuit 100, a chopper modulation/demodulation circuit, a linear transconductance operational amplifier OTA, a gain-adjustable GM-C integrator 500, a low-pass filter LPF, a magnetic field direction control circuit 300, and an offset voltage-adjustable subtractor 400. By adopting a two-phase rotating current technology and a chopping dynamic offset elimination technology, offset voltage signals and flicker noise can be effectively eliminated. Meanwhile, a linear transconductance operational amplifier OTA with high linearity, low offset and low noise is introduced to be used as the first-stage amplification of the circuit, so that the input linear range of the circuit is effectively improved; the high-gain, wide-bandwidth, low-offset gain-tunable GM-C integrator 500 is introduced as the second stage of the circuit for effectively amplifying the useful signal and filtering out unwanted higher harmonic signals. In addition, the two-phase rotating current control circuit 100 adopts a two-channel time-sharing sampling technology to perform time-sharing sampling on the positive hall voltage signal and the negative hall voltage signal, and the offset voltage adjustable subtracter 400 is used for obtaining the linearly amplified hall voltage signal, so that high-precision amplification of the output signal of the hall sensor is realized, and offset voltage and interference noise can be eliminated.

In the technical solution disclosed in the embodiment of the present application, the two-phase rotating current control circuit 100 is configured to: based on a variation period of a preset clock signal, a orthogonally rotated hall bias current from 0 degrees to 90 degrees is generated and supplied to the hall element. In addition, the present application also discloses a schematic structural diagram of each circuit module in the hall sensor readout circuit, for example, referring to fig. 2, the two-phase rotating current control circuit 100 disclosed in the embodiment of the present application may include:

a first constant current source I1, wherein a first input end of the first constant current source I1 is connected with an external power supply VDD;

a first clock signal switch S1 and a second clock signal switch S2, an input end of the first clock signal switch S1 and an input end of the second clock signal switch S2 are connected to an output end of the first constant current source I1, an output end of the first clock signal switch S1 is connected to a first input interface of the hall sensor, and an output end of the second clock signal switch S2 is connected to a second input interface of the hall sensor; the switch state of the first clock signal switch S1 is controlled by a first clock signal CLK +, and the switch state of the second clock signal switch S2 is controlled by a second clock signal CLK-;

a third clock signal switch S3 and a fourth clock signal switch S4, an input terminal of the third clock signal switch S3 being connected to an output terminal of the first clock signal switch S1, an input terminal of the fourth clock signal switch S4 being connected to an output terminal of the second clock signal switch S2; the switch state of the third clock signal switch S3 is controlled by a first clock signal CLK +, and the switch state of the fourth clock signal switch S4 is controlled by a second clock signal CLK-;

an operational amplifier U1, a first input terminal of the operational amplifier U1 is connected to output terminals of the third clock signal switch S3 and the fourth clock signal switch S4, a second input terminal of the operational amplifier U1 is input with a reference voltage VREF1, an output terminal of the operational amplifier U1 is connected to a second input terminal of the first constant current source I1, the reference voltage is an off-chip bias reference voltage, when in use, a proportional relation between a static output voltage of the linear hall sensor and an off-chip bias reference voltage of 50% can be set, and a hall bias current can be proportionally adjusted by the off-chip bias reference voltage;

the output end of the fifth clock signal switch S5 is connected to the first output interface of the hall sensor, the output end of the sixth clock signal switch S6 is connected to the second output interface of the hall sensor, the switching state of the fifth clock signal switch S5 is controlled by the first clock signal CLK +, and the switching state of the sixth clock signal switch S6 is controlled by the second clock signal CLK-.

The magnitude of the hall bias current provided by the two-phase rotating current control circuit 100 to the hall sensor can be proportionally adjusted by the off-chip bias reference voltage, and the direction of the hall bias current can be orthogonally rotated by 0 degree and 90 degrees by controlling the switches S1-S6 through the first clock signal CLK + and the second clock signal CLK-which are complementary with a preset frequency (for example, can be 200 KHZ).

In the above circuit, when the first clock signal CLK + is asserted, the switches S1, S3, S5 are closed, the hall bias current passes through the hall device via the direction D, B of the hall sensor, and the terminal A, C of the hall sensor is a positive hall voltage signal:

+Vhall＝VA-VC＝+ΔV+Vhall_os

(3-1)

in the circuit, when the second clock signal CLK-is active, the switches S2, S4 and S6 are closed, the Hall bias current passes through the Hall device in the direction A, C, and the terminal D, B is a negative Hall voltage signal:

-Vhall＝VD-VB＝-ΔV+Vhall_os (3-2)

then, subtracting the formula 3-1 from the formula 3-2 by a subtracter to obtain a final Hall voltage signal: vhall ═ Δ V (3-3)

Wherein, Δ V is the generated hall voltage signal, and Vhall _ os is the offset voltage of the hall device. When the clock signal changes periodically, the direction of the Hall bias current rotates orthogonally from 0 degree to 90 degrees, a positive Hall voltage signal and a negative Hall voltage signal are generated, the offset voltage Vhall _ os with the polarity unchanged all the time is generated, and then the offset voltage of the Hall device is eliminated through the subtracter.

Referring to fig. 3, the modulation circuit 201 may include:

a first modulation clock switch CH1, a second modulation clock switch CH2, a third modulation clock switch CH3 and a fourth modulation clock switch CH4, wherein the input end of the first modulation clock switch CH1 is connected with the second input end of the Hall sensor, the input end of the second modulation clock switch CH2 is connected with the first input end of the Hall sensor, the input end of the third modulation clock switch CH3 is connected with the first output end of the Hall sensor, the input end of the fourth modulation clock switch CH4 is connected with the second output end of the Hall sensor, the input ends of the first modulation clock switch CH1, the second modulation clock switch CH2, the third modulation clock switch CH3 and the fourth modulation clock switch CH4 are used as the input end of the modulation circuit, and the output ends of the first modulation clock switch CH1 and the second modulation clock switch CH2 are used as the first output end of the modulation circuit, the output ends of the third modulation clock switch CH3 and the fourth modulation clock switch CH4 are used as a second output end of the modulation circuit;

a self-zeroing clock switch CLK _ ZERO, a first input of said self-zeroing clock switch CLK _ ZERO being connected to outputs of said first modulation clock switch CH1 and said second modulation clock switch CH2, a second input of said self-zeroing clock switch CLK _ ZERO being connected to outputs of said third modulation clock switch CH3 and said fourth modulation clock switch CH 4;

a first capacitor C1, wherein the input end of the first capacitor C1 is connected with the output end of the self-zeroing clock switch CLK _ ZERO, and the output end of the first capacitor C1 is grounded.

Referring to fig. 3, the demodulation circuit includes:

a first DUMMY pipe unit DUMMY1, a second DUMMY pipe unit DUMMY2, a third DUMMY pipe unit DUMMY3, a fourth DUMMY pipe unit DUMMY4, a first demodulation clock switch CH5, a second demodulation clock switch CH6, a first RC filter circuit and a second RC filter circuit;

the input ends of the first DUMMY pipe unit DUMMY1 and the second DUMMY pipe unit DUMMY2 are used as the input ends of the demodulation circuit, the output end of the first DUMMY pipe unit DUMMY1 is connected with the input end of the first demodulation clock switch CH5, and the output end of the second DUMMY pipe unit DUMMY2 is connected with the input end of the second demodulation clock switch CH 6;

the output ends of the third DUMMY pipe unit DUMMY3 and the fourth DUMMY pipe unit DUMMY4 are used as the output ends of the demodulation circuit, the input end of the third DUMMY pipe unit DUMMY3 is connected with the output end of the first demodulation clock switch CH5, and the input end of the fourth DUMMY pipe unit DUMMY4 is connected with the output end of the second demodulation clock switch CH 6;

the first RC filter circuit is configured to filter a signal output by an output terminal of the third DUMMY pipe unit DUMMY3, and the second RC filter circuit is configured to filter a signal output by an output terminal of the fourth DUMMY pipe unit DUMMY4, as shown in fig. 4, where the RC filter circuit is formed by a capacitor and a resistor connected in parallel.

Specifically, the structure diagram of the demodulation circuit is shown in fig. 4, each of the first DUMMY tube unit DUMMY1, the second DUMMY tube unit DUMMY2, the third DUMMY tube unit DUMMY3, the fourth DUMMY tube unit DUMMY4, the first demodulation clock switch CH5, and the second demodulation clock switch CH6 is formed by an NMOS tube and a PMOS tube, wherein NMOS tubes in the first DUMMY tube unit DUMMY1, the second DUMMY tube unit DUMMY2, the third DUMMY tube unit DUMMY3, and the fourth DUMMY tube unit DUMMY4 are in accordance with the PMOS tube conduction states in the first demodulation clock switch CH5 and the second demodulation clock switch CH6, PMOS tubes in the first DUMMY tube unit DUMMY1, the second DUMMY tube unit DUMMY2, the third DUMMY tube unit DUMMY3, and the fourth DUMMY tube unit 4 are in accordance with the PMOS tube conduction states in the first demodulation clock switch CH 5827, the second DUMMY tube unit 1, the first demodulation clock switch 465, the third DUMMY tube unit DUMMY tube 465, and the fourth demodulation clock switch 465, the second DUMMY pipe unit DUMMY2, the fourth DUMMY pipe unit DUMMY4, and the second demodulation clock switch CH6 are controlled by a fourth clock signal.

Referring to fig. 3 and 4, in order to reduce the charge injection effect of the MOS switch, the chopper modulation demodulation circuit of the present invention introduces four techniques based on the conventional chopper:

(1) a DUMMY DUMMY tube unit is introduced and consists of an NMOS tube and a PMOS tube in a source-drain short circuit mode and is controlled by a switch tube complementary clock, when a demodulation clock switch is disconnected, the DUMMY tube unit corresponding to a branch circuit is conducted, channel charges are injected into the DUMMY tube units on two sides, the switch tube is isolated from an input capacitor of a rear-stage operational amplifier, and therefore the injection of the charges into the input capacitor of the rear-end operational amplifier is reduced, the injection mismatch of the charges is reduced, and a suppression effect is generated on a clock feed-through effect.

(2) NMOS and PMOS devices are combined such that opposite charge amounts are injected into each other by the two channels. As long as the injected charges of the NMOS and PMOS are guaranteed to be equal, namely:

WnLn (Vck-Vin-Vthn) ═ WpLp (Vck-Vin-l Vthp |), the opposite charge amounts can be exactly cancelled out.

(3) Differential operation is used to reduce charge injection. By using a differential sampling circuit, two differential signals with equal amplitude and opposite directions are generated, and when Vin1 is equal to Vin2, the charge quantity is eliminated.

(4) And inputting a maladjustment storage technology. When a modulation clock (marked as CH1) for controlling the first modulation clock switch and a modulation clock (marked as CH2) for controlling the second modulation clock switch and a modulation clock (marked as CH2) for controlling the fourth modulation clock switch, and a clock signal (marked as CH5) for controlling the first demodulation clock switch and a clock signal (marked as CH6) for controlling the second modulation clock switch are all off, the self-ZERO clock CLK _ ZERO is enabled, the switch CLK _ ZERO is closed, the input offset voltage of the operational amplifier and the residual offset voltage caused by a switch tube are stored, when the chopper works, the operational chopper is modulated to a high-frequency end and filtered by a low-pass filter LPF of a later stage, and therefore the purpose of eliminating the charge injection mismatch is achieved.

Referring to fig. 5, the linear transconductance operational amplifier OTA includes:

a first MOS transistor M1 and a second MOS transistor M2, a control terminal of the first MOS transistor M1 is connected to the first output terminal of the modulation circuit, and a control terminal of the second MOS transistor M2 is connected to the second output terminal of the modulation circuit;

a second constant current source I2 and a third constant current source I3, wherein the second constant current source I2 is connected with the input end of the first MOS transistor M1, and the third constant current source I3 is connected with the input end of the second MOS transistor M2;

a source degeneration resistor R0, wherein a first end of the source degeneration resistor R0 is connected with the input end of the first MOS transistor M1, and a second end of the source degeneration resistor R0 is connected with the input end of the second MOS transistor M2;

a second source follower a1, a first input end of the second source follower a1 is connected to an output end of the first MOS transistor M1, a second end input of the second source follower a1 is connected to an output end of the second MOS transistor M2, a first output end of the second source follower a1 is used as a first output end of the OTA, and a second output end of the second source follower a1 is used as a second output end of the OTA;

a negative transconductance-GM, a first input end of the negative transconductance-GM being connected to a first output end of the second source follower a1, a second input end of the negative transconductance-GM being connected to a second output end of the second source follower a1, a first output end of the negative transconductance-GM being connected to an input end of the first MOS transistor M1, and a second output end of the negative transconductance-GM being connected to an input end of the second MOS transistor M2;

a fourth constant current source I4 and a fifth constant current source I5, a first input end of the fourth constant current source I4 is connected with an output end of the first MOS transistor M1, a first input end of the fifth constant current source I5 is connected with an output end of the second MOS transistor M2, and output ends of the fourth constant current source I4 and the fifth constant current source I5 are grounded;

a first error amplifier U2, a first input terminal of the first error amplifier U2 is configured to obtain a common mode feedback signal, a second input terminal of the first error amplifier U2 is configured to obtain a first reference signal VREF2, and an output terminal of the first error amplifier is connected to the fourth constant current source I4 and a second input terminal of the fifth dc source;

a second capacitor C2 and a third capacitor C3, the second capacitor C2 is disposed between the first input terminal of the fourth constant current source I4 and the output terminal of the first error amplifier, and the third capacitor C3 is disposed between the first input terminal of the fifth constant current source I5 and the output terminal of the first error amplifier.

Referring to fig. 5, the circuit structure of the linear transconductance operational amplifier OTA mainly comprises a PNP input differential pair transistor (composed of a first MOS transistor and a second MOS transistor), a source follower a1, a negative transconductance-GM circuit, and an error amplifier U2, wherein a common mode feedback signal CMFB is provided by a tail current source common mode signal of a gain-adjustable GM-C integrator. Because the hall sensor signal is basically in a low frequency band, the signal amplitude is small, generally between hundreds of microvolts and several millivolts, and therefore, the offset voltage and the flicker noise of the back-end circuit become the most important factors influencing the amplification of the hall voltage signal. Meanwhile, as the process node of the integrated circuit is lower and lower, and in the face of the reduction of the power supply voltage, the aggravation of flicker noise and the increase of offset voltage, the noise and offset performance of the linear transconductance operational amplifier OTA positioned at the first stage of the circuit are the key for determining the success or failure of the whole detection amplifying circuit. Therefore, the invention introduces three techniques on the basis of the traditional transconductance operational amplifier OTA to reduce offset voltage and flicker noise.

(1) The first MOS tube and the second MOS tube can be PNP tubes, namely PNP type MOS tubes are used as differential input geminate transistors. Because the Hall voltage signal is lower, so choose PNP type transistor as the input geminate transistor, in addition, PNP transistor is better than NPN transistor matching nature, the maladjustment of introducing is lower, and the scintillation noise is less.

(2) With the emitter degeneration resistor R0, although the two tail current sources (the second constant current source I2 and the third constant current source I3) introduce some differential error, which subjects the output to higher noise (and offset voltage), the trade-off of the exponential increase in linearity is acceptable.

(3) A negative transconductance-GM circuit is added. In order to reduce the effects of noise and offset voltage, the present invention proposes an improved emitter degeneration linearization technique, as shown in fig. 5. After the differential input signal is amplified by the first error amplifier U2 and the second source follower A1, the differential output signal is fed back to two branches of the source degeneration resistor R0 through the negative transconductance-GM circuit, and the negative feedback is returned to automatically adjust the offset voltage caused by system offset and random offset and the larger noise and offset voltage caused by emitter degeneration linearization.

Referring to fig. 6, the gain tunable GM-C integrator 500 includes:

a third MOS transistor M3 and a fourth MOS transistor M4, a control terminal of the third MOS transistor M3 is connected to the first output terminal of the modulation circuit, and an input terminal of the fourth MOS transistor M4 is connected to the second output terminal of the modulation circuit;

a fifth MOS transistor M5 and a sixth MOS transistor M6, where a control end of the fifth MOS transistor M5 and a control end of the sixth MOS transistor M6 are used to input a preset reference voltage signal, an output end of the fifth MOS transistor M5 is connected to an input end of the third MOS transistor M3, and an output end of the sixth MOS transistor M6 is connected to an input end of the fourth MOS transistor M4;

a sixth constant current source I6 and a seventh constant current source I7, wherein a first output terminal of the sixth constant current source I6 is connected to an input terminal of the fifth MOS transistor M5, a first output terminal of the seventh constant current source I7 is connected to an input terminal of the sixth MOS transistor M6, an output terminal of the sixth constant current source I6 serves as a first output terminal of the gain-adjustable GM-C integrator 500, and an output terminal of the seventh constant current source I7 serves as a second output terminal of the gain-adjustable GM-C integrator 500;

a first resistor R1 and a second resistor R2, wherein the first resistor R1 and the second resistor R2 are connected in series between the output ends of the sixth constant current source I6 and the seventh constant current source I7;

a second error amplifier U3, a first input terminal of the second error amplifier U3 is connected to a common terminal of the first resistor R1 and the second resistor R2 for obtaining the common mode feedback signal, a second input terminal of the second error amplifier U3 is used for obtaining a second reference signal VREF3, and a second output terminal of the second error amplifier U3 is connected to second input terminals of the sixth constant current source I6 and the seventh constant current source I7;

an eighth direct current source I8, an input end of the eighth direct current source I8 is connected to output ends of the third MOS transistor M3 and the fourth MOS transistor M4, and an output end of the eighth direct current source I8 is grounded;

an output terminal of the first gainer GAIN-TRIM is connected to an input terminal of the eighth dc source I8.

Referring to fig. 6, the GAIN-adjustable GM-C integrator 500 circuit mainly includes an NPN differential input pair transistor (formed by the third MOS transistor M3 and the fourth MOS transistor M4), a common mode negative feedback detection circuit (formed by the resistor R1 and the resistor R2), a second error amplifier U3, and a first GAIN-TRIM. The integrator formed by the linear transconductor (OTA) and the capacitor is called GM-C integrator. The single-ended OTA and the fully-differential OTA have respective advantages, the single-ended OTA does not need to consider a common-mode negative feedback circuit, but is easily influenced by noise, and the output range is small. The fully-differential OTA has obvious advantages over single-ended OTAs, and has obvious suppression capability on offset and noise. The invention adopts a fully differential OTA single-capacitor balanced structure. The gain-tunable GM-C integrator 500 not only has a considerable gain and bandwidth, but also can handle higher signal frequencies, enabling undistorted amplification of hall voltage signals modulated to the chopping frequency. In addition, the transconductor outputs current without a low-impedance output stage like an operational amplifier, an internal circuit does not need an interstage Miller compensation capacitor, and an output pole Vout of the circuit is a dominant pole, so that the transconductor has good high-frequency characteristics. Because the gain-adjustable GM-C integrator 500 works in an open loop mode, the linear transconductance signal input range of the transconductor is closely related to the linearity, and the transconductor is linearized by adopting NPN pair transistors working in a subthreshold region as input stages. The invention also adjusts the gain value by adjusting the current magnitude of the tail current source. Referring to fig. 7, the first GAIN-TRIM can be fine-tuned by using the structure of the mirror current source, and satisfies the GAIN value from 200 to 300 by presetting the programmable adjustment bit.

Referring to fig. 8, the magnetic field direction control circuit 300 includes:

a third source follower A2, an input of the third source follower A2 being an input of the magnetic field direction control circuit 300;

a first direction control switch B _ DIR1, a second direction control switch B _ DIR2, a third direction control switch B _ DIR3 and a fourth direction control switch B _ DIR4, a first end of the first direction control switch B _ DIR1 is connected with a first output end of the third source follower A2, a first end of the second direction control switch B _ DIR2 is connected with a second output end of the third source follower A2, a first end of the third direction control switch B _ DIR3 is connected with a second end of the second direction control switch B _ DIR2, a second end of the third direction control switch B _ DIR3 is connected with a first end of the first direction control switch B _ DIR1, a first end of the fourth direction control switch B _ DIR4 is connected with a first end of the second direction control switch B _ DIR2, a first end of the fourth direction control switch B _ DIR4 is connected with a second end of the fourth direction control switch B _ DIR1, a of the third source follower a2 is 1;

a fourth source follower A3, a first input end of the fourth source follower A3 is connected to the second end of the first direction control switch B _ DIR1, a second input end of the fourth source follower A3 is connected to the second end of the second direction control switch B _ DIR2, an output end of the third source follower a2 serves as an output end of the magnetic field direction control circuit 300, and a of the fourth source follower A3 is equal to 1.

The structures of the third source follower a2 and the fourth source follower A3 can be set according to the needs of the user, for example, see fig. 9 for the third source follower a2, see fig. 10 for the fourth source follower A3, and fig. 9 and 10 are two different structure types of source followers, respectively.

The polarity of the hall voltage signal is related to the direction of the applied magnetic field and the direction of the generated hall bias current, as well as to the characteristics of the semiconductor material. When the direction of the applied magnetic field is the same as the direction of the current, the polarities of the Hall voltage signals generated by the N-type semiconductor material and the P-type semiconductor material are opposite. Because the hall sensor is applied to various modules, sometimes, in order to not change the structure of the original module, only the hall sensor is replaced, and the problem of polarity compatibility exists, so the magnetic field direction control circuit 300 is introduced in the invention, and the polarity can be adjusted according to the application condition only by configuring the magnetic field direction control signal B _ DIR. Referring to fig. 8, a magnetic field direction control circuit 300 is shown, which introduces two source followers for isolation in order not to affect the operation of the preceding and following stages. The rear-stage source follower is added with a negative feedback loop to reduce the system offset caused by the direction control switch tube and the random offset caused by the mismatch of devices. When the B _ DIR signal for controlling the first direction control switch and the second direction control switch is effective, the polarity of the Hall voltage signal is unchanged and is used as the input of the next stage; and when the B _ DIR signal for controlling the first direction control switch and the second direction control switch is invalid, the polarity of the Hall voltage signal is exchanged and is used as the input of the next stage, so that the aim of controlling the direction of the magnetic field is fulfilled.

Referring to fig. 11, the offset voltage adjustable subtractor 400 includes:

a first operational amplifier U4, an input terminal of the first operational amplifier being an input terminal of the offset voltage adjustable subtractor 400, and an output terminal of the operational amplifier being an output terminal of the offset voltage adjustable subtractor 400;

a second op amp U5, a first input of the second op amp U5 being solely for inputting a third reference signal VREF4,

an OFFSET voltage trimmer OFFSET _ TRIM, an output end of the OFFSET voltage trimmer OFFSET _ TRIM is connected to the second input end of the second operational amplifier U5, and a schematic structural diagram of the OFFSET voltage trimmer OFFSET _ TRIM may be shown in fig. 12;

a voltage dividing circuit, a first end of which is connected to the inverting input terminal of the first operational amplifier U4, a second end of which is connected to the output terminal of the second operational amplifier U5, and a third end of which is connected to the output terminal of the OFFSET voltage trimmer OFFSET _ TRIM, as shown in fig. 11, the voltage dividing circuit is composed of two voltage dividing resistors connected in series, and three ports of the voltage dividing circuit are respectively used as the first end, the second end, and the third end of the voltage dividing circuit.

The offset voltage adjustable subtractor 400 has a circuit structure as shown in fig. 11, and the circuit cooperates with the two-phase rotating current control circuit 100 to complete the elimination of the offset voltage of the hall device and obtain an amplified hall voltage signal. VOUT + a1a2 A3 Δ V or VOUT-a 1a2 A3 Δ V, the polarity of which is determined by the state of the field direction control signal B _ DIR. According to the invention, an OFFSET voltage trimmer OFFSET _ TRIM is added to a classical subtracter, and the proportional relation of the static output voltage of the linear Hall sensor and the off-chip bias reference voltage is set to be 50%. Because the offset of the hall device, the offset of the amplifying circuit, the residual offset voltage introduced by the switching tube, and the like cannot be completely eliminated by the chopper and the differential structure, and a certain error exists, the linear hall sensor reading circuit sets the static output voltage VOUT to 40% VREF in a default state, and then adjusts the static output voltage VOUT to 50% VREF by the offset voltage trimming module. The OFFSET voltage fine tuning module OFFSET _ TRIM adopts a structure of a mirror current source for fine tuning, and meets the requirement that the static output voltage VOUT changes from 40% VREF to 60% VREF through presetting programmable regulation bits.

In another integrated embodiment of the present application, combining the above specific circuits, a hall sensor sensing circuit is disclosed, referring to fig. 13, wherein the control timing of the sensing circuit in the circuit is shown in fig. 14, and the transient waveform of the critical signal of the sensing circuit in the circuit is shown in fig. 15, wherein V1 is the voltage difference between two input terminals of OAT, V2 is the voltage difference between two input terminals of GM-C, V3 is the voltage difference between two output terminals of GM-C, V4 is the voltage value of the output signal of the first source follower, V5+ is the voltage value output by the first output terminal of A3, V5+ is the voltage value output by the second output terminal of A3, and VOUT is the output signal of the hall sensor sensing circuit, wherein the direction of VOUT will change with the state setting of the signal B _ DIR of the magnetic field direction control circuit 300. The Hall device obtains two-phase bias current through two-phase rotating current control clocks CLK + and CLK-, generates corresponding positive Hall voltage signal + delta V and negative Hall voltage signal-delta V, and can generate offset voltage Vhall _ os and flicker noise voltage Vhall _ n generated by the Hall device at the same time, and then samples the positive Hall voltage signal and the negative Hall voltage signal output by the two-phase rotating current control circuit 100 and mixed with offset and noise respectively by adopting a chopping dynamic offset cancellation technology and a time-sharing sampling technology through a chopper circuit, wherein the working process is as follows: first, when the signal is not sampled, CLK _ ZERO enables, the chopper modulation clocks CH1, CH2 and demodulation clocks CH5, CH6 are all turned off, at this time, the positive and negative input terminals of the detection amplifying circuit composed of OTA and GM _ C are short-circuited and an input common mode level bias is provided through the first capacitor C1, and the input offset voltage Va1a2_ os and the input reference noise voltage Va1a2_ n of the detection amplifying circuit are stored in capacitors respectively connected to the two output terminals of the GM _ C integrator, and since the GM _ C integrator has a filtering function, higher harmonic noise components are filtered out. When sampling a positive hall voltage signal aliased with offset and noise, CLK _ ZERO is set to ZERO, chopper modulation clock CH1 is enabled, positive hall voltage signal + av, hall device offset voltage Vhall _ os, and flicker noise voltage Vhall _ n will be modulated to the high frequency side and amplified by the detection amplifier circuit, then, the chopping demodulation clock CH5 is enabled, the input offset voltage Va1a2_ os and the input reference noise voltage Va1a2_ n of the detection amplifying circuit are modulated to a high-frequency end, the amplified positive Hall voltage signal of the high-frequency end, the offset voltage of the Hall device and the flicker noise voltage are demodulated, after passing through a low-pass filter LPF, eliminating the input offset voltage and the input reference noise voltage of the detection amplifying circuit and the flicker noise voltage of the Hall device to obtain an amplified positive Hall voltage signal and an amplified Hall device offset voltage, wherein the amplified positive Hall voltage signal and the amplified Hall device offset voltage have the value of 0.5A 1A2 (+ delta V + Vhall _ os); when sampling a negative hall voltage signal aliased with offset and noise, CLK _ ZERO is set to ZERO, chopper modulation clock CH2 is enabled, the negative hall voltage signal-av, hall device offset voltage Vhall _ os, and flicker noise voltage Vhall _ n will be modulated to the high frequency side and amplified by the detection amplifier circuit, then, the chopping demodulation clock CH6 is enabled, the input offset voltage Va1a2_ os and the input reference noise voltage Va1a2_ n of the detection amplifying circuit are modulated to a high-frequency end, the amplified negative Hall voltage signal of the high-frequency end, the offset voltage of the Hall device and the flicker noise voltage are demodulated, after passing through a low-pass filter LPF, eliminating the input offset voltage and the input reference noise voltage of the detection amplifying circuit and the flicker noise voltage of the Hall device to obtain an amplified negative Hall voltage signal and an amplified offset voltage of the Hall device, wherein the amplified negative Hall voltage signal and the amplified offset voltage are 0.5A 1A2 (-delta V + Vhall _ os); then, the positive and negative signals are subtracted by a subtracter to eliminate the direct-current offset voltage of the Hall device, so that an amplified Hall voltage signal is obtained, the value of the amplified Hall voltage signal is +/-A1A 2A 3 delta V, and the positive and negative directions are determined by the state of a signal B _ DIR of the magnetic field direction control circuit 300.

Corresponding to the circuit, the application also discloses an electronic device, wherein the Hall sensor reading circuit can be applied to the electronic device, and the electronic device can be any known electronic device in the prior art.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A hall sensor sensing circuit, comprising:

the Hall sensor reading circuit further comprises:

2. The hall sensor sensing circuit of claim 1 wherein the two-phase rotating current control circuit is configured to:

3. The hall sensor sensing circuit of claim 2 wherein the two-phase rotating current control circuit comprises:

4. The hall sensor sensing circuit of claim 1 wherein the modulation circuit comprises:

5. The hall sensor sensing circuit of claim 1 wherein the demodulation circuit comprises:

6. The Hall sensor readout circuit of claim 4 wherein said linear transconductance operational amplifier comprises:

7. The Hall sensor readout circuit of claim 6 wherein said gain adjustable GM-C integrator comprises:

the control end of the fifth MOS tube and the control end of the sixth MOS tube are used for inputting a preset reference voltage signal, the output end of the fifth MOS tube is connected with the input end of the third MOS tube, and the output end of the sixth MOS tube is connected with the input end of the fourth MOS tube;

8. The hall sensor sensing circuit of claim 1 wherein the magnetic field direction control circuit comprises:

9. The hall sensor sensing circuit of claim 1 wherein the offset voltage adjustable subtractor comprises:

10. An electronic device, characterized in that a hall sensor read-out circuit according to any of claims 1-9 is applied.