CN112511108A

CN112511108A - Design method compatible with LDMOS and GaN power amplifier

Info

Publication number: CN112511108A
Application number: CN202011378230.3A
Authority: CN
Inventors: 俞启进; 张力; 董昊; 李江舟
Original assignee: Nanjing Digitgate Technology Co ltd
Current assignee: Nanjing Digitgate Technology Co ltd
Priority date: 2020-12-01
Filing date: 2020-12-01
Publication date: 2021-03-16

Abstract

The invention provides a design method compatible with LDMOS and GaN power amplifiers, which comprises the following steps: and the GaN power supply circuit and the LDMOS power supply circuit are subjected to compatibility design by optimizing the design of the power supply circuit. The working state of the power amplifier is regulated through a positive voltage DAC or a similar voltage regulating circuit (such as a voltage dividing circuit); through the design of an adder, the DAC control voltage is added with a 0 level or a negative voltage level, and the working states of LDMOS positive voltage and GaN negative voltage are compatible through the switching of a control center; the compatibility of GaN and LDMOS is realized by controlling the drain switch.

Description

Design method compatible with LDMOS and GaN power amplifier

Technical Field

The invention relates to the technical field of communication, in particular to a power amplifier technology.

Background

With the expansion of the working frequency band of the 5G service from 600MHz to 6G, different design schemes are often adopted for the low frequency band and the high frequency band, and the different schemes mean one set of more platforms, so that the debugging difficulty and cost of the design are greatly increased, and the investment of peripheral resources is increased.

When the frequency is lower than 3.5GHz, the LDMOS power amplifier has the characteristics of simple design method, lower cost and easiness in implementation, meanwhile, the LDMOS power amplifier performance is similar to that of a GaN power amplifier, and the LDMOS power amplifier is generally adopted in a frequency band lower than 3.5GHz in consideration of cost and simplification of design.

When the frequency is higher than 3.5GHz, the LDMOS power amplifier has a larger difference in performance compared with a GaN power amplifier, and when the frequency is higher than 5GHz, the output power of the LDMOS can be greatly reduced, so that the requirements of a plurality of scenes cannot be met. In order to meet the design requirement, when the frequency is more than 3.5GHz, the high-power amplifier mainly uses a GaN power amplifier.

In order to meet the requirements of reducing cost and design difficulty, the method enables the LDMOS and the GaN power amplifiers to be compatible, the power amplifier types are selected through an I/O port, the design difficulty is greatly reduced, meanwhile, multiple power amplifiers can be compatible on the basis of one platform, and the loss of matched resources is greatly reduced.

Disclosure of Invention

In view of the above technical problems, the present invention aims to provide a design method compatible with a power amplifier controlled by positive voltage such as LDMOS and a power amplifier controlled by negative voltage such as GaN.

In order to solve the technical problems, the technical method adopted by the invention is as follows: a design method compatible with LDMOS and GaN power amplifiers comprises the following steps:

1, the control center I/O is switched to low level, the system is in LDMOS state, switch SW2 is grounded, switch SW1 is closed and turned on, and the drain supply VDD is powered on. Switch SW3 switches to ground, at which time the amplifier gate voltage is positive at the DAC output. The LDMOS realizes normal operation.

2, the control center I/O is switched to a high level, the system works in a GaN state at the moment, the switch SW2 is suspended at the moment, the switch SW1 is closed and conducted only when the negative voltage generation module generates the REG mark signal, and the drain supplies power to VDD and is electrified. The switch SW3 is switched to VSS, the power amplifier grid voltage is the sum of the positive voltage output by the DAC and the VSS negative voltage, the absolute value of the VSS is larger than the output of the DAC, and the negative voltage control is realized. The GaN achieves normal operation.

The invention has the following beneficial effects: the design resources and the product cost are reduced; and the design complexity is reduced.

Drawings

FIG. 1 is a schematic block diagram of an embodiment of the present invention.

Detailed Description

The present invention will be further described with reference to the following embodiments for the purpose of facilitating understanding of those skilled in the art.

Example (b):

in the design method for compatible LDMOS and GaN power amplifier of the embodiment, the compatibility design of the power amplifier is performed by the LDMOS of the 3.5GHz working frequency band and the GaN power amplifier of the 4.9GHz working frequency band through the method mentioned in the text.

Except that power amplifier part circuit carries out solitary design, all the other peripheral control parts carry out compatible design through this scheme, greatly reduced follow-up cloth board, control, the work load of production.

Switch SW1 is low; floating or high level off. Switch SW2 is low; floating or high level off. Switch SW3 low ground; the high level is connected with the negative voltage VSS.

In this embodiment, the switch state is only one of the operating states, and other operating states and modules in which the peripheral circuit can implement the switching function are also within the scope of the present invention.

The negative pressure generation module provides negative pressure required by GaN, can provide negative pressure of-5V, 10V and the like according to different types of power amplifiers, provides a negative pressure output completion mark REG after negative pressure output is completed, and clears the mark when the output negative pressure is less than 5% of the set negative pressure.

In this embodiment, the negative voltage generating module with the flag bit is only one state, and other combined circuits or modules can achieve the function of generating the flag by outputting the negative voltage, which also falls within the protection scope of the present invention.

LDMOS and GaN power amplifier parts refer to positive-voltage control LDMOS power amplifier and negative-voltage control GaN power amplifier. The method is also suitable for controlling the power amplifier by other types of positive and negative grid voltages.

The adder module realizes the adjustability of the grid voltage of the power amplifier and the adjustability of the grid voltage compatible with the GaN negative pressure, and realizes the compatibility of the LDMOS and the GaN power amplifier through the switching of the voltage 0 and the negative pressure VSS.

The adder module of this embodiment realizes the switching between negative pressure control and positive pressure control, and other similar modules are also within the protection scope of the present invention.

And the grid voltage control module is used for realizing the adjustability of the grid voltage of the output of the power amplifier. The method can be realized by using a DAC, a voltage division resistor, a PWM (pulse-width modulation) wave filter and the like, and is not limited to the three methods.

And the control center MCU is used for realizing the switching of the LDMOS and the GaN and the control and adjustment of the grid voltage. The fixed mechanical or electronic switch can also realize the power amplifier switching mode. And are not limited to these two control methods.

The specific control process is as follows:

1, the I/O of the control center is switched to a low level, the 3.5GHz power amplifier works at the moment, the switch SW2 is grounded at the moment, the switch SW1 is closed and conducted, and the drain power supply VDD is electrified. Switch SW3 switches to ground, at which time the amplifier gate voltage is positive at the DAC output. The 3.5GHz LDMOS power amplifier can work normally.

2, the control center I/O is switched to a high level, the 4.9GHz power amplifier works at the moment, the switch SW2 is suspended, the switch SW1 is closed and conducted only when the negative pressure generation module generates the REG mark signal, and the drain electrode supplies power to VDD and is electrified. The switch SW3 is switched to negative voltage VSS, at the moment, the power amplifier grid voltage is the sum of positive voltage output by the DAC and VSS negative voltage, and the absolute value of VSS is larger than the output of the DAC, so that negative voltage control is realized. The normal work of the GaN power amplifier of 4.9GHz is realized.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way, and any insubstantial modifications or equivalent changes made by those skilled in the art to the preparation technology of the present invention without departing from the scope of the experimental process of the present invention are still within the scope of the claims of the present invention.

Claims

1. A design method compatible with LDMOS and GaN power amplifier is provided, wherein LDMOS power amplifier refers to positive-pressure control LDMOS power amplifier, GaN power amplifier refers to negative-pressure control GaN power amplifier; the method is characterized in that:

the working state of the power amplifier is regulated through a positive voltage DAC or a similar voltage regulating circuit (such as a voltage dividing circuit); through the design of an adder, the DAC control voltage is added with a 0 level or a negative voltage level, and the working states of LDMOS positive voltage and GaN negative voltage are compatible through the switching of a control center; the compatibility of GaN and LDMOS is realized by controlling the drain switch.

2. The design method of the compatible LDMOS and GaN power amplifier of claim 1, wherein:

switch SW1 is closed at low level and open at floating or high level;

switch SW2 is closed at low level and open at floating or high level;

the switch SW3 is grounded at low level and connected to negative voltage VSS at high level.

3. The design method of the compatible LDMOS and GaN power amplifier of claim 1, wherein:

the negative pressure generation module provides negative pressure required by the GaN, when the negative pressure output is completed, the negative pressure generation module provides a negative pressure output completion mark REG, and when the output negative pressure is smaller than a set negative pressure threshold value, the mark bit is cleared.

4. The design method of the compatible LDMOS and GaN power amplifier of claim 1, wherein:

the grid voltage of the power amplifier is adjustable through the adder, meanwhile, the grid voltage of the compatible GaN negative voltage is adjustable, and the compatibility of the LDMOS and the GaN power amplifier is realized through the switching of the voltage 0 and the negative voltage VSS.

The grid voltage control realizes the adjustability of the output grid voltage of the power amplifier, and the grid voltage control is realized by using a DAC (digital-to-analog converter), a divider resistor or a PWM (pulse-width modulation) wave filter;

and the control center MCU is used for realizing the switching of the LDMOS and the GaN and the control and adjustment of the grid voltage.

5. The design method of a compatible LDMOS and GaN power amplifier of any of claims 1 to 4, wherein:

when the control center I/O is switched to a low level, the system works in an LDMOS state, the switch SW2 is grounded, the switch SW1 is closed and conducted, and the drain is powered on VDD; the switch SW3 is switched to the ground, and the grid voltage of the power amplifier is the positive voltage output by the DAC at the moment; the LDMOS realizes normal operation;

the I/O of the control center is switched to a high level, the system works in a GaN state at the moment, the switch SW2 is suspended at the moment, the switch SW1 is closed and conducted only when the REG mark signal is generated by the negative pressure generation module, and the drain electrode supplies power to VDD and is electrified; the switch SW3 is switched to VSS, the power amplifier grid voltage is the sum of positive voltage output by the DAC and VSS negative voltage at the moment, and the absolute value of VSS is larger than the output of the DAC, so that negative voltage control is realized; the GaN achieves normal operation.