CN112509971B - Method for manufacturing isolation structure - Google Patents
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- CN112509971B CN112509971B CN201910867622.7A CN201910867622A CN112509971B CN 112509971 B CN112509971 B CN 112509971B CN 201910867622 A CN201910867622 A CN 201910867622A CN 112509971 B CN112509971 B CN 112509971B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
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Abstract
The application discloses a method for manufacturing an isolation structure. The manufacturing method includes forming an active region in a first region and a second region on a substrate using a first photoresist mask, the first region and the second region being adjacent to each other; shielding a second region of the substrate by using a second photoresist mask, and forming a first well region of a first doping type in a first region of the substrate; shielding a second area of the substrate by adopting a second photoresist mask, forming a compensation area of the first doping type on part of the surface of the first well area of the first doping type by adopting the active area as a hard mask, and then removing the second photoresist mask; the active region is used as a hard mask and extends downwards along the surface of the substrate between the first region and the second region to form an isolation structure, and the compensation region is in contact with at least part of the isolation structure. The first well region and the compensation region are respectively formed by adopting the same photoresist mask, so that the isolation effect is enhanced without adding a mask and a photoetching step on the basis of not influencing the performance of a semiconductor device.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and more particularly, to a method for manufacturing an isolation structure in a semiconductor device.
Background
In an integrated circuit, to ensure the performance of each semiconductor device, adjacent semiconductor structures are generally isolated by forming isolation structures during the manufacturing process of the semiconductor devices.
In the prior art, an isolation structure is mainly formed in a semiconductor device through a local silicon oxide isolation process and a shallow trench isolation process. Compared with the shallow trench isolation process, the local silicon oxide formed by the local silicon oxide isolation process is large in thickness and good in isolation effect.
However, in the process of forming the isolation structure through the local silicon oxide isolation process, the high thickness of the local silicon oxide absorbs boron and discharges phosphorus, which in turn may cause the isolation effect of the isolation structure to be poor.
Disclosure of Invention
In view of the above, the present application provides a method for manufacturing an isolation structure of a semiconductor device.
According to an aspect of the present invention, there is provided an isolation structure manufacturing method, including: forming an active region in a first region and a second region on a substrate using a first photoresist mask, the first region and the second region being adjacent to each other; removing the first photoresist mask, shielding the second region of the substrate by adopting a second photoresist mask, and forming a first well region of a first doping type in the first region of the substrate; shielding a second region of the substrate by using the second photoresist mask, forming a compensation region of the first doping type on part of the surface of the first well region of the first doping type by using the active region as a hard mask, and removing the second photoresist mask; and taking the active region as a hard mask, extending downwards along the surface of the substrate between the first region and the second region to form an isolation structure, wherein the compensation region is in contact with at least part of the isolation structure.
Preferably, the isolation structure is a field oxide region or a trench.
Preferably, the implantation energy of the dopant of the first doping type forming the first well region is such that the dopant is able to penetrate the active region.
Preferably, the dopant of the first doping type forming the compensation region is a phosphorus fluoride ion, and the implantation energy of the dopant is such that the dopant cannot penetrate the active region.
Preferably, in the process of forming the first well region, a process of multiple high energy implantations is adopted to form the first well region.
Preferably, the method further comprises the following steps: before the step of forming the active region, a third photoresist mask is adopted to shield a first region of the substrate, a second well region of a second doping type is formed in a second region on the substrate, the first doping type is opposite to the second doping type, and the second well region and the first well region are adjacent to each other.
Preferably, in the process of forming the second well region, a step difference is formed on the surface of the substrate.
Preferably, the method further comprises the following steps: between the steps of forming the active region and forming the first well region, a third photoresist mask is used for shielding a first region of the substrate, a second well region of a second doping type is formed in a second region on the substrate, the first doping type is opposite to the second doping type, and the second well region and the first well region are adjacent to each other.
Preferably, in the process of forming the second well region, a process of high energy implantation is adopted to form the second well region.
Preferably, the method further comprises the following steps: after the step of forming the isolation structure, removing the active region.
Preferably, the step of forming the active region includes: forming an oxide layer on the substrate; forming a nitride layer on the oxide layer; and etching the nitride layer and the oxide layer by adopting a first photoresist mask for shielding so as to expose partial surfaces of the first area and the second area of the substrate.
Preferably, the oxide layer is a silicon dioxide layer, and the nitride layer is a silicon nitride layer.
Preferably, the first doping type is P-type.
Preferably, the isolation structure is formed in the semiconductor device for isolating two adjacent well regions or two adjacent doped regions or adjacent well regions and doped regions.
Preferably, the semiconductor device includes, but is not limited to: BCD devices, bi-CMOS devices, CMOS devices.
The invention provides a manufacturing method of an isolation structure, which is characterized in that active regions are formed in a first region and a second region on a substrate, then the same photoresist mask is adopted, and a well region of a first doping type and a compensation region of the first doping type positioned on at least part of the surface of the well region of the first doping type are respectively formed in sequence through implantation of dopants with different implantation energies and different doping dosages, so that the isolation structure formed on the surface of the first well region and extending downwards is contacted with the compensation region, the phenomenon that the doping of the well region of the first doping type is lightened due to the formation of the isolation structure is avoided, the compensation region is formed on at least part of the surface of the first well region without additional mask and photoetching steps on the basis of not influencing the performance of a semiconductor device, and the isolation effect of the isolation structure is enhanced. Isolation structures can be formed between adjacent well regions, between adjacent doped regions, and between well regions and doped regions adjacent to each other in the semiconductor device to perform an isolation function.
The method for manufacturing the isolation structure can be used for forming the isolation structure in a semiconductor device such as CMOS, bi-CMOS, BCD and the like.
Drawings
The above and other objects, features and advantages of the present application will become more apparent from the following description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 shows a schematic flow chart of a method for manufacturing an isolation structure according to a first embodiment of the present invention.
Fig. 2A to 2G are schematic structural diagrams showing each specific step in the manufacturing process of the isolation structure of the first embodiment.
Fig. 3 is a flow chart showing a method for manufacturing an isolation structure according to a second embodiment of the present invention.
Fig. 4A to 4G are schematic structural diagrams showing each specific step in the manufacturing process of the isolation structure of the second embodiment.
Detailed Description
The present application will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown.
Numerous specific details of the present application are set forth below in order to provide a more thorough understanding of the present application. However, as will be understood by those skilled in the art, the present application may be practiced without these specific details.
When a layer, a region, or a region is referred to as being "on" or "over" another layer, another region, or a region may be directly on or over the other layer, the other region, or another layer or a region may be included between the layer and the other layer or the other region. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.
If for the purpose of describing the situation directly above another layer, another region, the expression "a directly above B" or "a above and adjacent to B" will be used herein. In the present application, "a is directly in B" means that a is in B and a and B are directly adjacent, rather than a being in a doped region formed in B.
In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of semiconductor devices, are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
Fig. 1 shows a schematic flow chart of a method for manufacturing an isolation structure according to a first embodiment of the present invention. Fig. 2A to 2G are schematic structural diagrams showing each specific step in the manufacturing process of the isolation structure of the first embodiment.
As shown in fig. 1, the method for manufacturing the isolation structure of the first embodiment includes the steps of:
step S11: and shielding the first region of the substrate by using a third photoresist mask to form a second well region of the second doping type in the second region of the substrate. As shown in fig. 2A, a second well region 120 of the second doping type is formed in the second region 102 of the substrate by using a third photoresist mask 330 to block the first region 101 of the substrate. Further, a first oxide layer is formed on the P-type substrate 100, for example, silicon dioxide is generated by a thermal oxidation method; and etching the first oxide layer by using a third photoresist mask 330, positioning the second well region 120 of the second doping type in the substrate 100, removing the photoresist, then performing high-energy N-type ion implantation, annealing, removing the first oxide layer to form the N-type second well region 120, and simultaneously forming a step difference on the removed part of the first oxide layer, so that the first oxide layer can be used for subsequent photoetching alignment and the conventional alignment photoetching step is omitted.
Step S12: an oxide layer is formed on the substrate and a nitride layer is formed on the oxide layer. As shown in fig. 2B, the third photoresist mask 330 is removed, and an oxide layer 201, such as a silicon dioxide layer, and a nitride layer 202, such as a silicon nitride layer, are sequentially deposited on the surface of the substrate 100.
Step S13: active regions are formed in the first and second regions of the substrate using a first photoresist mask. As shown in fig. 2C, the oxide layer 201 and the nitride layer 202 are etched using the first photoresist mask 310 to expose portions of the surfaces of the first region 101 and the second region 102 of the substrate 100 to form active regions. The active area after photoetching is used as a hard mask for forming a compensation area and an isolation structure in the following process.
Step S14: a second photoresist mask is used to shield a second region of the substrate to form a first well region of the first doping type in the first region of the substrate. As shown in fig. 2D, further, the first photoresist mask 310 is removed, and the second photoresist mask 320 is used to shield the second region 102 in the substrate 100 and further shield the second well region 120, and a high energy implantation is performed to form the first well region 110 of the first doping type in the first region 101 of the substrate 100, wherein the implantation energy of the dopant of the first doping type of the high energy implantation enables the dopant to penetrate the active region. In other embodiments, a process of multiple high energy implants may be employed to form the first well region 110.
Step S15: and forming a compensation region of the first doping type on at least part of the surface of the well region of the first doping type by adopting a second photoresist mask and adopting the active region as a hard mask. As shown in fig. 2E, further, on the basis of not removing the second photoresist mask 320, a compensation region of the first doping type is formed on at least a portion of the surface of the first well region 110 of the first doping type by using the active region as a hard mask, and then the second photoresist mask 320 is removed. The implantation energy of the dopant of the first doping type forming the compensation region is such that the dopant is not able to penetrate the active region.
Step S16: and forming an isolation structure extending downwards along the surface of the substrate between the first region and the second region by using the active region as a hard mask. As shown in fig. 2F, an isolation structure 200 is formed extending down the substrate surface between the first region and the second region with the active region as a hard mask. Further, a field oxide region 200 extending downward from the upper surface of the substrate 100 is formed between the first well region 110 and the second well region 120 by local Oxidation of Silicon (LOCOS) or Chemical Vapor Deposition (CVD) to achieve isolation between adjacent well regions. The compensation region is in contact with at least a portion of the field oxide region 200. In other embodiments, a trench is formed between adjacent well regions or adjacent doped regions to serve as an isolation structure to achieve isolation, wherein the depth of the trench is related to the depth of the adjacent well regions or doped regions, for example.
Step S17: and removing the active region. As shown in fig. 2G, the active region on the substrate 100 is removed by etching.
The first doping type is P type, and the second doping type is N type.
Fig. 3 is a flow chart showing a method for manufacturing an isolation structure according to a second embodiment of the present invention. Fig. 4A to 4G are schematic structural diagrams showing each specific step in the manufacturing process of the isolation structure of the second embodiment.
The first embodiment of the invention forms a second well region of a second doping type in a second region of a substrate and forms a step difference on the substrate at the same time, then forms active regions in a first region and a second region of the substrate, and uses a photoresist mask to shield the second region of the substrate to perform high-energy injection in the substrate of the first region to form a first well region of a first doping type, and then still uses the photoresist mask and uses the active regions as a hard mask to form a compensation region of the first doping type on at least part of the surface of the first well region, so that an isolation structure formed on the surface of the first well region and extending downwards is contacted with the compensation region, thereby avoiding the dilution of the doping of the well region of the first doping type caused by the formation of the isolation structure, and forming the compensation region on at least part of the surface of the first well region without affecting the performance of a semiconductor device without additional mask and photoetching steps, and enhancing the isolation effect of the isolation structure. In the embodiment, the second well region is formed before the active region is formed and a step difference is formed on the substrate at the same time, so that the second well region can be used for subsequent photoetching alignment, and the conventional alignment photoetching step is omitted.
The second embodiment of the present invention is different from the first embodiment in that the second well region is formed by high energy implantation after the active region is formed. The second embodiment can still enable the isolation structure formed on the surface of the first well region and extending downwards to be in contact with the compensation region on the basis of not using an additional mask and photoetching operation, so that the phenomenon that the doping of the first doping type well region is lightened due to the formation of the isolation structure is avoided, and the isolation effect of the isolation structure is enhanced on the basis of not influencing the performance of the semiconductor device.
As shown in fig. 3, the method for manufacturing the isolation structure of the second embodiment includes the steps of:
step S21: an oxide layer is formed on a substrate and a nitride layer is formed on the oxide layer. As shown in fig. 4A, an oxide layer 501, a nitride layer 502, and an oxide layer 501 are sequentially deposited on the surface of the substrate 400. Such as a silicon dioxide layer and the nitride layer 502 is a silicon nitride layer.
Step S22: active regions are formed in the first and second regions of the substrate using a first photoresist mask. As shown in fig. 4B, the oxide layer 501 and the nitride layer 502 are then patterned by using a first photoresist mask 610 to etch the oxide layer 501 and the nitride layer 502 in the first region 401 and the second region 402 of the substrate 400, so as to expose portions of the surfaces of the first region 401 and the second region 402 of the substrate 400 and form an active region. The active area after photoetching is used as a hard mask for forming a compensation area and an isolation structure in the following process.
Step S23: and shielding the first region of the substrate by using a third photoresist mask to form a second well region of the second doping type in the second region of the substrate. As shown in fig. 4C, the first photoresist mask 610 is removed, the first region 401 of the substrate is masked by the third photoresist mask 630, and the second well region 420 of the second doping type is formed in the second region 402 of the substrate. Further, a second oxide layer is formed on the P-type substrate 400, for example, silicon dioxide is generated by a thermal oxidation method; and etching the second oxide layer by using a third photoresist mask 630, positioning the position of the second well region 420 with the second doping type in the substrate 400, removing the photoresist, then performing high-energy N-type ion implantation, annealing, removing the second oxide layer to form the N-type second well region 420, and forming a step difference on the removed part of the second oxide layer, so that the second oxide layer can be used for subsequent photoetching alignment and the conventional alignment photoetching step is omitted. In other embodiments, a process of multiple high energy implants may be employed to form the second well region 420.
Step S24: a second photoresist mask is used to shield a second region of the substrate to form a first well region of the first doping type in the first region of the substrate. As shown in fig. 4D, further, the third photoresist mask 630 is removed, and the second photoresist mask 620 is used to shield the second region 402 in the substrate 400 and further shield the second well region 420, and a high energy implantation is performed to form the first well region 410 of the first doping type in the first region 401 of the substrate 400, wherein the implantation energy of the dopant of the first doping type of the high energy implantation enables the dopant to penetrate the active region. In other embodiments, a process of multiple high energy implants may be employed to form the first well region 410.
Step S25: and forming a compensation region of the first doping type on at least part of the surface of the well region of the first doping type by adopting a second photoresist mask and adopting the active region as a hard mask. Further, as shown in fig. 4E, on the basis of not removing the second photoresist mask 620, a compensation region of the first doping type is formed on at least a portion of the surface in the first well region 410 of the first doping type using the active region as a hard mask, and then the second photoresist mask 620 is removed. The implantation energy of the dopant of the first doping type forming the compensation region is such that the dopant is not able to penetrate the active region.
Step S26: and forming an isolation structure extending downwards along the surface of the substrate between the first region and the second region by using the active region as a hard mask. As shown in fig. 4F, an isolation structure 500 is formed extending down the substrate surface between the first region and the second region with the active region as a hard mask. Further, a field oxide region 500 extending downward from the upper surface of the substrate 400 is formed between the first well region 410 and the second well region 420 by local Oxidation of Silicon (LOCOS) or Chemical Vapor Deposition (CVD) to achieve isolation between adjacent well regions. The compensation region is in contact with at least a portion of the field oxide region 500.
In other embodiments, a trench is formed between two adjacent well regions or two adjacent doped regions or between adjacent well regions and doped regions as an isolation structure to achieve isolation, wherein the depth of the trench is related to the depth of the adjacent well regions or doped regions, for example.
Step S27: and removing the active region. As shown in fig. 4G, the active region on the substrate 400 is removed by etching.
The first doping type is P type, and the second doping type is N type.
The method for manufacturing the isolation structure can be used for forming the isolation structure in a semiconductor device such as CMOS, bi-CMOS, BCD and the like, wherein the isolation structure can be a field oxide region or a trench, and the purpose is to enhance the isolation effect between adjacent well regions, between adjacent doped regions and between the well regions and the doped regions which are adjacent to each other in the semiconductor device.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
In accordance with the embodiments of the present application, as set forth above, these embodiments are not intended to be exhaustive or to limit the disclosure to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and its practical application, to thereby enable others skilled in the art to best utilize the application and its various modifications as are suited to the particular use contemplated.
Claims (15)
1. An isolation structure manufacturing method, comprising:
forming an active region in a first region and a second region on a substrate using a first photoresist mask, the first region and the second region being adjacent to each other;
removing the first photoresist mask, shielding the second region of the substrate by using a second photoresist mask, firstly forming a first well region of a first doping type in the first region of the substrate, then forming a compensation region of the first doping type on part of the surface of the first well region of the first doping type by using the active region as a hard mask, and then removing the second photoresist mask;
using the active region as a hard mask, extending down along the substrate surface between the first region and the second region to form an isolation structure,
the compensation region is in contact with at least a portion of the isolation structure.
2. The method of claim 1, wherein the isolation structure is a field oxide region or a trench.
3. The method of manufacturing an isolation structure of claim 1, wherein an implantation energy of a dopant of the first doping type forming the first well region enables the dopant to penetrate the active region.
4. The manufacturing method according to claim 1, wherein the dopant of the first doping type forming the compensation region is a phosphorus fluoride ion, and an implantation energy of the dopant is such that the dopant cannot penetrate the active region.
5. The method for manufacturing the isolation structure of claim 1, wherein a plurality of high energy implants are used to form the first well region during the formation of the first well region.
6. The method of fabricating an isolation structure according to claim 1, further comprising:
before the step of forming the active region, a third photoresist mask is adopted to shield a first region of the substrate, a second well region of a second doping type is formed in a second region on the substrate, the first doping type is opposite to the second doping type, and the second well region and the first well region are adjacent to each other.
7. The method for manufacturing an isolation structure according to claim 6, wherein a step difference is formed on a surface of the substrate during the formation of the second well region.
8. The method of fabricating an isolation structure according to claim 1, further comprising:
and between the steps of forming the active region and forming the first well region, shielding a first region of the substrate by using a third photoresist mask, and forming a second well region of a second doping type in a second region on the substrate, wherein the first doping type is opposite to the second doping type, and the second well region and the first well region are adjacent to each other.
9. The method for manufacturing the isolation structure of claim 8, wherein a high energy implantation process is used to form the second well region during the formation of the second well region.
10. The method of fabricating an isolation structure according to claim 1, further comprising:
after the step of forming the isolation structure, removing the active region.
11. The isolation structure manufacturing method of claim 1, wherein the step of forming the active region comprises:
forming an oxide layer on the substrate;
forming a nitride layer on the oxide layer; and
and adopting a first photoresist mask for shielding, and etching the nitride layer and the oxide layer to expose partial surfaces of the first area and the second area of the substrate.
12. The method for manufacturing an isolation structure according to claim 11, wherein the oxide layer is a silicon dioxide layer, and the nitride layer is a silicon nitride layer.
13. The method of manufacturing an isolation structure of claim 1, wherein the first doping type is P-type.
14. The method of claim 1, wherein the isolation structure is formed in a semiconductor device for isolating two adjacent well regions or two adjacent doped regions or adjacent well and doped regions.
15. The isolation structure fabrication method of claim 14, wherein the semiconductor device includes, but is not limited to: BCD devices, bi-CMOS devices, CMOS devices.
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| US4409726A (en) * | 1982-04-08 | 1983-10-18 | Philip Shiota | Method of making well regions for CMOS devices |
| US5132241A (en) * | 1991-04-15 | 1992-07-21 | Industrial Technology Research Institute | Method of manufacturing minimum counterdoping in twin well process |
| DE19527146A1 (en) * | 1995-07-25 | 1997-01-30 | Siemens Ag | Method for producing a self-aligned contact and a doped region |
| CN104916575B (en) * | 2014-03-11 | 2018-03-16 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacture method of semiconductor devices |
| CN105762103B (en) * | 2016-03-08 | 2018-11-16 | 上海华虹宏力半导体制造有限公司 | Semiconductor structure and forming method thereof |
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