CN112505467A

CN112505467A - Testing device and testing method for chip electromagnetic interference test

Info

Publication number: CN112505467A
Application number: CN202110122430.0A
Authority: CN
Inventors: 田露; 乔彦彬; 李纪平; 张婧晶; 宋蕾; 原义栋; 张海峰
Original assignee: State Grid Information and Telecommunication Co Ltd; Beijing Smartchip Microelectronics Technology Co Ltd
Current assignee: State Grid Information and Telecommunication Co Ltd; Beijing Smartchip Microelectronics Technology Co Ltd
Priority date: 2021-01-29
Filing date: 2021-01-29
Publication date: 2021-03-16

Abstract

The invention relates to the technical field of electromagnetic interference tests, and provides a test device and a test method for chip electromagnetic interference tests. The test device includes: the device comprises a test main board, a signal generator, a coupling network probe and a test sub-board for placing a chip; the test daughter board comprises a lead-out circuit correspondingly connected with a plurality of pins of the chip; the coupling network probe is connected with the lead-out circuit and the signal generator and is used for transmitting the electromagnetic interference signal generated by the signal generator to the lead-out circuit so as to lead the electromagnetic interference signal into the chip through the lead-out circuit; the test mainboard is connected with the test daughter board and used for acquiring signal data generated by the chip under the interference of the electromagnetic interference signals. According to the invention, the electromagnetic interference signal is directly introduced into the integrated circuit chip to accurately evaluate the anti-electromagnetic interference capability of each pin of the chip, so that a reference is provided for improving the internal circuit design of the chip, and the anti-electromagnetic interference capability of the chip is improved.

Description

Testing device and testing method for chip electromagnetic interference test

Technical Field

The invention relates to the technical field of electromagnetic interference testing, in particular to a testing device for chip electromagnetic interference testing and a chip electromagnetic interference testing method.

Background

At present, electromagnetic interference tests for electronic products are all at a device level, and the electromagnetic interference resistance of the whole device or system is evaluated by testing the whole machine, for example, an Electrical Fast Transient (EFT) test is performed on the electronic device.

With the development of integrated circuits, the structures of devices related to the fields of intelligent manufacturing, artificial intelligence, power industry, rail transit and the like are more and more complex, and the devices tend to be multifunctional and miniaturized. These devices contain a large number of basic elements by which various functions are implemented. As a typical basic element, an integrated circuit chip (IC) has higher and smaller integration, and the electromagnetic interference environment of the semiconductor devices in the chip is also worse and worse. However, the electromagnetic interference test based on the device level cannot evaluate the electromagnetic interference resistance of various chips as basic elements of the device. Therefore, in order to improve the anti-electromagnetic interference capability of the whole device or system, the anti-electromagnetic interference capability of the basic elements (i.e. chips) constituting the device needs to be improved. Therefore, an electromagnetic interference test needs to be performed on the chip to accurately evaluate the anti-electromagnetic interference capability of the chip.

However, at present, there is no apparatus or platform for performing electromagnetic interference test on a chip, and particularly, there is no EFT testing apparatus suitable for chip level.

Disclosure of Invention

The invention aims to provide a testing device for testing electromagnetic interference of a chip so as to accurately evaluate the anti-electromagnetic interference capability of the chip.

In order to achieve the above object, an embodiment of the present invention provides a testing apparatus for testing electromagnetic interference of a chip, the testing apparatus including: the device comprises a test main board, a signal generator, a coupling network probe and a test sub-board for placing a chip; the test daughter board comprises a lead-out circuit correspondingly connected with a plurality of pins of the chip; the coupling network probe is connected with the lead-out circuit and the signal generator and is used for transmitting the electromagnetic interference signal generated by the signal generator to the lead-out circuit so as to lead the electromagnetic interference signal into the chip through the lead-out circuit;

the test mainboard is connected with the test daughter board and used for acquiring signal data generated by the chip under the interference of the electromagnetic interference signals.

Further, the test daughter board further comprises an adapter module and a pin unit; the adapter module is butted with a plurality of pins of the chip; the input end of the pin unit is in butt joint with the probe of the coupling network probe, and the output end of the pin unit is connected with the adaptation module through the lead-out circuit.

Furthermore, the test daughter board further comprises a first connection module, the test main board is provided with a second connection module matched with the first connection module, and the test daughter board is detachably connected with the second connection module of the test main board through the first connection module so as to transmit the signal data fed back by the chip.

Furthermore, the test device also comprises a test control system and a power supply controller, and the test control system and the power supply controller are connected with the test mainboard.

Furthermore, the test mainboard comprises a communication interface module, a data storage module and a power interface module; the communication interface module is connected with the test control system and used for sending signal data generated by the chip to the test control system and receiving a test instruction sent by the test control system; the data storage module is used for storing signal data generated by the chip in a test process; the power interface module is connected with the power controller and used for inputting voltage.

Furthermore, the test mainboard further comprises a data output module; the data output module is connected with the data storage module and used for outputting the signal data stored in the data storage module.

Further, the power interface module includes a voltage stabilizing unit, and the voltage stabilizing unit is used for keeping the input voltage stable.

Furthermore, the pin unit comprises a plurality of pin interfaces, and the number of the pin interfaces of the pin unit is the same as that of the pins of the chip and corresponds to that of the pins of the chip one by one.

Furthermore, the test daughter board further comprises a signal adjusting unit, and the signal adjusting unit is used for adjusting signal data transmitted between the chip and the test motherboard.

Furthermore, the test daughter board further comprises a shielding layer, and the shielding layer is used for shielding interference of interference signals except the electromagnetic interference signals generated by the signal generator to the chip.

Further, the signal generator is an electric fast transient pulse group signal generator, a radio frequency signal generator or an electrostatic discharge device.

The embodiment of the invention also provides a chip electromagnetic interference test method, based on the test device for chip electromagnetic interference test, the method comprises the following steps:

selecting a matched test daughter board according to the number of pins of the chip to be tested;

mounting the selected test daughter board on the test main board;

connecting a test mainboard with a test control system and a power supply controller, connecting a control end of a signal generator with the test control system, and connecting a signal output end of the signal generator with a coupling network probe;

and placing the chip to be tested into an adapter module of the test daughter board, starting a signal generator after the chip is determined to enter a normal working state, contacting a probe of a coupling network probe with a pin interface of a pin unit of the test daughter board, and injecting an electromagnetic interference signal into each pin of the chip.

According to the testing device for testing the electromagnetic interference of the chip, provided by the embodiment of the invention, the electromagnetic interference signals are directly introduced into each pin of the integrated circuit chip, so that the anti-electromagnetic interference capability of each pin of the chip is accurately evaluated; through the evaluation result of each pin in the chip, reference is provided for improving the design of the internal circuit of the chip, so that the anti-electromagnetic interference capability of the chip is improved, and the anti-interference capability of the whole equipment or system is improved.

In addition, the test mainboard is detachably connected with the test daughter board, the test mainboard is mainly used for supplying power voltage and transmitting communication signals, the test mainboard can be matched with different test daughter boards for use, and the anti-interference test on chips of different models or sizes can be realized only by replacing the test daughter board matched with the chip to be tested.

Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention without limiting the embodiments of the invention. In the drawings:

FIG. 1 is a schematic structural diagram of a testing apparatus for testing electromagnetic interference of a chip according to an embodiment of the present invention;

FIG. 2 is a schematic structural diagram (cross-sectional view) of a test daughter board of a test apparatus for testing electromagnetic interference of a chip according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a planar structure of a test daughter board according to one embodiment of the present invention;

FIG. 4 is a schematic diagram of a plan view of a test daughter board according to another embodiment of the present invention;

fig. 5 is a block diagram of a test motherboard of a test apparatus for testing electromagnetic interference of a chip according to an embodiment of the present invention.

Description of the reference numerals

10-test daughter board, 11-adapter module, 12-pin unit, 13-first connection module,

14-leading out circuit, 15-signal regulating unit, 16-shielding layer, 17-coupling network probe,

20-test mainboard, 21-second connecting module, 22-communication interface module,

23-power interface module, 30-signal generator, 40-test control system,

50-power controller, 60-chip.

Detailed Description

The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation.

The terms "first" and "second" herein are used merely to distinguish one description from another, and are not to be construed as indicating or implying relative importance. "connected" as used herein is intended to mean an electrical power connection or a signal connection between two components; "coupled" may be a direct connection between two elements, an indirect connection between two elements through an intermediary (e.g., a wire), or an indirect connection between three elements.

fig. 2 is a schematic structural diagram (cross-sectional view) of a test daughter board of a test apparatus for testing electromagnetic interference of a chip according to an embodiment of the present invention.

As shown in fig. 1 and fig. 2, the testing apparatus for testing electromagnetic interference of a chip according to the present embodiment includes: the test daughter board 10, the test motherboard 20, the signal generator 30, the test control system 40, and the power controller 50 and the coupling network probe 17. The test daughter board 10 is used to place a chip 60 to be tested. The test daughter board 10 includes a lead-out circuit 14 connected to a plurality of pins of the chip 60. The coupling network probe 17 is connected with the lead-out circuit 14 and the signal generator 30, and is used for transmitting the electromagnetic interference signal generated by the signal generator 30 to the lead-out circuit 14 so as to lead the electromagnetic interference signal into the chip 60 through the lead-out circuit 14; the test motherboard 20 is connected to the test daughter board 10, and is configured to obtain signal data generated by the chip 60 under the interference of the electromagnetic interference signal. The power controller 50 is connected to the test motherboard 20, and is configured to provide a voltage for the test motherboard 20, and provide a voltage for normal operation of the chip 60 placed on the test daughter board 10 through the test motherboard 20. The test control system 40 is connected to the test motherboard 20, and is configured to control the entire test process and analyze signal data generated in the test process.

The testing device for the chip electromagnetic interference test can be used for various conduction type electromagnetic compatibility tests. For example, the signal generator 30 adopts an Electrical Fast Transient (EFT) signal generator, and the test apparatus can implement EFT test at a chip level; the signal generator 30 adopts a radio frequency signal generator, and can realize direct radio frequency Power Injection (DPI) test of a chip by combining the test device with the oscillograph to monitor the waveforms and Power of reflected and incident radio frequency signals; the signal generator 30 adopts an electrostatic discharge device, and the test device can realize the charged electrostatic discharge immunity (called power-ESD for short) test of the chip.

According to the testing device for testing the electromagnetic interference of the chip, provided by the embodiment of the invention, the electromagnetic interference signal is introduced into the integrated circuit chip so as to accurately evaluate the anti-electromagnetic interference capability of the chip, and reference is provided for improving the internal circuit design of the chip so as to improve the anti-electromagnetic interference capability of the chip.

fig. 4 is a schematic plan view of a test daughter board according to another embodiment of the present invention.

As shown in fig. 2 to 4, the test daughter board 10 provided in this embodiment further includes an adapter module 11, a pin unit 12, and a first connection module 13. The adapter module 11 is butted with a plurality of pins of the chip 60; the input end of the pin unit 12 is in butt joint with the probe of the coupling network probe 17, and the output end of the pin unit 12 is connected with the adaptation module 11 through the lead-out circuit 14. The adapting module 11 is a planar pad structure, and the tested chip 60 is directly connected with the test daughter board 10 in a patch welding mode, so that the interference possibly introduced by a complicated connection mode or an overlong connection distance is reduced. The lead-out circuit 14 is disposed inside the test daughter board 10 (for example, in the form of PCB wiring), and the pin unit 12 is connected to the adapter module 11 through the lead-out circuit 14, so as to lead the electromagnetic interference signal generated by the signal generator 30 into the chip 60. The pin unit 12 includes a plurality of pin interfaces, and the number of the pin interfaces of the pin unit 12 is the same as that of the pins of the chip 60 and corresponds to the pins of the chip 60 one by one, so as to introduce the electromagnetic interference signals to the corresponding pins of the chip 60.

As shown in fig. 1, the test main board 20 provided in this embodiment is provided with a second connection module 21 matching with the first connection module 13 of the test sub board 10, and the test sub board 10 is detachably connected to the second connection module 21 of the test main board 20 through the first connection module 13 to transmit signal data fed back by the chip 60 and provide the chip 60 with a voltage required for normal operation. The first connection module 13 and the second connection module 21 constitute a transmission loop of power voltage and signal data between the test daughter board 10 and the test motherboard 20. As shown in fig. 2, the test daughter board 10 provided in this embodiment further includes a signal conditioning unit 15 and a shield layer 16. The signal conditioning unit 15 is used for conditioning signal data transmitted between the chip 60 and the test motherboard 20, for example, buffering a voltage signal therebetween. The shielding layer 16 is used for shielding interference of interference signals other than the electromagnetic interference signals generated by the signal generator to the chip 60, so as to ensure the accuracy of the test data.

Fig. 5 is a block diagram of a test motherboard of a test apparatus for testing electromagnetic interference of a chip according to an embodiment of the present invention. As shown in fig. 5, the test motherboard 20 provided in this embodiment includes a second connection module 21, a communication interface module 22, a data storage module, a power interface module 23, and a data output module. The second connection module 21 is connected to the communication interface module 22 and the data storage module, and is used for transmitting the signal data generated by the chip 60 during the test process to the communication interface module 22 or the data storage module. The data storage module is used for storing signal data generated by the chip in the test process. The data output module is connected with the data storage module and used for outputting the signal data stored in the data storage module. Such as a USB interface module. As shown in fig. 1, the communication interface module 22 is connected to the test control system 40, and is configured to send signal data generated by the chip 60 to the test control system 40 and receive a test instruction sent by the test control system 40. The communication interface module 22 includes, for example, an RS232 communication interface, an SPI communication interface, an Asynchronous Receiver/Transmitter (UART), an I2C interface, a GPIO interface, a USB interface, and an EMAC interface. The power interface module 23 is connected to the power controller 50 for inputting voltage. The power interface module 23 includes a voltage regulation unit for maintaining the stability of the input voltage.

The embodiment of the invention also provides a chip electromagnetic interference test method, based on the test device for chip electromagnetic interference test, which comprises the following steps (taking EFT test as an example): before testing, a matched test sub-board 10 is selected according to the pin number of the chip 60 to be tested (the pin interface number of the pin unit 12 of the test sub-board 10 is consistent with the pin number of the chip 60), and the selected test sub-board 10 is installed on the test main board 20. The test motherboard 20 is connected to the test control system 40 and the power controller 50, the control terminal of the EFT signal generator 30 is connected to the test control system 40, and the signal output terminal of the EFT signal generator 30 is connected to the coupling network probe 17. During testing, the chip 60 to be tested is placed in the adapter module 11 of the test daughter board 10, the power controller 50 inputs voltage, and after determining that the chip 60 enters a normal working state, the EFT signal generator 30 is turned on, the probe of the coupling network probe 17 is contacted with the pin interface of the pin unit 12 of the test daughter board 10, and an EFT interference signal is injected to each pin of the chip 60 through the pin unit 12. The EFT interference signal meets the requirements of a test standard GB/T17626.4-2008 'electromagnetic compatibility test and measurement technology electric fast transient pulse group immunity test', the frequency is 100kHz, the time length of a single pulse group is 0.75ms, the pulse group period is 300ms, the amplitude initial value is 200V, the step length is 200V, and the maximum value is 2000V. In the testing process, the test control system 40 communicates with the chip 60, monitors the running state and the communication state of the chip 60 in real time through a serial port communication debugging program, and analyzes signal data of each pin of the chip 60, thereby accurately evaluating the EFT anti-interference performance of the chip 60.

The following lists a test example to perform an EFT test on an MCU master control chip of a certain model. The MCU main control chip is provided with various serial ports (UART, I2C, SPI, GPIO, USB and EMAC) and 144 pins (namely pins). During testing, the serial port is debugged through the test software of the test control system, test signals are sent to the chip, and feedback signals are monitored so as to judge whether the running state of the chip is normal or not. After the serial port is debugged, the chip is kept in a normal working state, the EFT signal generator is started, the coupling network probe is connected with the test pin unit, EFT interference signals are introduced into each pin of the chip, and the signal state of each pin is monitored in real time. The test results of various pins obtained by the EFT test of the MCU main control chip are as follows:

power supply pin:

pin type	Pin name	±200	±1200	±2000
					PWR	1-VDDIO	PASS	PASS	PASS
PWR	16-VDDIO	PASS	PASS	PASS
					PWR	27-VDD12	FAIL
PWR	30-VDD33	PASS	PASS	FAIL
					PWR	31-VDD16	PASS	PASS	PASS
PWR	118-VDDIO	PASS	PASS	PASS
					PWR	132-VDDIO	PASS	PASS	PASS
PWR	2-GNDIOC	PASS	PASS	PASS
					PWR	15-GNDIO	PASS	PASS	PASS
PWR	42-GNDIOC	PASS	PASS	PASS
					PWR	57-GNDIOC	PASS	PASS	PASS
PWR	102-GNDIO	PASS	PASS	FAIL
					PWR	117-GNDIOC	PASS	PASS	PASS
PWR	131-GNDIO	PASS	PASS	PASS

The EFT anti-interference capability of each pin of the chip can be accurately detected through testing, and the sensitivity of different interface pins or communication protocols to EFT interference signals is obviously different. The reason of chip pin communication failure is analyzed according to the test result, and the EFT anti-jamming capability of each pin is improved by improving the circuit design, so that the EFT anti-jamming performance of the whole chip is improved.

The testing device provided by the embodiment of the invention can also be used for various conduction type electromagnetic interference (EMI) tests, such as: direct radio frequency power injection (DPI) test, charged-ESD immunity (Powered-ESD) test.

In another example, a DPI test, a Power-ESD test, and an EFT test are performed on a security chip of a certain type, and the test results are shown in the following table.

DPI (limit of 30dBm) test results:

pin number	Pin name	30dBm
			1	GND	PASS
2	RST	/
			3	SPI_MISO	FAIL
4	SPI_SSN	FAIL
			5	SPI_CLK	FAIL
6	GPIO	/
			7	SPI_MOSI	PASS
8	VCC	FAIL

Power-ESD (Limit of + -2000V) test results:

pin number

1

3

4

5

7

8

Pin name

GND

SPI_MISO

SPI_SSN

SPI_CLK

SPI_MOSI

VCC

+200V

PASS

-200V

PASS

FAIL

+600V

PASS

-600V

PASS

FAIL

+1000V

PASS

-1000V

PASS

+1400V

PASS

-1400V

PASS

+1800V

PASS

-1800V

PASS

+2000V

PASS

-2000V

PASS

EFT (Limit. + -. 2000V) test results:

pin number	1	7	8
				Pin name	GND	SPI_MOSI	VCC
-200V	PASS	FAIL	PASS
				+200V	PASS	FAIL	PASS
-1000V	FAIL	FAIL	FAIL
				+1000V	PASS	PASS	PASS
-2000V	/	PASS	/
				+2000V	/	PASS	/

According to the testing device for testing the chip electromagnetic interference, provided by the embodiment of the invention, the electromagnetic interference signals are directly introduced into each pin (namely the pin) of the integrated circuit chip, so that the anti-electromagnetic interference capability (such as the failure voltage value and the failure time of each type of pin) of each pin of the chip is accurately evaluated; through the evaluation result of each pin in the chip, reference is provided for improving the design of the internal circuit of the chip, and the anti-electromagnetic interference capability of the chip is improved, so that the anti-interference capability of the whole equipment or system is improved.

While the embodiments of the present invention have been described in detail with reference to the accompanying drawings, the embodiments of the present invention are not limited to the details of the above embodiments, and various simple modifications can be made to the technical solution of the embodiments of the present invention within the technical idea of the embodiments of the present invention, and the simple modifications are within the scope of the embodiments of the present invention.

Claims

1. A test apparatus for electromagnetic interference testing of a chip, the test apparatus comprising: the device comprises a test main board, a signal generator, a coupling network probe and a test sub-board for placing a chip;

the test daughter board comprises a lead-out circuit correspondingly connected with a plurality of pins of the chip;

the coupling network probe is connected with the lead-out circuit and the signal generator and is used for transmitting the electromagnetic interference signal generated by the signal generator to the lead-out circuit so as to lead the electromagnetic interference signal into the chip through the lead-out circuit;

2. The test device for testing the electromagnetic interference of the chip according to claim 1, wherein the test daughter board further comprises an adapter module and a pin unit;

the adapter module is butted with a plurality of pins of the chip;

the input end of the pin unit is in butt joint with the probe of the coupling network probe, and the output end of the pin unit is connected with the adaptation module through the lead-out circuit.

3. The testing device for the electromagnetic interference test of the chip as claimed in claim 2, wherein the testing daughter board further comprises a first connection module, the testing motherboard is provided with a second connection module matching with the first connection module, and the testing daughter board is detachably connected with the second connection module of the testing motherboard through the first connection module to transmit the signal data fed back by the chip.

4. The testing device for the electromagnetic interference test of the chip as recited in claim 2, further comprising a testing control system and a power controller, wherein the testing control system and the power controller are connected with the testing motherboard.

5. The testing device for the chip electromagnetic interference test according to claim 4, wherein the testing motherboard comprises a communication interface module, a data storage module and a power interface module;

the communication interface module is connected with the test control system and used for sending signal data generated by the chip to the test control system and receiving a test instruction sent by the test control system;

the data storage module is used for storing signal data generated by the chip in a test process;

the power interface module is connected with the power controller and used for inputting voltage.

6. The testing device for the chip electromagnetic interference test according to claim 5, wherein the testing motherboard further comprises a data output module;

the data output module is connected with the data storage module and used for outputting the signal data stored in the data storage module.

7. The device according to claim 5, wherein the power interface module comprises a voltage regulator unit for keeping the input voltage stable.

8. The apparatus of claim 2, wherein the pin unit comprises a plurality of pin interfaces, and the number of the pin interfaces of the pin unit is the same as the number of the pins of the chip and corresponds to one of the pin interfaces of the chip.

9. The testing device for the chip electromagnetic interference test according to claim 3, wherein the test daughter board further comprises a signal conditioning unit, and the signal conditioning unit is used for conditioning signal data transmitted between the chip and the test motherboard.

10. The testing device for testing the electromagnetic interference of the chip as claimed in claim 2, wherein the testing daughter board further comprises a shielding layer for shielding the chip from interference signals other than the electromagnetic interference signals generated by the signal generator.

11. The testing device for testing the electromagnetic interference of the chip as claimed in claim 1, wherein the signal generator is an electric fast transient pulse group signal generator, a radio frequency signal generator or a static electricity discharge device.

12. A chip electromagnetic interference test method based on the test device for chip electromagnetic interference test of any one of claims 1-11, wherein the method comprises;

mounting the selected test daughter board on the test main board;