CN112491678A - Digital level transmission circuit and method - Google Patents

Digital level transmission circuit and method Download PDF

Info

Publication number
CN112491678A
CN112491678A CN202011280188.1A CN202011280188A CN112491678A CN 112491678 A CN112491678 A CN 112491678A CN 202011280188 A CN202011280188 A CN 202011280188A CN 112491678 A CN112491678 A CN 112491678A
Authority
CN
China
Prior art keywords
control module
slave control
fault
signal
slave
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202011280188.1A
Other languages
Chinese (zh)
Inventor
刘超
卢昆忠
胡慧璇
李辉
姜伟
闫大鹏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuxi Ruike Fiber Laser Technology Co ltd
Original Assignee
Wuxi Ruike Fiber Laser Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuxi Ruike Fiber Laser Technology Co ltd filed Critical Wuxi Ruike Fiber Laser Technology Co ltd
Priority to CN202011280188.1A priority Critical patent/CN112491678A/en
Publication of CN112491678A publication Critical patent/CN112491678A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/28Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40Bus networks
    • H04L12/40006Architecture of a communication node
    • H04L12/40013Details regarding a bus controller
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S3/00Lasers, i.e. devices using stimulated emission of electromagnetic radiation in the infrared, visible or ultraviolet wave range
    • H01S3/09Processes or apparatus for excitation, e.g. pumping
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/28Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40Bus networks
    • H04L12/40169Flexible bus arrangements
    • H04L12/40176Flexible bus arrangements involving redundancy
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/28Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40Bus networks
    • H04L2012/40208Bus networks characterized by the use of a particular bus standard
    • H04L2012/40215Controller Area Network CAN

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Plasma & Fusion (AREA)
  • Optics & Photonics (AREA)
  • Optical Communication System (AREA)

Abstract

The embodiment of the invention provides a digital level transmission circuit and a method thereof, wherein the circuit comprises a master control module and at least one slave control module; the master control module comprises a Controller Area Network (CAN) chip and a peripheral circuit, and the slave control module comprises a CAN chip and a peripheral circuit; the master control module is used for sending a signal to be transmitted to the slave control module in a digital level mode; the CAN chip is used for controlling digital level transmission; the master control module and the slave control module are connected through a bus. The main control module and the slave control module are connected through a bus, and the CAN chips in the main control module and the slave control module are used for achieving transmission of key digital levels, so that the anti-interference capability and the transmission rate of digital signals in the transmission process are improved.

Description

Digital level transmission circuit and method
Technical Field
The invention relates to the technical field of digital electronics, in particular to a digital level transmission circuit and a digital level transmission method.
Background
In the present master-slave system laser, in order to control the light emission of the laser, a master control module generally sends a digital enable signal and a modulation signal to a plurality of slave control modules to achieve the purpose of controlling the light emission.
At present, the main control module mainly controls each laser directly by a wire transmission level mode.
However, due to the existence of various noises, the existing technical solutions have the problem that two digital signals, namely, the light-emitting enable signal and the modulation signal, are easily interfered by the noises inside and outside the cabinet when being transmitted, and cause the defect that the laser is easily operated incorrectly.
Disclosure of Invention
The embodiment of the invention provides a digital level transmission circuit and a digital level transmission method, which are used for solving the problems that in the prior art, a digital signal is easily interfered by noise inside and outside a cabinet when being transmitted and the defect that a laser is easily operated by mistake is caused, and realizing the improvement of the anti-interference capability and the transmission rate of the digital signal in the transmission process.
An embodiment of the present invention provides a digital level transmission circuit, including:
a master control module and at least one slave control module; the master control module comprises a Controller Area Network (CAN) chip and a peripheral circuit, and the slave control module comprises a CAN chip and a peripheral circuit; the master control module is used for sending a signal to be transmitted to the slave control module in a digital level mode;
the master control module and the slave control module are connected through a bus.
The digital level transmission circuit according to an embodiment of the present invention further includes:
and the signal generating equipment is used for sending the signal to be transmitted to the main control module.
The embodiment of the present invention further provides a digital level transmission method applied to the digital level transmission circuit, including:
the master control module judges whether the slave control module has a fault;
and if the slave control modules do not have faults, the master control module sends the signals to be transmitted to each slave control module.
According to the digital level transmission method of an embodiment of the present invention, the determining whether the slave control module fails specifically includes:
if a fault feedback signal sent by the slave control module is received, determining that the slave control module has a fault;
if the fault feedback signal is not received, determining that the slave control module has no fault;
the fault feedback signal is a dominant level signal used for representing the fault of the slave control module.
According to the digital level transmission method of an embodiment of the present invention, before determining whether the slave control module fails, the method further includes:
and the main control module receives or generates the signal to be transmitted.
According to the digital level transmission method of an embodiment of the present invention, after the master control module determines whether the slave control module has a fault, the method further includes:
if the slave control module fails, the failed slave control module sends a dominant level signal to the normal slave control module and the master control module.
The embodiment of the present invention further provides a digital level transmission method applied to the digital level transmission circuit, including:
each slave control module judges whether the slave control module has a fault or not;
and if the slave control modules do not have faults, receiving a signal to be transmitted sent by the master control module.
According to the digital level transmission method of an embodiment of the present invention, after each slave control module determines whether itself has a fault, the method further includes:
if at least one slave control module in the slave control modules has faults, the slave control module with the faults sends fault feedback signals to the master control module and the normal slave control module;
the fault feedback signal is a dominant level signal used for representing the fault of the slave control module.
According to the digital level transmission circuit and the digital level transmission method, the master control module and the slave control module are connected through the bus, and the transmission of the key digital level is achieved through the CAN chips in the master control module and the slave control module, so that the anti-interference capacity and the transmission rate of digital signals in the transmission process are improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a digital level transmission circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a main control module in a digital level transmission circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a slave control module in a digital level transmission circuit according to an embodiment of the present invention;
fig. 4 is a schematic flowchart of a digital level transmission method applied to the digital level transmission circuit according to an embodiment of the present invention;
fig. 5 is a flowchart of another digital level transmission method applied to the digital level transmission circuit according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a schematic structural diagram of a digital level transmission circuit according to an embodiment of the present invention, as shown in fig. 1, including:
a master control module and at least one slave control module; the master control module comprises a Controller Area Network (CAN) chip and a peripheral circuit, and the slave control module comprises a CAN chip and a peripheral circuit; the master control module is used for sending a signal to be transmitted to the slave control module in a digital level mode;
specifically, the digital level transmission circuit in the application comprises a master control module and at least one slave control module; the master control module consists of a Controller Area Network (CAN) chip and a peripheral circuit thereof, and the slave control module consists of a CAN chip and a peripheral circuit thereof. Peripheral circuits of the master control module and the slave control module may be modified as needed, and are not particularly limited herein.
For example, fig. 2 is a schematic structural diagram of a main control module in a digital level transmission circuit according to an embodiment of the present invention, and as shown in fig. 2, an MOD signal in the diagram is an outgoing light modulation signal of a laser, which controls an outgoing light frequency of the laser. MOD is an outgoing light modulation signal pin; RE _ MOD is a modulation signal feedback pin on the bus; r159 and R162 are matched resistances; d19 shows the state of the MOD signal; c119 is power supply filtering; r164 pulling RS of U32 to ground places U32 in slope control mode, reducing electromagnetic interference generated by fast rise time and resulting harmonics; the VREF is not influenced by suspension due to the grounding of the C120; r156 is CAN bus terminal resistance; r152 and R161 are matching resistors; l9 is filtering. U32 is CAN transceiver chip.
Fig. 3 is a schematic structural diagram of a slave control module in a digital level transmission circuit according to an embodiment of the present invention, and as shown in fig. 3, R131 and R137 are matching resistors; r140 pulls RS of U32 to ground placing U32 in a slope control mode, reducing electromagnetic interference generated by fast rise times and harmonics generated thereby; c170 is power filtering; the VREF is not influenced by suspension by grounding through the C111; u34 is ESD resistant; l22 is bus filtering; r122 and R143 are matched resistances.
The main control module and the slave control module are connected through a bus, and the CAN chips in the main control module and the slave control module are used for achieving transmission of key digital levels, so that the anti-interference capability and the transmission rate of digital signals in the transmission process are improved.
The master control module and the slave control module are connected through a bus.
Specifically, the master control module and the slave control module are connected through a bus, and the master control module receives a feedback signal sent by the slave control module through the bus and performs digital level transmission to the slave control module through the bus.
The main control module and the slave control module are connected through a bus, and the CAN chips in the main control module and the slave control module are used for achieving transmission of key digital levels, so that the anti-interference capability and the transmission rate of digital signals in the transmission process are improved.
Optionally, on the basis of the foregoing embodiments, the digital level transmission circuit further includes:
and the signal generating equipment is used for sending the signal to be transmitted to the main control module. The signal generating device may be an external signal generating device.
Specifically, the signal to be transmitted may be generated by the main control module itself, or may be generated by the received signal generating device. The type of signal to be transmitted may be a modulation signal, a light-out enable signal, and other digital signals capable of controlling the light source.
The main control module and the slave control module are connected through a bus, and the CAN chips in the main control module and the slave control module are used for achieving transmission of key digital levels, so that the anti-interference capability and the transmission rate of digital signals in the transmission process are improved.
Fig. 4 is a schematic flowchart of a digital level transmission method applied to the digital level transmission circuit according to an embodiment of the present invention, as shown in fig. 4, specifically including:
step 401, the master control module judges whether the slave control module has a fault;
specifically, the master control module is to send a signal to be transmitted to the slave control module, and first, whether the slave control module fails is determined.
Step 402, if no slave control module has a fault, the master control module sends a signal to be transmitted to each slave control module.
Specifically, if none of the slave control modules fails, the master control module sends a signal to be transmitted to each of the slave control modules. The type of signal to be transmitted may be a modulation signal, a light-out enable signal, and other digital signals capable of controlling the light source.
The main control module and the slave control module are connected through a bus, and the CAN chips in the main control module and the slave control module are used for achieving transmission of key digital levels, so that the anti-interference capability and the transmission rate of digital signals in the transmission process are improved.
Optionally, on the basis of the foregoing embodiments, the determining whether the slave control module fails specifically includes:
if a fault feedback signal sent by the slave control module is received, determining that the slave control module has a fault;
if the fault feedback signal is not received, determining that the slave control module has no fault;
the fault feedback signal is a dominant level signal used for representing the fault of the slave control module.
Specifically, when the master control module receives a fault feedback signal sent by the slave control module, it is determined that a fault occurs in the slave control module.
In the embodiment of the present application, the specific model of the CAN chip is not limited, and CAN chips of various models of various manufacturers are applicable, for example, SN65HVD230, SN65HVD231, and the like.
The following describes the flow of the above digital level transmission method by taking a CAN chip with model number SN65HVD230D as an example:
the function table of the transmitting end (DRIVER) is shown in table 1.
TABLE 1 sender (DRIVER) function Table
Figure BDA0002780529460000071
Where H is high, L is low, X is irrelevant, and Z is high impedance.
The function table of the receiving end (RECEIVER) is shown in table 2.
TABLE 2 RECEIVER function TABLE
Figure BDA0002780529460000072
Where H is high, L is low, and X is irrelevant? Is uncertain.
When the D input of the pin 1 of the chip is L/low level, the CAN bus is dominant, and when the input is H/high level, the CAN bus is recessive.
The first condition is as follows: when the MOD on the master control module is high and one or more of the slave control modules fails, i.e. the ERR is low, the following reactions occur: the CAN chip on the main control module is in a receiving state; and the CAN chip on the slave control module with the fault sends a dominant level, the CAN chip on the slave control module without the fault is in a receiving state, and the received MOD is a low level. The CAN chip on the main control module receives the dominant level, VID is more than or equal to 0.9V, R is the low level, namely RE _ MOD is the low level, and the abnormality of the slave control module is fed back. And other slave control modules receive the dominant level on the bus, receive the low level at the MOD and stop emitting light, so that the laser is protected from being damaged.
And when the master control module does not receive the fault feedback signal sent by the slave control module, judging that the slave control module has a fault.
Case two: when MOD on the master is low, the following responses will occur: and the CAN chip on the main control module outputs dominant level. And receiving the dominant level from the CAN chip on the control module, wherein VID is more than or equal to 0.9V, and R is the low level, namely MOD on the control module is the low level (achieving digital signal transmission).
Case three: when the MOD on the master control module is high and all slave control modules are not faulty, i.e. ERR is high, the following reactions occur: the CAN chip on the main control module is in a receiving state. And receiving a recessive level by a CAN chip on the slave control module, wherein VID is less than or equal to 0.5V, and R is a high level, namely MOD on the slave control is a high level (achieving digital signal transmission).
The main control module and the slave control module are connected through a bus, and the CAN chips in the main control module and the slave control module are used for achieving transmission of key digital levels, so that the anti-interference capability and the transmission rate of digital signals in the transmission process are improved.
Optionally, on the basis of the foregoing embodiments, before determining whether the slave control module fails, the method further includes:
and the main control module receives the signal to be transmitted.
Specifically, the signal to be transmitted may be generated by the main control module itself, or may be generated by the received signal generating device. If the signal to be transmitted is generated by the received signal generating device, the master control module needs to receive the signal to be transmitted generated by the signal generating device before judging whether the slave control module has a fault. The type of signal to be transmitted may be a modulation signal, a light-out enable signal, and other digital signals capable of controlling the light source.
Optionally, on the basis of the foregoing embodiments, after the master control module determines whether the slave control module fails, the method further includes:
if the slave control module fails, the failed slave control module sends a dominant level signal to the normal slave control module and the master control module.
Specifically, when one or more slave controllers have a fault, the slave control module with the fault sends a dominant level signal to the normal slave control module and the master control module, so that other slave control modules can skip the master control module, respond quickly and shut off the light output controlled by the slave control module.
The main control module and the slave control module are connected through a bus, and the CAN chips in the main control module and the slave control module are used for achieving transmission of key digital levels, so that the anti-interference capability and the transmission rate of digital signals in the transmission process are improved.
Fig. 5 is a schematic flow chart of another digital level transmission method applied to the digital level transmission circuit according to an embodiment of the present invention, as shown in fig. 5, specifically including:
step 501, judging whether each slave control module has a fault or not;
specifically, each slave control module judges whether the slave control module has a fault, and determines to send a fault feedback signal to the master control module according to whether the slave control module has the fault.
Step 502, if no fault occurs in each slave control module, receiving a signal to be transmitted sent by the master control module.
Specifically, if each slave control module fails, the master control module sends a signal to be transmitted to each slave control module; the type of signal to be transmitted may be a modulation signal, a light-out enable signal, and other digital signals capable of controlling the light source.
The main control module and the slave control module are connected through a bus, and the CAN chips in the main control module and the slave control module are used for achieving transmission of key digital levels, so that the anti-interference capability and the transmission rate of digital signals in the transmission process are improved.
Optionally, on the basis of the foregoing embodiments, after each slave control module determines whether it has a fault, the method further includes:
if at least one slave control module in the slave control modules has faults, the slave control module with the faults sends fault feedback signals to the master control module and the normal slave control module;
the fault feedback signal is a dominant level signal used for representing the fault of the slave control module.
Specifically, when one or more of the slave control modules fails, the master control module can quickly receive a failure feedback signal and operate the laser to take corresponding measures. Other normal slave control modules can skip the master control module, respond quickly and shut off the light output controlled by the slave control module.
The main control module and the slave control module are connected through a bus, and the CAN chips in the main control module and the slave control module are used for achieving transmission of key digital levels, so that the anti-interference capability and the transmission rate of digital signals in the transmission process are improved.
In the embodiment of the invention, the CAN chip has high speed, the highest transmission speed CAN reach 1Mbps, and the requirements of (modulation signal) MOD and (light-emitting enabling signal) LASER _ EN signals of a LASER CAN be met. The CAN transmission has the function of resisting interference because of the cross signal. When one or more slave control modules are in fault, the master control module can quickly receive a fault signal and operate the laser to take corresponding measures. The method is suitable for a master-slave mode, when one or more slave control modules are in fault, other slave control modules can skip master control and respond quickly to shut off light emitted from the slave control modules.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims (8)

1. A digital level transfer circuit, comprising:
a master control module and at least one slave control module; the master control module comprises a Controller Area Network (CAN) chip and a peripheral circuit, and the slave control module comprises a CAN chip and a peripheral circuit; the master control module is used for sending a signal to be transmitted to the slave control module in a digital level mode; the CAN chip is used for controlling digital level transmission;
the master control module and the slave control module are connected through a bus.
2. The digital level transfer circuit of claim 1, further comprising:
and the signal generating equipment is used for sending the signal to be transmitted to the main control module.
3. A digital level transmission method applied to the digital level transmission circuit of claim 1 or 2, comprising:
the master control module judges whether the slave control module has a fault;
and if the slave control modules do not have faults, the master control module sends the signals to be transmitted to each slave control module.
4. The method according to claim 3, wherein the determining whether the slave control module has a fault includes:
if a fault feedback signal sent by the slave control module is received, determining that the slave control module has a fault;
if the fault feedback signal is not received, determining that the slave control module has no fault;
the fault feedback signal is a dominant level signal used for representing the fault of the slave control module.
5. The method of claim 3, wherein before determining whether the slave control module is faulty, the method further comprises:
and the main control module receives or generates the signal to be transmitted.
6. The method of claim 3, wherein the step of the master control module determining whether the slave control module has failed further comprises:
if the slave control module fails, the failed slave control module sends a dominant level signal to the normal slave control module and the master control module.
7. A digital level transmission method applied to the digital level transmission circuit of claim 1 or 2, comprising:
each slave control module judges whether the slave control module has a fault or not;
and if the slave control modules do not have faults, receiving a signal to be transmitted sent by the master control module.
8. The method of claim 7, wherein after each slave control module determines whether it has a fault, the method further comprises:
if at least one slave control module in the slave control modules has faults, the slave control module with the faults sends fault feedback signals to the master control module and the normal slave control module;
the fault feedback signal is a dominant level signal used for representing the fault of the slave control module.
CN202011280188.1A 2020-11-16 2020-11-16 Digital level transmission circuit and method Pending CN112491678A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011280188.1A CN112491678A (en) 2020-11-16 2020-11-16 Digital level transmission circuit and method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011280188.1A CN112491678A (en) 2020-11-16 2020-11-16 Digital level transmission circuit and method

Publications (1)

Publication Number Publication Date
CN112491678A true CN112491678A (en) 2021-03-12

Family

ID=74930949

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011280188.1A Pending CN112491678A (en) 2020-11-16 2020-11-16 Digital level transmission circuit and method

Country Status (1)

Country Link
CN (1) CN112491678A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114978798A (en) * 2022-05-23 2022-08-30 重庆奥普泰通信技术有限公司 Serial communication method, device and board card

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140023365A1 (en) * 2012-07-17 2014-01-23 Teledyne Instruments, Inc. Systems and methods for subsea optical can buses
US20190036732A1 (en) * 2017-07-27 2019-01-31 X Development Llc Asymmetric CAN-based Communication for Aerial Vehicles
CN110718847A (en) * 2019-10-15 2020-01-21 武汉锐科光纤激光技术股份有限公司 Multi-module optical fiber laser with function of monitoring abnormity of optical module in real time

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140023365A1 (en) * 2012-07-17 2014-01-23 Teledyne Instruments, Inc. Systems and methods for subsea optical can buses
US20190036732A1 (en) * 2017-07-27 2019-01-31 X Development Llc Asymmetric CAN-based Communication for Aerial Vehicles
CN110718847A (en) * 2019-10-15 2020-01-21 武汉锐科光纤激光技术股份有限公司 Multi-module optical fiber laser with function of monitoring abnormity of optical module in real time

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
牛跃听: "《工程师经验手记 CAN总线嵌入式开发 从入门到实战 第2版》", 30 April 2016 *
黄智伟: "《全国大学生电子设计竞赛 常用电路模块制作 第2版》", 30 September 2016 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114978798A (en) * 2022-05-23 2022-08-30 重庆奥普泰通信技术有限公司 Serial communication method, device and board card
CN114978798B (en) * 2022-05-23 2024-02-27 重庆奥普泰通信技术有限公司 Serial communication method, device and board card

Similar Documents

Publication Publication Date Title
US9568534B2 (en) Battery electronics system
US7346785B2 (en) Structure cabling system
US6473608B1 (en) Structure cabling system
US10572428B2 (en) Bus system
US10901041B2 (en) Semiconductor device, battery monitoring system and semiconductor device activation method
EP1688811A2 (en) Networks for process control
CN112491678A (en) Digital level transmission circuit and method
US6992599B2 (en) Terminal adapter for connecting a terminal to a computer local area network capable of identifying any of several terminal types
EP4207691A1 (en) Controller area network termination scheme
CN113079071B (en) Method for detecting digital signals in real time through unidirectional wiring
EP3930265A1 (en) Can transceiver
CN111555946B (en) Subscriber station for a bus system and method for data transmission in a bus system
US12021346B2 (en) Multi-module fiber laser capable of monitoring abnormalities of optical modules in real time
JP3816366B2 (en) Data transmission device control method, data transmission device control unit, and data transmission device
JP2000324153A (en) Converter for lan
CN115766388A (en) CAN communication circuit, control method thereof and vehicle
CN114020679A (en) I2C bus control circuit and circuit system for ship
CN116032338A (en) Mining RS485 signal repeater
JPH11167401A (en) Distributed control system
CN116683412A (en) Ethernet interface circuit and network interface
JP2021044759A (en) Deterioration detection device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20210312

RJ01 Rejection of invention patent application after publication