CN112485516A - Electric energy meter and non-intrusive load identification chip architecture - Google Patents
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Abstract
The application discloses chip architecture of non-intervention load identification includes: the analog-to-digital conversion unit is used for performing analog-to-digital conversion on the sampled current and voltage; the metering unit is used for carrying out electric energy analysis according to the output data of the analog-to-digital conversion unit to obtain an electric energy analysis result; the AI accelerator is used for carrying out reasoning operation on the electric energy analysis result based on a preset AI reasoning algorithm to obtain an electric energy load identification result; the storage unit is used for storing a parameter model of an AI inference algorithm, process data generated by inference operation and an electric energy load identification result; the processor is used for configuring the AI accelerator and the metering unit; the analog-to-digital conversion unit, the metering unit, the AI accelerator, the storage unit and the processor are all integrated in a single SOC chip. By applying the scheme, the speed and the precision of load identification can be improved, the burden of data network transmission and a data center is reduced, the calculation efficiency is high, and the size and the power consumption are low.
Description
Technical Field
The invention relates to the technical field of power analysis, in particular to an electric energy meter and a chip architecture for non-intrusive load identification.
Background
With the rapid development of national economy, the demand of society on electric energy is increasing day by day, and the requirement on electric energy quality is also higher and higher. The improvement of the power quality has important significance for safe operation of a power grid and electrical equipment, guarantee of the product quality and improvement of the living standard of people. The decomposition and classification identification of the electric energy load are beneficial to knowing the load composition of the electric power system, so that the change rule and the development trend of the electric energy load can be mastered, and the scientific management of the electric energy load can be facilitated.
At present, when the electric energy load is identified, a general traditional identification mode is mainly adopted, the identification rate is difficult to improve, in addition, a metering chip of an electric energy meter is utilized to obtain metering data, and the metering data is sent to a remote data center for further analysis, so that although the identification rate can be improved, the burden of the data center is increased, and particularly, the data center needs more and more data to be processed along with the more and more complex power grid system. In addition, such an approach also increases the burden of network transmission.
In summary, how to improve the accuracy of load identification and reduce the burden of data network transmission and data center is a technical problem that needs to be solved urgently by those skilled in the art.
Disclosure of Invention
The invention aims to provide an electric energy meter and a chip architecture without intervention of load identification, so as to improve the accuracy of load identification and reduce the burden of data network transmission and a data center.
In order to solve the technical problems, the invention provides the following technical scheme:
a chip architecture for non-intrusive load recognition, comprising:
the analog-to-digital conversion unit is used for performing analog-to-digital conversion on the sampled current and voltage;
the metering unit is connected with the analog-to-digital conversion unit and used for carrying out electric energy analysis according to the output data of the analog-to-digital conversion unit to obtain an electric energy analysis result;
the AI accelerator is connected with the metering unit and used for carrying out reasoning operation on the electric energy analysis result based on a preset AI reasoning algorithm to obtain an electric energy load identification result;
the storage unit is connected with the AI accelerator through a communication bus and is used for storing a parameter model of an AI inference algorithm, process data generated by inference operation and the electric energy load identification result;
a processor connected to the AI accelerator and the metering unit via a communication bus for configuring the AI accelerator and the metering unit;
wherein the analog-to-digital conversion unit, the metering unit, the AI accelerator, the storage unit, and the processor are all integrated in a single SOC chip.
Preferably, the analog-to-digital conversion unit is based on a high-precision architecture.
Preferably, the metering unit is specifically configured to:
performing electric energy analysis according to the output data of the analog-to-digital conversion unit to obtain an electric energy analysis result, wherein the electric energy analysis result comprises: fundamental instantaneous active power, fundamental instantaneous reactive power, full-wave instantaneous active power, full-wave instantaneous reactive power, fundamental average active power, fundamental average reactive power, full-wave average active power, full-wave average reactive power, fundamental instantaneous voltage effective value, fundamental instantaneous current effective value, full-wave instantaneous voltage effective value, full-wave instantaneous current effective value, fundamental average voltage effective value, fundamental average current effective value, full-wave average voltage effective value, full-wave average current effective value, voltage direct component, current direct component, power waveform data.
Preferably, the metering unit is further configured to:
and analyzing electric energy according to the output data of the analog-to-digital conversion unit to obtain a dynamic power difference value, a dynamic voltage difference value and a dynamic current difference value.
Preferably, the method further comprises the following steps:
and the coprocessor is connected with the AI accelerator through a communication bus and is used for executing the logic operation of the set items in the AI inference algorithm.
Preferably, the method further comprises the following steps:
one or more embedded Flash units arranged in the SOC chip;
and the SOC chip also comprises one or more storage interfaces for connecting external Flash.
Preferably, the SOC chip further includes a high-speed peripheral interface and a low-speed peripheral interface.
Preferably, the method further comprises the following steps:
and the DMA unit is used for realizing data transmission.
Preferably, the processor is further configured to:
and transmitting the electric energy load identification result through wireless communication or power carrier communication.
An electric energy meter comprising the chip architecture for non-intrusive load identification of any one of the above.
In the scheme of this application, the precision that utilizes artificial intelligence algorithm can improve power load discernment is considered, therefore, this application utilizes the metering unit to obtain the electric energy analysis result after, through the AI accelerator, based on preset AI inference algorithm, carry out inference operation to the electric energy analysis result to can obtain the very high electric energy load of precision and distinguish the result, and AI inference algorithm can improve inference operation at the terminal side execution efficiency. In addition, the electric energy analysis result obtained by the metering unit does not need to be sent to a remote data center to realize the identification of the power load, so that the scheme of the application can reduce the burden of data network transmission and the data center. In addition, the scheme of the application is not a double-core architecture but a single-core architecture, namely, the application does not arrange a metering chip and an AI accelerating chip for carrying out AI operation, but integrates an analog-to-digital conversion unit, a metering unit, an AI accelerator, a storage unit and a processor into a single SOC chip. In addition, the AI accelerator and the metering unit are configured by the processor, frequent intervention operation of the processor is reduced in the operation process after configuration is finished, the identification result of the power load can be obtained based on the metering unit and the AI accelerator, and the efficiency is improved. In summary, the scheme of the application can effectively improve the speed and the precision of load identification under the conditions of reducing the dominant frequency and reducing the power consumption, and the AI inference algorithm can improve the execution efficiency of the inference operation at the end side, and in addition, the data network transmission and the burden of a data center are reduced, the calculation efficiency is high, and the volume and the power consumption of the scheme are also lower.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a chip architecture for non-intrusive load identification in the present invention;
FIG. 2 is a schematic structural diagram of an AI accelerator according to an embodiment of the invention;
fig. 3 is a schematic structural diagram of a chip architecture for non-intrusive load identification according to an embodiment of the present invention.
Detailed Description
The core of the invention is to provide a chip architecture for non-intrusive load identification, which can effectively improve the speed and the precision of load identification under the conditions of reducing dominant frequency and reducing power consumption, and an AI inference algorithm can improve the execution efficiency of inference operation at the end side, and in addition, the invention also reduces the burden of data network transmission and a data center, and has high calculation efficiency and lower volume and power consumption of the scheme.
In order that those skilled in the art will better understand the disclosure, the invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a chip architecture for non-intrusive load recognition in the present invention, where the chip architecture for non-intrusive load recognition may include:
an analog-to-digital conversion unit 10, configured to perform analog-to-digital conversion on the sampled current and voltage;
the metering unit 20 is connected with the analog-to-digital conversion unit 10 and used for performing electric energy analysis according to the output data of the analog-to-digital conversion unit 10 to obtain an electric energy analysis result;
the AI accelerator 30 is connected with the metering unit 20 and used for performing reasoning operation on the electric energy analysis result based on a preset AI reasoning algorithm to obtain an electric energy load identification result;
a storage unit 40 connected to the AI accelerator 30 through a communication bus, for storing a parameter model of an AI inference algorithm, process data generated by inference operation, and an electric energy load identification result;
a processor 50 connected to the AI accelerator 30 and the metering unit 20 through a communication bus, for configuring the AI accelerator 30 and the metering unit 20;
among them, the analog-to-digital conversion unit 10, the metering unit 20, the AI accelerator 30, the storage unit 40, and the processor 50 are all integrated in a single SOC chip.
Specifically, the non-intrusive load identification chip architecture of the present application may be generally disposed in an electric energy meter, the analog-to-digital conversion unit 10 may perform analog-to-digital conversion on sampled current and voltage, the specific type of the analog-to-digital conversion unit 10 may be set and selected according to actual needs, and a specific circuit structure for sampling current and voltage may also be set and adjusted according to actual needs. In an embodiment of the present invention, the analog-to-digital conversion unit 10 may be selected as the analog-to-digital conversion unit 10 based on the high-precision Σ/Δ architecture, considering that the precision of the analog-to-digital conversion unit 10 may affect the precision of the power load identification according to the present invention.
The metering unit 20 is connected to the analog-to-digital conversion unit 10, and can perform power analysis according to the output data of the analog-to-digital conversion unit 10 to obtain a power analysis result. Generally, the metering unit 20 may obtain a corresponding waveform according to the output data of the analog-to-digital conversion unit 10, and then perform power analysis. Furthermore, the metering unit 20 supports the buffering of waveforms, and in addition, part of the AI inference algorithm needs to use the electric energy waveform data obtained by the AD sampling, so that the electric energy analysis result obtained by the metering unit 20 also supports the inclusion of the electric energy waveform data, so as to be sent to the AI accelerator 30 and other devices, that is, the electric energy analysis result obtained by the metering unit 20 may also include the electric energy waveform data.
When the metering unit 20 performs the electric energy analysis to obtain the electric energy analysis result, the item content specifically included in the electric energy analysis result may be set and adjusted according to actual needs, for example, the calculation of active/reactive power, the calculation of effective value and average value of voltage/current, and the like may be included.
In one embodiment of the present invention, the metering unit 20 may be specifically configured to:
performing power analysis according to the output data of the analog-to-digital conversion unit 10 to obtain a power analysis result, where the power analysis result includes: fundamental instantaneous active power, fundamental instantaneous reactive power, full-wave instantaneous active power, full-wave instantaneous reactive power, fundamental average active power, fundamental average reactive power, full-wave average active power, full-wave average reactive power, fundamental instantaneous voltage effective value, fundamental instantaneous current effective value, full-wave instantaneous voltage effective value, full-wave instantaneous current effective value, fundamental average voltage effective value, fundamental average current effective value, full-wave average voltage effective value, full-wave average current effective value, voltage direct component, current direct component, power waveform data.
In this embodiment, the metering unit 20 is utilized to perform comprehensive electric energy analysis, so as to obtain a comprehensive electric energy analysis result, and meanwhile, the AD sampled electric energy waveform data is cached, thereby being beneficial to obtaining a more accurate electric energy load identification result in the follow-up process.
Further, in an embodiment of the present invention, the metering unit 20 may further be configured to:
and analyzing the electric energy according to the output data of the analog-to-digital conversion unit 10 to obtain a dynamic power difference value, a dynamic voltage difference value and a dynamic current difference value.
In this embodiment, considering that the scheme of the present application can perform the identification of the electric load based on the AI accelerator 30, it can be understood that, the more the content of the electric energy analysis result for identifying the electric load is, the more complicated the identification of the electric load is, since the dimensionality of the independent variables is increased, the AI inference algorithm can support this multi-dimensional variable scenario well, and therefore, this embodiment takes into account that the solution of the present application is based on the recognition of the electrical load by the AI accelerator 30, after the electric energy analysis is performed according to the output data of the analog-to-digital conversion unit 10, the obtained electric energy analysis result further includes a dynamic power difference value, a dynamic voltage difference value and a dynamic current difference value, the parameters more conveniently realize the reasoning operation of the electric energy load identification, thereby being beneficial to the scheme of the application to obtain the electric energy load identification result with higher precision more quickly and conveniently.
The AI accelerator 30 may perform inference operation on the electric energy analysis result based on a preset AI inference algorithm to obtain an electric energy load identification result.
The specific form of the preset AI inference algorithm can be set and adjusted according to actual needs, as long as the electric energy load identification result meeting the precision requirement can be obtained. It can be understood that, after the AI inference algorithm is set, it needs to be trained by using a training sample, and the AI inference algorithm can be applied after the training is completed.
The specific configuration of the AI accelerator 30 may also be set and adjusted according to actual conditions, and generally, the selection of the AI accelerator 30 may be performed according to an specifically selected AI inference algorithm in actual applications. For example, fig. 2 is a schematic structural diagram of a general AI accelerator 30 in a specific embodiment, and a double-buffer mechanism, that is, a buffer a and a buffer B, are set in a data buffer in the AI accelerator 30 in fig. 2, and are respectively used for storing input data and parameter data, so as to prepare for source data and operator data of convolution operation, that is, facilitate convolution operation. Data in the data buffer part can enter the operation part through the control part, and specifically, operations such as vector comparison, vector addition, dot multiplication, activation and the like can be executed. The operation result of the operation component can return to the data cache or the operation component according to the control requirement of the flow of the AI inference algorithm, namely, the operation component can also be provided with the operation cache.
The AI accelerator 30 supports convolution vector multiplication, and may support structures such as 3 × 3, 5 × 5, and 7 × 7, and may support multiplier structures such as 1 × 3, 1 × 5, and 1 × 7, and multiplication such as 8 bits and 16 bits. The activation function may support sigmod, tanh, Relu, etc. activation functions. The AI accelerator 30 also supports basic operations such as vector maximum, minimum, average, etc.
In an embodiment of the present invention, referring to fig. 3, the method may further include:
the coprocessor 60 connected to the AI accelerator 30 through a communication bus is configured to perform logical operations of setting items in the AI inference algorithm.
Specifically, the coprocessor 60 may be used to assist the AI accelerator 30, and in some cases, when the processor 50 supports DSP operations, the processor 50 may also be used to assist the AI accelerator 30 without additionally providing the coprocessor 60. That is, the processor 50 may be used to configure the AI accelerator 30 and the metering unit 20, and the processor 50 may also support performing data movement and data operation, so as to assist the operation of the AI inference algorithm.
The coprocessor 60 may be configured to perform a logical operation on setting items in the AI inference algorithm, where the setting items may be generally embodied as items with large operation amounts, such as sin, cos, tan, and an open root.
The processor 50 of the present application may configure the AI accelerator 30 and the metering unit 20 through a communication bus, and it can be understood that, in the operation process, the intervention of the processor 50 is reduced by the scheme of the present application, and the AI accelerator 30 and the metering unit 20 can work, so as to improve the efficiency of the AI inference algorithm, and also facilitate reducing energy consumption and balancing power consumption and area of a chip. The processor 50 may be an ARM-M family core or a lightweight core such as a RISC-V core.
The storage unit 40 may store a parameter model of the AI inference algorithm, process data generated by the inference operation, and an electric energy load identification result. The storage unit 40 may be used as a program space or a data space. In general, the storage unit 40 may include 1 or more roms, and may include 1 or more rams. For example, in the embodiment of fig. 3, 1 rom and n rams are provided. In addition, when the internal ram resources are not enough, the scheme of the application can also support the externally-extended PSRAM.
In an embodiment of the present invention, the method may further include:
one or more embedded Flash units arranged in the SOC chip. For example, in the embodiment of fig. 3, an embedded Flash unit 70 is disposed in the SOC chip, and the embedded Flash unit 70 may be selected according to actual needs to store data.
Furthermore, the SOC chip may further include one or more storage interfaces for connecting to external Flash. When the internal Flash storage resources are not enough, the external Flash can be used for realizing the expansion of the storage resources.
Flash can store data such as a program and a network parameter model of an AI inference algorithm. For example, in the embodiment of fig. 3, an external storage interface 1 is provided for connecting an external Flash, and an external storage interface 2 is provided for connecting an external ram memory.
In a specific embodiment of the present invention, the SOC chip may further include a high-speed peripheral interface and a low-speed peripheral interface, so as to meet a requirement of a common peripheral connection. For example, in the embodiment of fig. 3, a high-speed peripheral interface is provided, and a plurality of low-speed peripheral interfaces, which may be specifically low-speed peripheral interfaces such as UART, SPI, I2C, are provided through the secondary bus matrix, for connecting various low-speed peripherals.
In an embodiment of the present invention, the method may further include:
a DMA unit 80 for implementing data transfer. The DMA (Direct Memory Access) unit 80 can allow data interaction between hardware devices of different speeds without relying on a CPU. The DMA unit 80 may support memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral data transfers.
In one embodiment of the present invention, the processor 50 is further configured to: and transmitting the electric energy load identification result through wireless communication or power carrier communication. The electric energy load identification result is sent through wireless communication or power carrier communication, so that the receiving end can conveniently and timely obtain the electric energy load identification result.
In the scheme of the application, the accuracy of power load identification can be improved by using an artificial intelligence algorithm, so that after the electric energy analysis result is obtained by using the metering unit 20, the electric energy analysis result is subjected to reasoning operation based on a preset AI reasoning algorithm through the AI accelerator 30, so that the electric energy load identification result with high accuracy can be obtained, and the AI reasoning algorithm can improve the execution efficiency of the reasoning operation at the end side. In addition, according to the present invention, it is not necessary to transmit the electric energy analysis result obtained by the metering unit 20 to a remote data center to identify the electric power load, and therefore, the data network transmission and the load of the data center can be reduced. In addition, the scheme of the present application is not a two-core architecture, but a single-core architecture, that is, the present application does not provide a metering chip and an AI acceleration chip for performing AI operations, but integrates the analog-to-digital conversion unit 10, the metering unit 20, the AI accelerator 30, the storage unit 40, and the processor 50 into a single SOC chip, which is a single-core architecture, so that the chip size and power consumption are reduced, and the identification result of the power load can be obtained more quickly. In addition, in the present application, the AI accelerator 30 and the metering unit 20 are configured by the processor 50, and in the operation process after the configuration is completed, frequent intervention operations of the processor 50 are reduced, so that the identification result of the power load can be obtained based on the metering unit 20 and the AI accelerator 30, which is beneficial to improving the efficiency. In summary, the scheme of the application can effectively improve the speed and the precision of load identification under the conditions of reducing the dominant frequency and reducing the power consumption, and the AI inference algorithm can improve the execution efficiency of the inference operation at the end side, and in addition, the data network transmission and the burden of a data center are reduced, the calculation efficiency is high, and the volume and the power consumption of the scheme are also lower.
Corresponding to the chip architecture for non-intrusive load identification, the application also provides an electric energy meter, and the electric energy meter may include the chip architecture for non-intrusive load identification in any embodiment, and a description thereof is not repeated here.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The principle and the implementation of the present invention are explained in the present application by using specific examples, and the above description of the embodiments is only used to help understanding the technical solution and the core idea of the present invention. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.
Claims (10)
1. A chip architecture for non-intrusive load recognition, comprising:
the analog-to-digital conversion unit is used for performing analog-to-digital conversion on the sampled current and voltage;
the metering unit is connected with the analog-to-digital conversion unit and used for carrying out electric energy analysis according to the output data of the analog-to-digital conversion unit to obtain an electric energy analysis result;
the AI accelerator is connected with the metering unit and used for carrying out reasoning operation on the electric energy analysis result based on a preset AI reasoning algorithm to obtain an electric energy load identification result;
the storage unit is connected with the AI accelerator through a communication bus and is used for storing a parameter model of an AI inference algorithm, process data generated by inference operation and the electric energy load identification result;
a processor connected to the AI accelerator and the metering unit via a communication bus for configuring the AI accelerator and the metering unit;
wherein the analog-to-digital conversion unit, the metering unit, the AI accelerator, the storage unit, and the processor are all integrated in a single SOC chip.
2. The chip architecture for non-intrusive load identification as recited in claim 1, wherein the analog-to-digital conversion unit is a high-precision sigma/delta architecture based analog-to-digital conversion unit.
3. The chip architecture for non-intrusive load recognition as recited in claim 1, wherein the metering unit is specifically configured to:
performing electric energy analysis according to the output data of the analog-to-digital conversion unit to obtain an electric energy analysis result, wherein the electric energy analysis result comprises: fundamental instantaneous active power, fundamental instantaneous reactive power, full-wave instantaneous active power, full-wave instantaneous reactive power, fundamental average active power, fundamental average reactive power, full-wave average active power, full-wave average reactive power, fundamental instantaneous voltage effective value, fundamental instantaneous current effective value, full-wave instantaneous voltage effective value, full-wave instantaneous current effective value, fundamental average voltage effective value, fundamental average current effective value, full-wave average voltage effective value, full-wave average current effective value, voltage direct component, current direct component, power waveform data.
4. The chip architecture of non-intrusive load recognition as defined in claim 3, wherein the metering unit is further configured to:
and analyzing electric energy according to the output data of the analog-to-digital conversion unit to obtain a dynamic power difference value, a dynamic voltage difference value and a dynamic current difference value.
5. The chip architecture for non-intrusive load recognition as recited in claim 1, further comprising:
and the coprocessor is connected with the AI accelerator through a communication bus and is used for executing the logic operation of the set items in the AI inference algorithm.
6. The chip architecture for non-intrusive load recognition as recited in claim 1, further comprising:
one or more embedded Flash units arranged in the SOC chip;
and the SOC chip also comprises one or more storage interfaces for connecting external Flash.
7. The chip architecture for non-intrusive load recognition of claim 1, wherein the SOC chip further comprises a high speed peripheral interface and a low speed peripheral interface.
8. The chip architecture for non-intrusive load recognition as recited in claim 1, further comprising:
and the DMA unit is used for realizing data transmission.
9. The chip architecture of non-intrusive load recognition as defined in claim 1, wherein the processor is further configured to:
and transmitting the electric energy load identification result through wireless communication or power carrier communication.
10. An electric energy meter, characterized in that it comprises a chip architecture for non-intrusive load identification as defined in any one of claims 1 to 9.
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| CN113220628A (en) * | 2021-04-29 | 2021-08-06 | 深圳供电局有限公司 | Processor and edge computing device for power grid anomaly detection |
| CN113899946A (en) * | 2021-09-02 | 2022-01-07 | 江苏智臻能源科技有限公司 | Power detection system and detection method for identification module |
| CN116821638A (en) * | 2023-08-31 | 2023-09-29 | 北京中电科卫星导航***有限公司 | Data analysis method and system for AI chip application optimization design |
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