CN112466885B - Three-dimensional memory and manufacturing method thereof - Google Patents
Three-dimensional memory and manufacturing method thereof Download PDFInfo
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- CN112466885B CN112466885B CN202011343824.0A CN202011343824A CN112466885B CN 112466885 B CN112466885 B CN 112466885B CN 202011343824 A CN202011343824 A CN 202011343824A CN 112466885 B CN112466885 B CN 112466885B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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Abstract
The invention relates to a three-dimensional memory and a manufacturing method thereof, wherein the three-dimensional memory comprises: a substrate; a stacked structure on a substrate; a plurality of dummy channel structures passing through the step structure of the stack structure; a plurality of contact plugs electrically connected to the gate layer at the step structures, respectively; the contact plugs are positioned between two adjacent rows of virtual channel structures, the maximum width of at least one of the contact plugs and the virtual channel structures along the first transverse direction is smaller than that along the second transverse direction, and the second transverse direction is parallel to the substrate and perpendicular to the first transverse direction, so that a process window in the first transverse direction when the virtual channel structures and the contact plugs are formed by etching can be enlarged, and the problem that the virtual channel structures and the contact plugs are fused in the etching process is avoided.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of memories, in particular to a three-dimensional memory and a manufacturing method thereof.
[ background of the invention ]
As technology evolves, the semiconductor industry is continually looking for new ways of production so that each memory die in a memory device has a greater number of memory cells. Among them, the 3D NAND (three-dimensional NAND) memory has become a leading-edge three-dimensional memory technology with great development potential due to its advantages of high storage density and low cost.
In the 3D NAND memory, the stacked 3D NAND memory is realized by vertically stacking a plurality of layers of data storage units. The stack structure in the 3D NAND memory generally includes a core array region and a step region in which a dummy channel structure and a contact plug are simultaneously distributed.
However, in the existing formation process of the 3D NAND memory, the dummy channel structure and the contact plug located in the step region (especially, the region with the lower step) may have shape distortion during etching, and there is a high risk of merging the dummy channel structure and the contact plug, which further causes gate leakage current, and affects the performance of the finally formed 3D NAND memory.
[ summary of the invention ]
The invention aims to provide a three-dimensional memory and a manufacturing method thereof, so as to avoid the problem of fusion of a virtual channel structure and a contact plug, and further improve the performance of the three-dimensional memory.
In order to solve the above problems, the present invention provides a three-dimensional memory including: a substrate; the stacked structure comprises a plurality of gate electrode layers and gate insulating layers which are stacked alternately, and the end parts of the gate electrode layers and the gate insulating layers form a step structure; a plurality of dummy channel structures passing through the step structure of the stack structure; a plurality of contact plugs electrically connected to the gate layer at the step structures, respectively; the contact plugs are positioned between two adjacent rows of the virtual channel structures, and the maximum width of at least one of the contact plugs and the virtual channel structures along the first transverse direction is smaller than that along the second transverse direction, and the second transverse direction is parallel to the substrate and perpendicular to the first transverse direction.
The cross section of at least one of the contact plugs and the dummy channel structures is in an elliptical shape with a long axis and a short axis, and the long axis direction of the elliptical shape is in a second transverse direction.
The contact plugs are arranged in rows and columns along a first transverse direction and a second transverse direction, and the cross sections of the contact plugs are oval.
The virtual channel structure combination comprises three virtual channel structures adjacent to the corresponding contact plugs, and the cross sections of the virtual channel structures in the virtual channel structure combination and the corresponding contact plugs in the same row in the first transverse direction are in an elliptical shape.
The projections of the three virtual channel structures in the virtual channel structure combination on the substrate enclose an isosceles triangle, and the projections of the corresponding contact plugs on the substrate are located at the center of the isosceles triangle.
And in every two adjacent rows of virtual channel structures, one row of virtual channel structures are linearly distributed in the second transverse direction, and the other row of virtual channel structures are distributed in a wavy line in the second transverse direction.
At least two rows of dummy channel structures are arranged between two rows of contact plugs adjacent to each other in the first transverse direction.
Wherein a cross-sectional shape of the plurality of contact plugs and/or the plurality of dummy channel structures includes a circle or a square.
Wherein, a plurality of gate electrode layers and gate insulating layers also form a core array structure connected with the step structure in a second transverse direction, and the three-dimensional memory further comprises: a plurality of channel structures passing through the core array structure of the stacked structure; and the common source structure is vertical to the substrate and penetrates through the core array structure in the second transverse direction.
In order to solve the above problems, the present invention further provides a method for manufacturing a three-dimensional memory, the method comprising: forming a stacked structure on the substrate, wherein the stacked structure comprises a plurality of gate electrode layers and gate insulating layers which are stacked alternately, and the end parts of the plurality of gate electrode layers and the gate insulating layers form a step structure; forming a plurality of dummy channel structures on the step structure of the stacked structure, the plurality of dummy channel structures passing through the step structure; forming a plurality of contact plugs, wherein the contact plugs are electrically connected with the grid layer at the positions of the step structures respectively; the contact plugs are positioned between two adjacent rows of the virtual channel structures, and the maximum width of at least one of the contact plugs and the virtual channel structures along the first transverse direction is smaller than that along the second transverse direction, and the second transverse direction is parallel to the substrate and perpendicular to the first transverse direction.
Wherein, form a plurality of virtual channel structures on the stair structure, specifically include: and etching to form a plurality of virtual channel structures on the step structure by using a first preset mask, wherein the first preset mask is provided with a plurality of first openings, and the maximum width of at least one of the plurality of first openings along the first transverse direction is smaller than the maximum width along the second transverse direction.
Wherein, form a plurality of contact plugs, specifically include: and etching to form a plurality of contact plugs on the step structure by using a second preset mask, wherein the second preset mask is provided with a plurality of second openings, and the maximum width of at least one of the second openings along the first transverse direction is smaller than the maximum width along the second transverse direction.
The invention has the beneficial effects that: different from the prior art, according to the three-dimensional memory and the manufacturing method thereof provided by the invention, the maximum width of at least one of the plurality of contact plugs and the plurality of dummy channel structures along the first transverse direction (for example, the vertical transverse direction) is smaller than the maximum width of the at least one of the plurality of contact plugs and the plurality of dummy channel structures along the second transverse direction (for example, the horizontal transverse direction), so that the process window in the first transverse direction during the etching process for forming the dummy channel structures and the contact plugs can be increased, the problem of fusion of the dummy channel structures and the contact plugs in the etching process is avoided, and the performance of the three-dimensional memory is improved.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a top view structure of a three-dimensional memory according to an embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view taken along line O-O' in FIG. 1;
FIG. 3 is a schematic cross-sectional view taken along line P-P' of FIG. 1;
FIG. 4 is a schematic diagram illustrating a partial top view of a contact plug and a dummy channel structure in a three-dimensional memory according to an embodiment of the present invention;
FIG. 5 is a schematic diagram illustrating another partial top view of a contact plug and a dummy channel structure in a three-dimensional memory according to an embodiment of the present invention;
FIG. 6 is a schematic diagram illustrating another partial top view structure of a contact plug and a dummy channel structure in a three-dimensional memory according to an embodiment of the present invention;
fig. 7 is a flowchart illustrating a method for manufacturing a three-dimensional memory according to an embodiment of the invention.
[ detailed description ] embodiments
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be noted that the following examples are only illustrative of the present invention, and do not limit the scope of the present invention. Likewise, the following examples are only some but not all examples of the present invention, and all other examples obtained by those skilled in the art without any inventive step are within the scope of the present invention.
In addition, directional terms mentioned in the present invention, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], and the like, refer to directions of the attached drawings only. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention. In the various figures, elements of similar structure are identified by the same reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Moreover, some well-known elements may not be shown in the figures.
Referring to fig. 1 to 3, fig. 1 is a schematic top view structure diagram of a three-dimensional memory according to an embodiment of the invention, fig. 2 is a schematic cross-sectional structure diagram taken along a line O-O 'in fig. 1, and fig. 3 is a schematic cross-sectional structure diagram taken along a line P-P' in fig. 1. The three-dimensional memory includes a substrate 11, a stack structure 12, a dielectric layer 13, a plurality of dummy channel structures 14, and a plurality of contact plugs 15. The stacked structure 12 is located on the substrate 11 and includes several gate layers 121 and gate insulating layers 122 alternately stacked in a longitudinal direction Z perpendicular to the substrate 11, and ends of the several gate layers 121 and the gate insulating layers 122 form a step structure 12A. The dielectric layer 13 covers the step structure 12A. The dummy channel structures 14 pass through the step structure 12A of the stack structure 12, and the contact plugs 15 are electrically connected to the gate layer 121 at the positions of the step structure 12A, respectively.
Specifically, the gate electrode layer 121 and the gate insulating layer 122 may extend in a second transverse direction X parallel to the substrate 11, and a step structure 12A may be formed at one end of the second transverse direction X, where the step structure 12A is stepped in the longitudinal direction Z. The plurality of dummy channel structures 14 and the plurality of contact plugs 15 may be perpendicular to the substrate 11 and formed in the dielectric layer 13 and the step structure 12A of the stack structure 12. The dummy channel structures 14 may be arranged in a plurality of rows in a first lateral direction Y parallel to the substrate 11 and perpendicular to the second lateral direction X. The contact plugs 15 respectively extend to the gate layers 121 along the longitudinal direction Z, and each contact plug 15 is located between two adjacent rows of dummy trench structures 14.
In the present embodiment, the maximum width of at least one of the plurality of contact plugs 15 and the plurality of dummy channel structures 14 in the first lateral direction Y is smaller than the maximum width in the second lateral direction X, so that when the distribution positions and the area ratios of the dummy channel structures 14 and the contact plugs 15 in the step structure 12A are fixed, by optimizing the cross-sectional shapes of part of the dummy channel structures 14 and the contact plugs 15, compared with the prior art, the process window in the first lateral direction Y when the dummy channel structures 14 and the contact plugs 15 are formed in at least part of the step structure 12A is increased, the effective area between adjacent dummy channel structures 14 and contact plugs 15 is ensured, and thus the problem of fusion caused by the length of the dummy channel structures 14 and the contact plugs 15 in the first lateral direction Y due to deformation during etching is avoided. Moreover, since the contact plug 15 is located between two adjacent rows of dummy channel structures 14, that is, both sides of the contact plug 15 on the second transverse direction X do not have the dummy channel structures 14, it can be considered that the process window of the contact plug 15 on the second transverse direction X is large enough, so that the dummy channel structure 14 and the contact plug 15 do not merge due to the length increase on the second transverse direction X in the etching process, and further, the problem of gate leakage current due to the electrical communication between the contact plug 15 and the dummy channel structure 14 caused by the merging of the contact plug 15 and the dummy channel structure 14 does not occur.
Specifically, in order to realize that the maximum width of the contact plug 15 and the dummy channel structure 14 in the first lateral direction Y is smaller than the maximum width in the second lateral direction X, the cross-sectional shapes of the contact plug 15 and the dummy channel structure 14 may be elliptical shapes having a major axis and a minor axis, and the major axis direction of the elliptical shapes is the second lateral direction X. Also, in some alternative embodiments, the oval shape may be replaced by other shapes (e.g., oblate, rectangular, diamond, etc.) obtained by compressing or stretching a centrosymmetric shape (e.g., a circle or square) in a certain direction and a certain ratio.
As shown in fig. 2, two adjacent gate electrode layers 121 may be electrically isolated from each other by a gate insulating layer 122, and the top and the bottom of the stacked structure 12 also include the gate insulating layer 122. The number of layers of the gate layer 121 in the stacked structure 12 may be determined according to the number of memory cells to be formed in the longitudinal direction Z. The number of steps of the step structure 12A may be equal to or less than the number of the gate layers 121, for example, as shown in fig. 2, each step may include 1 gate layer 121. Specifically, the above-described stepped structure 12A exposes the respective gate layers 121 so that the corresponding gate layers 121 are led out through the contact plugs 15 provided on the respective stepped mesas. The contact plugs 15 are used for connecting the corresponding gate electrode layer 121 and peripheral circuits, and extend in a vertical direction Z perpendicular to the stacked structure 12.
In this embodiment, the substrate 11 may be made of monocrystalline silicon, monocrystalline germanium, silicon-on-insulator (SOI), or the like. The gate layer 121 may be made of a conductive material such as tungsten. The gate insulating layer 122 may be made of any one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbonitride. The material of the dielectric layer 13 may be an insulating material such as silicon oxide. The gate electrode layer 121 and the gate insulating layer 122 may further form a core array structure 12B connected to the step structure 12A in the second transverse direction X, and the three-dimensional memory may further include a plurality of channel holes 16, a gate line slit 17, a common source structure (not shown) located in the gate line slit 17, and a channel structure (not shown) located in the channel holes 16.
The plurality of channel holes 16 and the gate line slits 17 are formed in the core array structure 12A and are perpendicular to the substrate 11, and accordingly, the channel structure passes through the core array structure 12A of the stacked structure 12, and the common source structure is perpendicular to the substrate 11 and passes through the core array structure 12A in the second transverse direction X. The contact plug 15 may be made of a conductive material such as tungsten. The common source structure may include a spacer layer on the sidewall surface of the gate line slit 17 and a common source on the spacer layer surface, wherein the spacer layer is an insulating layer, such as an oxide layer, the common source may be made of a conductive material (e.g., titanium or titanium nitride, polysilicon and/or tungsten), and the bottom of the common source is connected to the substrate 11 to provide a conductive channel for source connection. The channel structure may include a charge storage layer on a surface of a sidewall of the channel hole 16 and a channel layer on a surface of the charge storage layer, the charge storage layer may include a blocking oxide layer, a charge trapping layer on the blocking oxide layer, and a tunneling oxide layer on the charge trapping layer, wherein the charge trapping layer may be made of silicon nitride, and the channel layer may be made of polysilicon.
It is understood that, in the formation process of the three-dimensional memory, the dummy channel structure is not removed in the step of removing the gate sacrificial layer, and thus the dummy channel structure can support the step structure 12A, so that the step structure 12A is not easily collapsed. In specific implementation, the virtual channel structure and the channel structure may have the same structure, and thus, the details are not repeated herein.
Also, only one core array structure 12B and one step structure 12A are given as an example in the present embodiment, in other embodiments, the number of the step structures 12A may be two, the core array structure 12B is located between the two step structures a2, and the internal structure of one side of the three-dimensional memory in the second transverse direction X may refer to the internal structure of the other side. It is understood that the present embodiment specifically describes only the internal structure of the three-dimensional memory on one side in the second transverse direction X.
Specifically, as shown in fig. 4, the plurality of contact plugs 15 may be arranged in rows and columns along the first transverse direction Y and the second transverse direction X, and a maximum width of the plurality of contact plugs 15 along the first transverse direction Y may be smaller than a maximum width of the plurality of contact plugs 15 along the second transverse direction X, for example, cross-sectional shapes of the plurality of contact plugs 15 may be all elliptical shapes. In addition, in a specific implementation, the contact plug 15 may be formed by patterning a mask layer to determine the shape and the position thereof, and then etching the stacked structure 12 by using a dry etching process or a wet etching process.
In one embodiment, as shown in fig. 5, the plurality of dummy channel structures 14 may also be arranged in rows and columns along the second lateral direction X and the first lateral direction Y, and a maximum width of the dummy channel structures 14 adjacent to and in the same column as the contact plug 15 along the first lateral direction Y may also be smaller than a maximum width along the second lateral direction X, for example, the cross-sectional shape thereof may be an oval shape, so as to reduce a risk of merging of the contact plug 15 and the dummy channel structures 14 during the etching step.
In another embodiment, as shown in fig. 1, to improve the supporting effect of the dummy channel structures 14 in the step structure 12A, two adjacent rows of the dummy channel structures 14 may be arranged in a staggered manner in the first transverse direction X to increase the distribution density of the dummy channel structures 14 in the step structure 12A. Specifically, if a first plane is defined to be perpendicular to the substrate 11 and parallel to the second lateral direction X, then in two adjacent rows of dummy channel structures 14, a projection of each dummy channel structure 14 of one row on the first plane is located in an interval area between projections of two adjacent dummy channel structures 14 of the other row on the first plane, or located outside a projection of one outermost dummy channel structure 14 of the other row on the first plane.
Also, the plurality of contact plugs 15 may be uniformly distributed among the plurality of rows of dummy trench structures 14 and arranged in rows and columns along the second lateral direction X and the first lateral direction Y. Accordingly, each of the contact plugs 15 may correspond to one dummy channel structure combination 14A, and the dummy channel structure combination 14A may include three dummy channel structures 14 adjacent to the corresponding contact plug 15. For example, as shown in fig. 1, the dummy channel structure combination 14A corresponding to the contact plug 151 may be composed of a dummy channel structure 141, a dummy channel structure 142, and a dummy channel structure 143. Specifically, the maximum width of the dummy channel structures 141 in the dummy channel structure combination 14A, which are distributed in the same column with the corresponding contact plugs 151 in the first lateral direction Y, may be smaller than the maximum width in the second lateral direction X, for example, the cross-sectional shape thereof may be an elliptical shape. The three dummy channel structures 141/142/143 in the dummy channel structure combination 14A may be from two adjacent rows of dummy channel structures 14, specifically, two dummy channel structures 142/143 in the dummy channel structure combination 14A may be from the same row, and the projection of the corresponding contact plug 151 on the first plane is located in a spacing region between the projections of the two dummy channel structures 142/143 on the first plane, and the remaining dummy channel structures 141 may be from the other row and are distributed in the same column as the corresponding contact plugs 151 in the first transverse direction Y.
In one embodiment, the projections of the three dummy trench structures 141/142/143 on the substrate 11 in the dummy trench structure combination 14A may define an isosceles triangle or an equilateral triangle, and the projections of the corresponding contact plugs 151 on the substrate 11 may be located at the center positions of the isosceles triangle or the equilateral triangle, so as to ensure that each contact plug 15 and the three dummy trench structures 14 adjacent to it have a larger spacing distance with a fixed spacing distance between two adjacent rows of dummy trench structures 14.
In some embodiments, as shown in fig. 6, in each two adjacent rows of the dummy trench structures 14, one row of the dummy trench structures 14 may be linearly arranged in the second transverse direction X, and the other row of the dummy trench structures 14 may be waved in the second transverse direction X, for example, the first row of the dummy trench structures 14 in fig. 6 is linearly arranged along the imaginary straight line L1 in the second transverse direction X, and the second row of the dummy trench structures 14 in fig. 6 is waved along the imaginary waved line L2 in the second transverse direction X.
Specifically, a second plane may be defined to be perpendicular to the substrate 11 and parallel to the first transverse direction Y, one row of virtual channel structures 14 in two adjacent rows of the virtual channel structures 14, which are distributed in a straight line, may be a straight line row virtual channel structure, the other row of virtual channel structures 14 in a wavy line distribution may be a wavy line row virtual channel structure, projections of the virtual channel structures 14 in the straight line row virtual channel structures on the second plane may be located on the same straight line in the second plane, projections of the virtual channel structures 14 in the wavy line row virtual channel structures on the second plane may be located on two parallel straight lines in the second plane, and projections of any two adjacent virtual channel structures 14 in the wavy line row virtual channel structures on the second plane may be located on different straight lines respectively.
Further, in view of that, in the two adjacent rows of dummy channel structures 14, one of the two adjacent dummy channel structures 14 of the wavy line row dummy channel structure is far away from the straight line row dummy channel structure, and the other is close to the straight line row dummy channel structure, the contact plug 15 may be preferably distributed in the same column as the dummy channel structure 14 far away from the straight line row dummy channel structure in the wavy line row dummy channel structure in the first transverse direction Y, so that the separation distance between the contact plug 15 and the dummy channel structure 14 in the first transverse direction Y can be further increased compared with the scheme that all the rows of dummy channel structures 14 are linearly distributed in the second transverse direction X.
In a specific implementation, at least two rows of dummy trench structures 14 may exist between two adjacent rows of contact plugs 15 in the first lateral direction Y. Also, the cross-sectional shapes of the plurality of contact plugs 15 and/or the plurality of dummy channel structures 14 may also include a circular or square isocentric symmetry shape. The contact plug 15 and the dummy channel structure 14 having a circular or square cross-sectional shape may be formed by the same etching process as the contact plug 15 and the dummy channel structure 14 having an oval cross-sectional shape.
It is understood that, in the present embodiment, only one of the dummy channel structure 14 and the contact plug 15 in the step structure 12A, which has a high risk of merging, is designed to have a maximum width in the first lateral direction Y smaller than a maximum width in the second lateral direction X, for example, the cross-sectional shape of at least one of the dummy channel structure 14 and the contact plug 15 in the step structure 12A, which has a high risk of merging, is designed to be an elliptical shape having a long axis and a short axis, and the long axis direction of the elliptical shape is perpendicular to the direction of the connection line between the corresponding dummy channel structure 14 and the contact plug 15, so that the spacing distance between the dummy channel structure 14 and the contact plug 15 can be increased to avoid merging due to shape distortion under the condition that the position and area ratio of the dummy channel structure 14 and the contact plug 15 is fixed. Meanwhile, the cross-sectional shapes of the dummy channel structures 14 and the contact plugs 15 with low risk of merging in the step structures 12A are still conventional circular or square, so as to ensure that the dummy channel structures 14 and the contact plugs 15 can be effectively connected with peripheral circuits.
In order to ensure that the dummy trench structure 14 and the contact plug 15 having an elliptical cross-sectional shape can be effectively connected to a peripheral circuit, the ratio of the length of the minor axis to the length of the major axis of the elliptical shape may be in the range of 0.4 to 0.8. In one embodiment, the ratio of the length of the minor axis to the length of the major axis of the elliptical shape may be 0.7.
Different from the prior art, in the three-dimensional memory in this embodiment, by setting the maximum width of at least one of the plurality of contact plugs and the plurality of dummy channel structures along the first lateral direction (for example, the vertical lateral direction) to be smaller than the maximum width along the second lateral direction (for example, the horizontal lateral direction), the process window in the first lateral direction (for example, the vertical lateral direction) when the dummy channel structures and the contact plugs are formed by etching can be increased, so as to avoid the problem of merging of the dummy channel structures and the contact plugs during the etching process, and improve the performance of the three-dimensional memory.
Referring to fig. 7, fig. 7 is a schematic flow chart of a method for manufacturing a three-dimensional memory according to an embodiment of the present invention, where a specific flow of the method for manufacturing the three-dimensional memory may be as follows:
step S11: and forming a stacked structure on the substrate, wherein the stacked structure comprises a plurality of gate sacrificial layers and gate insulating layers which are stacked alternately, and the end parts of the gate sacrificial layers and the gate insulating layers form a step structure.
The substrate may be made of single crystal silicon, single crystal germanium, Silicon On Insulator (SOI), or the like. The gate sacrificial layer may be made of silicon nitride, the gate insulating layer may be made of silicon oxide, and the number of layers of the gate sacrificial layer may be determined according to the number of memory cells to be formed in the longitudinal direction. In specific implementation, a stacked structure of a gate insulating layer and a gate sacrificial layer may be formed on the substrate, and then the stacked structure may be etched, so that the stacked structure is stepped at one end of the second lateral direction.
Step S12: and forming a plurality of virtual channel structures on the step structures, wherein the virtual channel structures penetrate through the step structures.
Before step S12, the method may further include:
step A: and forming a dielectric layer covering the step structure.
Wherein. The dielectric layer may be made of an insulating material such as silicon oxide.
Specifically, a plurality of dummy channel structures may be formed on the step structure by etching using a first predetermined mask, the first predetermined mask may have a plurality of first openings, and a maximum width of at least one of the plurality of first openings along the first lateral direction is smaller than a maximum width of at least one of the plurality of first openings along the second lateral direction. In addition, when implemented, the step S12 may specifically include:
step S121: and etching the step structure and the dielectric layer by using a first preset mask to obtain a plurality of virtual channel holes. The plurality of virtual channel holes sequentially penetrate through the dielectric layer and the step structure in the longitudinal direction, and the substrate is exposed. The first preset mask is provided with a plurality of first openings, and the cross section of at least one of the first openings can be in an elliptical shape, so that the cross section of at least one of the virtual channel holes formed by etching is in an elliptical shape with a long axis and a short axis, and the long axis direction of the elliptical shape is in a second transverse direction.
Step S122: and forming a virtual channel structure in the virtual channel hole.
Step S13: and forming a plurality of contact plugs which are respectively and electrically connected with the gate layer at the positions of the step structures, wherein the plurality of virtual channel structures are arranged in a plurality of rows in a first transverse direction parallel to the substrate, the contact plugs are positioned between two adjacent rows of virtual channel structures, the maximum width of at least one of the plurality of contact plugs and the plurality of virtual channel structures along the first transverse direction is smaller than that along a second transverse direction, and the second transverse direction is parallel to the substrate and is vertical to the first transverse direction.
The contact plugs are perpendicular to the substrate, extend to the multiple steps of the step structure in the longitudinal direction, and are located between two adjacent rows of dummy channel structures, specifically, the cross-sectional shape of at least one of the contact plugs and the dummy channel structures may be an elliptical shape having a long axis and a short axis, and the long axis direction of the elliptical shape is the second transverse direction.
Specifically, a plurality of contact plugs are formed on the step structure by etching by using a second preset mask, the second preset mask is provided with a plurality of second openings, and the maximum width of at least one of the second openings along the first transverse direction is smaller than the maximum width along the second transverse direction. In addition, when implemented, the step S13 may specifically include:
step S131: and etching the step structure and the dielectric layer by using a second preset mask to obtain a plurality of contact holes. The second preset mask is provided with a plurality of second openings, and the cross section of at least one of the second openings can be in an elliptical shape, so that the cross section of at least one of the contact holes formed by etching is in an elliptical shape with a long axis and a short axis, and the long axis direction of the elliptical shape is in a second transverse direction.
Step S132: and forming a conductive material layer in the contact hole.
The conductive material layer may be made of a conductive material such as tungsten, and the conductive material layer extends in the longitudinal direction and is connected to a peripheral circuit, so as to connect each gate layer of the stacked structure to the peripheral circuit.
It is to be understood that the detailed implementation of the above embodiment of the three-dimensional memory may be referred to for the arrangement and the cross-sectional shape of the contact plugs and the dummy channel structures, and thus, the detailed description is omitted here. And by changing the arrangement and shape of the plurality of first openings on the first preset mask and the arrangement and shape of the plurality of second openings on the second preset mask, different arrangement and different cross-sectional shapes of the plurality of virtual channel structures and the plurality of contact plugs can be correspondingly realized.
In a specific embodiment, the plurality of gate sacrificial layers and the gate insulating layer may further form a core array structure connected to the step structure in a second lateral direction, and the method for manufacturing the three-dimensional memory may further include:
step S14: a plurality of channel holes are formed in the core array structure, perpendicular to the substrate, and through the stacked structure to expose the substrate.
Wherein the channel hole and the dummy channel hole may be formed by a same etching process.
Step S15: a channel structure is formed in the channel hole, the channel structure including a charge storage layer on a sidewall surface of the channel hole and a channel layer on a surface of the charge storage layer.
Specifically, a blocking oxide layer, a charge trapping layer, and a tunneling oxide layer, which are charge storage layers, and a semiconductor layer, which is a channel, may be sequentially deposited on sidewalls of the channel hole to obtain the above-described channel structure. The charge trapping layer may be made of silicon nitride, and the semiconductor layer may be made of polysilicon.
Specifically, the step S15 and the step S122 may be executed simultaneously, and the virtual channel structure and the channel structure may have substantially the same specific structure.
Step S16: and forming a grid line slit in the core array structure, wherein the grid line slit is perpendicular to the substrate and penetrates through the stacked structure to expose the substrate.
Step S17: and replacing the grid sacrificial layer with a grid layer through the grid line gap.
Specifically, a replacement process may be used to replace the gate sacrificial layer in the stacked structure and fill the same with a conductive material (e.g., tungsten) to form a corresponding gate layer. It is understood that the dummy channel structure is not removed in the step of removing the gate sacrificial layer, and thus the dummy channel structure can support the step structure so that the step structure is not easily collapsed.
Step S19: and forming a common source structure in the gate line slit, wherein the common source structure comprises a spacing layer positioned on the surface of the side wall of the gate line slit and a common source positioned on the surface of the spacing layer.
The spacer layer is an insulating layer, such as an oxide layer, the common source is made of a conductive material (such as titanium or titanium nitride, polysilicon and/or tungsten), and the bottom of the common source is connected to the substrate to provide a conductive channel for source connection.
Different from the prior art, the method for fabricating the three-dimensional memory in this embodiment includes forming a stack structure on a substrate, where the stack structure includes a plurality of gate layers and gate insulating layers stacked alternately, and step structures are formed at ends of the plurality of gate layers and the gate insulating layers, and then forming a plurality of dummy channel structures on the step structures of the stack structure, where the plurality of dummy channel structures pass through the step structures and form a plurality of contact plugs electrically connected to the gate layers at positions of the step structures, respectively, where the plurality of dummy channel structures are arranged in a plurality of rows in a first lateral direction parallel to the substrate, the contact plugs are located between two adjacent rows of dummy channel structures, and a maximum width of at least one of the plurality of contact plugs and the plurality of dummy channel structures in the first lateral direction is smaller than a maximum width of the contact plugs in a second lateral direction parallel to the substrate and perpendicular to the first lateral direction, therefore, the process window in the first transverse direction (for example, the vertical transverse direction) when the virtual channel structure and the contact plug are formed by etching can be increased, so that the problem of fusion of the virtual channel structure and the contact plug in the etching process is avoided, and the performance of the three-dimensional memory is improved.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (12)
1. A three-dimensional memory, comprising:
a substrate;
the stacked structure comprises a plurality of gate electrode layers and gate insulating layers which are stacked alternately, and the end parts of the plurality of gate electrode layers and the gate insulating layers form a step structure;
a plurality of dummy channel structures passing through the step structure of the stack structure;
a plurality of contact plugs electrically connected to the gate layer at positions of the step structures, respectively;
the dummy channel structures are arranged in a plurality of rows in a first transverse direction parallel to the substrate, the contact plugs are located between two adjacent rows of the dummy channel structures, the dummy channel structures include first dummy channel structures adjacent to and in the same column as the contact plugs in the first transverse direction, a maximum width of at least one of the first dummy channel structures and the contact plugs in the first transverse direction is smaller than a maximum width of the at least one of the first dummy channel structures and the contact plugs in a second transverse direction, and the second transverse direction is parallel to the substrate and perpendicular to the first transverse direction.
2. The three-dimensional memory according to claim 1, wherein a cross-sectional shape of at least one of the plurality of contact plugs and the plurality of dummy channel structures is an elliptical shape having a major axis and a minor axis, and a major axis direction of the elliptical shape is the second transverse direction.
3. The three-dimensional memory according to claim 1, wherein the plurality of contact plugs are arranged in rows and columns along the first and second lateral directions, and a maximum width of the plurality of contact plugs along the first lateral direction is smaller than a maximum width along the second lateral direction.
4. The three-dimensional memory according to claim 1 or 3, wherein two adjacent rows of the dummy channel structures are arranged in a staggered manner in the second transverse direction, each contact plug corresponds to a dummy channel structure combination, the dummy channel structure combination comprises three dummy channel structures adjacent to the corresponding contact plug, and the maximum width of the dummy channel structures in the dummy channel structure combination, which are distributed in the same column as the corresponding contact plugs in the first transverse direction, is smaller than the maximum width of the dummy channel structures in the second transverse direction.
5. The three-dimensional memory according to claim 4, wherein the projections of the three virtual channel structures in the virtual channel structure combination on the substrate enclose an isosceles triangle, and the projection of the corresponding contact plug on the substrate is located at the center of the isosceles triangle.
6. The three-dimensional memory according to claim 4, wherein in each two adjacent rows of the dummy trench structures, one row of the dummy trench structures is linearly arranged in the second transverse direction, and the other row of the dummy trench structures is waved in the second transverse direction.
7. The three-dimensional memory according to claim 4, wherein at least two rows of the dummy channel structures are present between two laterally adjacent rows of the contact plugs in the first direction.
8. The three-dimensional memory according to claim 1, wherein a cross-sectional shape of the plurality of contact plugs and/or the plurality of dummy channel structures comprises a circle or a square.
9. The three-dimensional memory according to claim 1, wherein the number of gate layers and gate insulating layers further form a core array structure connected to the step structure in the second lateral direction, the three-dimensional memory further comprising:
a plurality of channel structures passing through a core array structure of the stacked structure;
a common source structure perpendicular to the substrate and traversing the core array structure in the second lateral direction.
10. A method for manufacturing a three-dimensional memory is characterized by comprising the following steps:
forming a stacked structure on a substrate, wherein the stacked structure comprises a plurality of gate electrode layers and gate insulating layers which are stacked alternately, and the end parts of the plurality of gate electrode layers and the gate insulating layers form a step structure;
forming a plurality of dummy channel structures on a step structure of the stack structure, the plurality of dummy channel structures passing through the step structure;
forming a plurality of contact plugs which are electrically connected with the gate layer at the positions of the step structures respectively;
the dummy channel structures are arranged in a plurality of rows in a first transverse direction parallel to the substrate, the contact plugs are located between two adjacent rows of the dummy channel structures, the dummy channel structures include first dummy channel structures adjacent to and in the same column as the contact plugs in the first transverse direction, a maximum width of at least one of the first dummy channel structures and the contact plugs in the first transverse direction is smaller than a maximum width of the at least one of the first dummy channel structures and the contact plugs in a second transverse direction, and the second transverse direction is parallel to the substrate and perpendicular to the first transverse direction.
11. The method according to claim 10, wherein the forming of the plurality of dummy trench structures on the step structure specifically comprises:
and etching to form a plurality of virtual channel structures on the step structure by using a first preset mask, wherein the first preset mask is provided with a plurality of first openings, and the maximum width of at least one of the plurality of first openings along the first transverse direction is smaller than the maximum width along the second transverse direction.
12. The method for fabricating the three-dimensional memory according to claim 10, wherein the forming a plurality of contact plugs specifically comprises:
and etching to form a plurality of contact plugs on the step structure by utilizing a second preset mask, wherein the second preset mask is provided with a plurality of second openings, and the maximum width of at least one of the second openings along the first transverse direction is smaller than the maximum width along the second transverse direction.
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| CN111602244A (en) * | 2020-04-24 | 2020-08-28 | 长江存储科技有限责任公司 | Three-dimensional memory device with drain selection gate cutting structure and forming method thereof |
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| CN111602244A (en) * | 2020-04-24 | 2020-08-28 | 长江存储科技有限责任公司 | Three-dimensional memory device with drain selection gate cutting structure and forming method thereof |
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