CN112463675A - Program off-line downloading method - Google Patents
Program off-line downloading method Download PDFInfo
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- CN112463675A CN112463675A CN202011340079.4A CN202011340079A CN112463675A CN 112463675 A CN112463675 A CN 112463675A CN 202011340079 A CN202011340079 A CN 202011340079A CN 112463675 A CN112463675 A CN 112463675A
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- 238000000034 method Methods 0.000 title claims abstract description 50
- 230000015654 memory Effects 0.000 claims abstract description 52
- 230000006870 function Effects 0.000 claims description 19
- 238000004806 packaging method and process Methods 0.000 claims description 5
- 238000005538 encapsulation Methods 0.000 claims description 2
- 238000012942 design verification Methods 0.000 abstract description 3
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/61—Installation
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- Debugging And Monitoring (AREA)
Abstract
The invention provides a program off-line downloading method, which relates to the technical field of integrated circuit design verification and software engineering, and comprises the following steps: step S1, the offline downloader establishes data paths with the chip processor and the memory of the target board through the serial bus debug interface, respectively; step S2, the off-line downloader controls the chip processor to enter a debugging mode; step S3, the offline downloader writes a pre-generated program file into the memory; in step S4, the offline downloader controls the chip processor to exit the debugging mode to execute the program file. The method has the advantages of simple operation, reliable execution, and capability of realizing off-line program downloading, and provides a simple, reliable and practical scheme for the program downloading of the chip under certain conditions.
Description
Technical Field
The invention relates to the technical field of integrated circuit design verification and software engineering, in particular to a program offline downloading method.
Background
In the field of integrated circuit design verification, after a chip is subjected to a back-end, a common program downloading mode is a j-link simulator or an SWD mode, wherein the j-link simulator is a JATG simulator supporting an ARM core chip, and the SWD is a serial bus debugging interface. However, both of the above two methods must be performed with power on, and when the program cannot be downloaded with power on or needs to be downloaded offline, neither of the two existing methods can achieve program downloading, so a solution for achieving program offline downloading is needed.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a program offline downloading method, which comprises the steps of presetting a target board and an offline downloader, wherein the target board is provided with a chip processor, the chip processor comprises at least one memory, and the offline downloader is connected with the target board through a serial bus debugging interface;
the program offline downloading method comprises the following steps:
step S1, the offline downloader establishes data paths with the chip processor and the memory of the target board through the serial bus debug interface, respectively;
step S2, the off-line downloader controls the chip processor to enter a debugging mode;
step S3, the offline downloader writes a pre-generated program file into the memory;
in step S4, the offline downloader controls the chip processor to exit the debugging mode to execute the program file.
Preferably, in step S1, the offline downloader establishes data paths between a read function and a write function, which are obtained by pre-packaging, and the chip processor and the memory of the target board, respectively.
Preferably, before executing the step S1, a function packaging process is included, which includes:
and packaging the off-line downloader and the target board through the implementation mode of the process of establishing the data path by the serial bus debugging interface, and the implementation mode of the process of establishing the data path by the serial bus debugging interface, the chip processor and the memory of the target board to obtain the read function and the write function.
Preferably, the process of establishing a data path between the offline downloader and the target board through the serial bus debug interface includes:
step A1, the off-line downloader controls the serial bus debug interface of the target board to reset, so as to establish connection between the off-line downloader and the target board;
step A2, the off-line downloader performs read-write operation on the debugging access register associated with the serial bus debugging interface of the target board, so as to establish a data path between the off-line downloader and the target board.
Preferably, the debug access register includes a debug register and an access register.
Preferably, in step S2, the offline downloader controls the chip processor to enter a debug mode by configuring a register corresponding to the chip processor.
Preferably, a configuration file is burned in the memory in advance, and the configuration file includes a predefined storage sequence of the memory and a correspondence between addresses of the memory;
in step S3, the offline downloader calls the write function and writes the program files into the addresses of the corresponding memories according to the storage sequence.
Preferably, before executing step S4, the method further includes changing a program counter pointer and a stack pointer of the memory, so as to enable the program counter pointer and the stack pointer to point to corresponding addresses of the memory when the program file is executed.
Preferably, in step S4, the offline downloader configures and clears the register corresponding to the chip processor, and then reads the register to exit the debug mode.
The technical scheme has the following advantages or beneficial effects: the method has the advantages of simple operation and reliable execution, can realize off-line program downloading, and provides a simple, reliable and practical scheme for the program downloading of the chip under certain conditions.
Drawings
FIG. 1 is a flowchart illustrating a program offline downloading method according to a preferred embodiment of the present invention;
FIG. 2 is a flowchart illustrating a process of establishing a data path between an offline downloader and a target board via a serial bus debug interface according to a preferred embodiment of the present invention.
Detailed Description
The invention is described in detail below with reference to the figures and specific embodiments. The present invention is not limited to the embodiment, and other embodiments may be included in the scope of the present invention as long as the gist of the present invention is satisfied.
In a preferred embodiment of the present invention, based on the above problems in the prior art, there is provided a program offline download method, which includes presetting a target board and an offline downloader, the target board having a chip processor, the chip processor including at least one memory, the offline downloader being connected to the target board via a serial bus debug interface;
as shown in fig. 1, the program offline downloading method includes:
step S1, the off-line downloader establishes data paths with the chip processor and the memory of the target board respectively through the serial bus debugging interface;
step S2, the off-line downloader controls the chip processor to enter a debugging mode;
step S3, the off-line downloader writes a pre-generated program file into the memory;
in step S4, the off-line downloader controls the chip processor to exit the debug mode to execute the program file.
Specifically, in this embodiment, the program offline downloading method of the present application is implemented based on a serial bus debug interface, where the target board includes a chip processor that needs to perform offline program downloading, where the target board and the offline downloader both have serial bus debug interfaces, the target board and the offline downloader are connected to each other through their respective serial bus debug interfaces, the connection is physical connection, and a data path between the chip processor and a memory of the target board and the offline downloader is established on the basis that the target board and the offline downloader have the physical connection, so as to implement data interaction between the offline downloader and the target board.
Further, after the Chip Processor (CPU) establishes the data path, the offline downloader can control the chip processor to enter a debug mode (debug mode) through the data path, so as to subsequently write the program file into a Memory, where the Memory may be an SRAM (Static Random-Access Memory).
Preferably, the program file may be generated by keil compilation or GCC compilation, where the generated file is a hex file, and then the hex file is converted into an hx file and written into the memory as the program file.
Furthermore, after the program file is written into the memory, the control chip processor exits the debugging mode and enters a release mode, the program file is executed, and the off-line downloading process of the program file is completed. The whole process is simple to operate and reliable to execute, can realize off-line program downloading, and provides a simple, reliable and practical scheme for the program downloading of the chip under certain conditions.
In the preferred embodiment of the present invention, in step S1, the offline downloader establishes data paths between a read function and a write function, which are obtained by pre-packaging, and the chip processor and the memory of the target board, respectively.
In a preferred embodiment of the present invention, before the step S1 is executed, a function encapsulation process is included, which includes:
and packaging the off-line downloader and the target board by the serial bus debugging interface to obtain the read function and the write function.
Specifically, in this embodiment, the data path between the offline downloader and the chip processor and the memory of the target board includes two parts, one part is the data path between the offline downloader and the serial bus debug interface of the target board, and the other part is the data path between the serial bus debug interface of the target board and the memory between the chip processor and the memory, where the memory includes, but is not limited to, a flash memory and a ram memory. When establishing the data path between the offline downloader and the chip processor and the memory of the target board, both the two data paths need to be successfully established. The above-mentioned implementation mode of the process of establishing the data path between the off-line downloader and the target board through the serial bus debug interface, and the implementation mode of the process of establishing the data path between the serial bus debug interface of the target board and the chip processor and the memory are packaged as the implementation codes of the above-mentioned two processes and the related function calling mode, so as to be directly called.
As shown in fig. 2, the process of establishing the data path between the offline downloader and the target board through the serial bus debug interface includes:
step A1, the off-line downloader controls the serial bus debugging interface of the target board to reset so as to establish connection between the off-line downloader and the target board;
step A2, the off-line downloader performs read-write operation on the debug access register associated with the serial bus debug interface of the target board, so as to establish a data path between the off-line downloader and the target board.
Specifically, in this embodiment, a process in which the offline downloader and the target board establish a data path through the serial bus debug interface is an initialization process of the serial bus debug interface, the offline downloader controls the serial bus debug interface of the target board to reset by sending a reset signal to the target board, where the reset signal includes at least 50 pieces of 1 and at least two Idle signals that are sent continuously, and the Idle signal may be 0 that represents a low level, and at this time, the offline downloader establishes a connection with the target board, but the data path is not yet established.
Furthermore, after the off-line downloader is connected with the target board, read-write operation is performed through a debugging access register associated with a serial bus debugging interface of the target board, so that a data path is established between the off-line downloader and the target board.
In a preferred embodiment of the present invention, the debug access registers include debug registers and access registers.
Specifically, in this embodiment, the debugging register is a DP register, and the access register is an AP register, where the DP register is responsible for receiving external data to access an AP port, and further accesses internal resources. The above operations of reading and writing the DP register and the AP register include, but are not limited to, reading an IDCODE register (ID register), reading a CTRL/STAT register (DP control status register), writing a CTRL/STAT register (DP control status register), reading a CTRL/STAT register (DP control status register), writing a SELECT register (SELECT register), reading an AP CSW register, reading a RDBUFF register (buffer register), and writing a CSW register (AP control status register).
Further, the read-write operation is used to confirm that the read-in and write-in values are correct, so as to ensure that the initialization process is correct, and further ensure that the data path is successfully established. Different read-write operations are adopted for different registers, such as an IDCODE register, an identification code 0x0bb11477 is stored in the IDCODE register by default, the IDCODE register can be read, the read result is compared with the identification code stored by default, and when the read result is consistent with the identification code stored by default, the initialization process of the IDCODE register is finished and correct; if the CTRL/STAT register does not store the default value, the CTRL/STAT register may be written with a predetermined content by writing to the CTRL/STAT register, and then read, and the read result may be compared with the written predetermined content, and when the read result matches the predetermined content, the initialization process of the CTRL/STAT register is finished and correct. And finishing the initialization process of the serial bus debugging interface when the read-write operation of all the DP registers and the AP registers is finished and correct, and establishing a data path between the off-line downloader and the target board.
In a preferred embodiment of the present invention, in step S2, the offline downloader controls the chip processor to enter the debug mode by configuring the register corresponding to the chip processor.
Specifically, in this embodiment, different types of chip processors may need to configure different registers, and the configuration process and the specific configuration values of the specific registers are not the point of the invention of this application and are not described herein again.
In a preferred embodiment of the present invention, a configuration file is burned in advance in the memory, and the configuration file includes a predefined storage sequence of the memory and a correspondence between addresses of the memory;
the offline downloader calls the write function and writes the program files to the addresses of the corresponding memories, respectively, in the order of storage in step S3.
Specifically, the configuration file may be an flm file, the flm file matches with the type of the flash memory, and when the program is downloaded offline, the corresponding configuration file may be burned according to the type of the flash memory.
In a preferred embodiment of the present invention, before the step S4 is executed, the method further includes modifying the program counter pointer and the stack pointer of the memory, so that the program counter pointer and the stack pointer point to the corresponding addresses of the memory when the program file is executed.
Specifically, in this embodiment, the program counter pointer is used to point to a next instruction of the currently running instruction, the stack pointer is used for stack entering and stack popping operations of the program file in the memory, and the program file can be executed according to the pointer definition sequence by changing the program counter pointer and the stack pointer of the memory.
In a preferred embodiment of the present invention, in step S4, the offline downloader configures and clears the register corresponding to the chip processor, and then reads the register to exit the debug mode.
Specifically, in this embodiment, the offline downloader needs to perform the operation of reading the register again after configuring and clearing the register, so as to clear the register and exit the debug mode, and the register cannot be cleared and cannot exit the debug mode only by configuring and clearing.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
Claims (9)
1. A program off-line downloading method is characterized in that a target board and an off-line downloader are preset, a chip processor is arranged on the target board and comprises at least one memory, and the off-line downloader is connected with the target board through a serial bus debugging interface;
the program offline downloading method comprises the following steps:
step S1, the offline downloader establishes data paths with the chip processor and the memory of the target board through the serial bus debug interface, respectively;
step S2, the off-line downloader controls the chip processor to enter a debugging mode;
step S3, the offline downloader writes a pre-generated program file into the memory;
in step S4, the offline downloader controls the chip processor to exit the debugging mode to execute the program file.
2. The method for off-line downloading of a program according to claim 1, wherein in step S1, the off-line downloader establishes data paths between a read function and a write function, which are pre-packaged, and the chip processor and the memory of the target board, respectively.
3. The method for downloading programs from a storage device according to claim 2, wherein before performing step S1, the method comprises a function encapsulation process:
and packaging the off-line downloader and the target board through the implementation mode of the process of establishing the data path by the serial bus debugging interface, and the implementation mode of the process of establishing the data path by the serial bus debugging interface, the chip processor and the memory of the target board to obtain the read function and the write function.
4. The program offline downloading method of claim 3, wherein the process of the offline downloader and the target board establishing a data path through the serial bus debug interface comprises:
step A1, the off-line downloader controls the serial bus debug interface of the target board to reset, so as to establish connection between the off-line downloader and the target board;
step A2, the off-line downloader performs read-write operation on the debugging access register associated with the serial bus debugging interface of the target board, so as to establish a data path between the off-line downloader and the target board.
5. The program offline download method of claim 4, wherein the debug access registers comprise debug registers and access registers.
6. The method for off-line program downloading according to claim 1, wherein in step S2, the off-line downloader controls the chip processor to enter a debug mode by configuring a register corresponding to the chip processor.
7. The off-line program downloading method of claim 2, wherein a configuration file is pre-programmed into the memory, and the configuration file includes a predefined storage sequence of the memory and a correspondence between addresses of the memory;
in step S3, the offline downloader calls the write function and writes the program files into the addresses of the corresponding memories according to the storage sequence.
8. The method for off-line program downloading of claim 7, wherein before executing step S4, the method further comprises changing a program counter pointer and a stack pointer of the memory to enable the program counter pointer and the stack pointer to point to corresponding addresses of the memory when the program file is executed.
9. The method for off-line program downloading according to claim 6, wherein in step S4, the off-line downloader clears the configuration of the register corresponding to the chip processor, and then reads the register to exit the debug mode.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011340079.4A CN112463675A (en) | 2020-11-25 | 2020-11-25 | Program off-line downloading method |
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| CN202011340079.4A CN112463675A (en) | 2020-11-25 | 2020-11-25 | Program off-line downloading method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113176861A (en) * | 2021-05-25 | 2021-07-27 | 北京物芯科技有限责任公司 | Method and device for realizing memory access and memory |
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| CN102609288A (en) * | 2012-02-14 | 2012-07-25 | 上海三一精机有限公司 | FPGA/CPLD (Field Programmable Gate Array/Complex Programmable Logic Device)-based program downloader |
| CN204808308U (en) * | 2015-04-24 | 2015-11-25 | 南京锆石光电科技有限公司 | FPGACPLD procedure downloader based on programmable logic chip |
| CN106407522A (en) * | 2016-08-31 | 2017-02-15 | 德为显示科技股份有限公司 | FPGA-based logic IP bus interconnection realization device |
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2020
- 2020-11-25 CN CN202011340079.4A patent/CN112463675A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1332409A (en) * | 2000-07-05 | 2002-01-23 | 先进数字芯片股份有限公司 | Central processing unit capable of testing and debugging program easily |
| CN102609288A (en) * | 2012-02-14 | 2012-07-25 | 上海三一精机有限公司 | FPGA/CPLD (Field Programmable Gate Array/Complex Programmable Logic Device)-based program downloader |
| CN204808308U (en) * | 2015-04-24 | 2015-11-25 | 南京锆石光电科技有限公司 | FPGACPLD procedure downloader based on programmable logic chip |
| CN106407522A (en) * | 2016-08-31 | 2017-02-15 | 德为显示科技股份有限公司 | FPGA-based logic IP bus interconnection realization device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113176861A (en) * | 2021-05-25 | 2021-07-27 | 北京物芯科技有限责任公司 | Method and device for realizing memory access and memory |
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