CN112462836A - POK circuit applied to LDO with delay function and LDO circuit - Google Patents

POK circuit applied to LDO with delay function and LDO circuit Download PDF

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Publication number
CN112462836A
CN112462836A CN202011476762.0A CN202011476762A CN112462836A CN 112462836 A CN112462836 A CN 112462836A CN 202011476762 A CN202011476762 A CN 202011476762A CN 112462836 A CN112462836 A CN 112462836A
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circuit
output
input
inverter
nmos tube
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CN112462836B (en
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闫兆文
姚和平
汪西虎
唐威
苏海伟
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Shanghai Wei'an Semiconductor Co ltd
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Shanghai Wei'an Semiconductor Co ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/462—Regulating voltage or current wherein the variable actually regulated by the final control device is dc as a function of the requirements of the load, e.g. delay, temperature, specific voltage/current characteristic
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Manipulation Of Pulses (AREA)
  • Pulse Circuits (AREA)

Abstract

The invention discloses a POK circuit with a delay function applied to an LDO and the LDO circuit, and belongs to the technical field of power management. The POK circuit obtains a high level or a low level by comparing the feedback voltage with the reference voltage (the first reference voltage and the second reference voltage), so as to control the discharging or charging of the charging and discharging circuit, and the output circuit outputs a self-detection signal which can be delayed according to the difference of the voltages at two ends of the charging and discharging circuit before and after the charging and discharging circuit is fully charged.

Description

POK circuit applied to LDO with delay function and LDO circuit
Technical Field
The present invention relates to the field of power management technologies, and in particular, to a low-dropout linear regulator (LDO) and a pok (power ok) circuit with delay function.
Background
In recent years, with the continuous development of electronic technology, especially the prevalence of portable intelligent products such as intelligent terminals (e.g., mobile phones, notebooks), and automotive electronic devices, power supplies play an important role in these portable electronic products, and meanwhile, the requirements on the performance, volume, cost, and the like of the portable electronic products are also increasing. Therefore, higher requirements are put on the aspects of strong function, high precision, high stability and intellectualization of a power management IC (integrated Circuit chip) chip, and the quality of the power management IC directly influences the power supply efficiency and the service life of a power supply, and the precision, the stability, the reliability and other performances of the whole electronic product. LDOs are an important component of power management chips, and low voltage drop, low power consumption and high power supply rejection ratio have become hot research points in recent years. However, the existing LDO circuit does not have a power supply delay function.
Disclosure of Invention
Aiming at the defect that the conventional LDO circuit does not have the function of delaying power supply, the POK circuit and the LDO circuit which are applied to the LDO with the delay function and aim at realizing the voltage delay function are provided.
The invention provides a POK circuit with delay function applied to LDO, comprising: the self-checking circuit comprises an input voltage end, a bias voltage end, a feedback voltage end, a self-checking signal end, a first reference voltage end, a second reference voltage end, a comparison circuit and an output circuit;
the comparison circuit comprises five input ends and an output end, wherein the first input end is connected with the feedback voltage end, the second input end is connected with the first reference voltage end, the third input end is connected with the second reference voltage end, the fourth input end is connected with the input voltage end, the fifth input end is connected with the power ground, the comparison circuit is used for adjusting the state of a first level signal at the output end of the comparison circuit according to the feedback voltage of the feedback voltage end, the first reference voltage of the first reference voltage end and the second reference voltage of the second reference voltage end, and the state of the first level signal comprises a high level signal and a low level delay signal;
further comprising:
the charge and discharge circuit comprises four input ends, an output end, a second phase inverter, a third phase inverter, a second NMOS tube, a third PMOS tube, a second PMOS tube, a first capacitor, a fourth phase inverter and a fifth phase inverter, and is used for charging or discharging according to the state of the first level signal to generate a second level signal output from the output end of the charge and discharge circuit;
the input end of the second phase inverter forms a first input end of the charge-discharge circuit and is connected with the output end of the comparison circuit;
the third inverter is connected with the second inverter in series, and the input end of the third inverter is connected with the output end of the second inverter;
the grid electrode of the second NMOS tube is connected with the output end of the third phase inverter, and the source electrode of the second NMOS tube is connected with a power ground;
the drain electrode of the third PMOS tube is connected with the drain electrode of the second NMOS tube;
the source electrode of the second PMOS tube forms a second input end of the charge-discharge circuit and is connected with the input voltage end, the drain electrode of the second PMOS tube is connected with the source electrode of the third PMOS tube, and the grid electrode of the second PMOS tube and the grid electrode of the third PMOS tube are connected to form a third input end of the charge-discharge circuit and connected with the bias voltage end;
one end of the first capacitor is connected with the drain electrode of the second NMOS tube and the drain electrode of the third PMOS tube, and the other end of the first capacitor is connected with the source electrode of the second NMOS tube to form a fourth input end of the charge-discharge circuit and connected with a power ground;
the input end of the fourth inverter is connected with one end of the first capacitor;
the fifth inverter is connected with the fourth inverter in series, the input end of the fifth inverter is connected with the output end of the fourth inverter, and the output end of the fifth inverter forms the output end of the charge-discharge circuit;
output circuit, including three input and an output, first input with charge and discharge circuit's output is connected, and the second input is connected the input voltage end, third input connection power ground, output circuit's output is connected the self-checking signal end, output circuit is used for the basis second level signal generates follows the self-checking signal of output circuit's output.
Optionally, the comparison circuit further includes:
the inverting end of the operational amplifier forms the first input end of the comparison circuit, and the power supply end of the operational amplifier forms the fourth input end of the comparison circuit;
the grid electrode of the first NMOS tube is connected with the output end of the operational amplifier, and the source electrode and the power ground end of the operational amplifier jointly form a fifth input end of the comparison circuit;
the input end of the first phase inverter is connected with the drain electrode of the first NMOS tube;
a grid electrode of the fifth NMOS tube is connected with the output end of the first phase inverter, and a source electrode of the fifth NMOS tube forms a third input end of the comparison circuit;
a gate of the sixth NMOS transistor is connected with the input terminal of the first inverter and the drain of the first NMOS transistor to form the output terminal of the comparison circuit, a source of the sixth NMOS transistor forms the second input terminal of the comparison circuit, and a drain of the sixth NMOS transistor is connected with the drain of the fifth NMOS transistor and the non-inverting terminal of the operational amplifier.
Optionally, the comparison circuit further includes a filter circuit;
the filter circuit comprises an input end and two output ends, the input end of the filter circuit is connected with the drain electrode of the sixth NMOS tube and the drain electrode of the fifth NMOS tube, the first output end of the filter circuit is connected with the in-phase end of the operational amplifier, and the second output end of the filter circuit is connected with the power ground.
Optionally, the filter circuit further includes:
one end of the third resistor forms an input end of the filter circuit;
and one end of the second capacitor is connected with the other end of the third resistor to form a first output end of the filter circuit, and the other end of the second capacitor forms a second output end of the filter circuit.
Optionally, the output circuit further includes:
a source electrode of the third NMOS tube is connected with a power ground;
a grid electrode of the fourth NMOS tube and a grid electrode of the third NMOS tube are connected to form a first input end of the output circuit together, and a source electrode of the fourth NMOS tube and a source electrode of the third NMOS tube are connected to form a third input end of the output circuit together;
one end of the fifth resistor is connected with the drain electrode of the third NMOS tube;
one end of the sixth resistor is connected with the drain electrode of the fourth NMOS tube, the other end of the sixth resistor is connected with the other end of the fifth resistor,
and one end of the fourth resistor, the other end of the fifth resistor and the other end of the sixth resistor are connected to form an output end of the output circuit, and the other end of the fourth resistor forms a second input end of the output circuit.
The invention also provides an LDO circuit capable of delaying, which comprises the POK circuit applied to the LDO with the delay function.
The invention provides a POK circuit with a delay function and an LDO circuit, wherein the POK circuit obtains a high level or a low level by comparing a feedback voltage with a reference voltage (a first reference voltage and a second reference voltage), so as to control the discharge or charge of a charge-discharge circuit, and an output circuit outputs a self-detection signal which can be delayed according to the difference of voltages at two ends of the charge-discharge circuit before and after the charge-discharge circuit is fully charged and discharged.
Drawings
Fig. 1 is a circuit diagram of an embodiment of a POK circuit applied to a delay function in an LDO according to the present invention;
FIG. 2 is a circuit diagram of an embodiment of a delayable LDO circuit according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
The invention is further described with reference to the following drawings and specific examples, which are not intended to be limiting.
Example one
Referring to fig. 1, the present embodiment provides a POK circuit with a delay function for an LDO, including: input voltage terminal VINBias voltage terminal VBiasFeedback voltage terminal VFBA self-checking signal terminal POK and a first reference voltage terminal VREF_LAnd a second reference voltage terminal VREF_HThe comparison circuit 1 and the output circuit 3 further include: and a charge and discharge circuit 2.
It should be noted that the feedback voltage terminal VFBA feedback voltage end V for the output of the LDO circuitFBFirst reference voltage terminal VREF_LIs higher than the voltage value of the second reference voltage terminal VREF _ H.
The comparison circuit 1 comprises five input ends and an output end, wherein the first input end is connected with the feedback voltage end VFBA second input terminal connected to the first reference voltage terminal VREF_LA third input terminal connected to the second reference voltage terminal VREF_HA fourth input terminal connected to the input voltage terminal VINA fifth input terminal connected to ground GND, and a comparison circuit 1 for comparing the feedback voltageFBSaid first reference voltage terminal VREF_LAnd said second reference voltage terminal VREF_HAdjusts the state of a first level signal at the output of the comparison circuit 1, the state of the first level signal comprising a low level signal and a high voltageThe signal is delayed.
Further, the comparison circuit 1 further includes: an operational amplifier EA, a first NMOS transistor NM1, a first inverter INV1, a fifth NMOS transistor NM5, and a sixth NMOS transistor NM 6.
An operational amplifier EA, the inverting terminal of which forms the first input terminal of the comparison circuit 1, the supply terminal V of whichDDForming a fourth input of the comparison circuit 1;
a first NMOS transistor NM1, a gate of the first NMOS transistor NM1 is connected to the output terminal of the operational amplifier EA, and a source of the first NMOS transistor NM1 and a power ground of the operational amplifier EA together form a fifth input terminal of the comparison circuit 1;
a first inverter INV1, an input end of the first inverter INV1 is connected to the drain of the first NMOS transistor NM 1;
a fifth NMOS transistor NM5, a gate of the fifth NMOS transistor NM5 is connected to an output terminal of the first inverter INV1, and a source thereof forms a third input terminal of the comparison circuit 1;
a sixth NMOS transistor NM6, a gate of the sixth NMOS transistor NM6 is connected to an input terminal of the first inverter INV1 and a drain of the first NMOS transistor NM1 to form an output terminal of the comparison circuit 1, a source of the sixth NMOS transistor NM6 forms a second input terminal of the comparison circuit 1, and a drain of the sixth NMOS transistor NM6 is connected to a drain of the fifth NMOS transistor NM5 and a non-inverting terminal of the operational amplifier EA.
In this embodiment, the operational amplifier EA inputs the feedback voltage terminal VFBThe feedback voltage (the feedback voltage output by the LDO circuit) and the first reference voltage terminal VREF_LWhen the feedback voltage is higher than the first reference voltage, indicating that the LDO output state is normal, the operational amplifier EA outputs a low level signal, the cut-off first NMOS transistor NM1 outputs a high level signal, the sixth NMOS transistor NM6 is turned on, and the fifth NMOS transistor NM5 is turned off. When the feedback voltage is lower than the first reference voltage, indicating that the output state of the LDO is abnormal, the operational amplifier EA outputs a high voltage signal, the first NMOS transistor NM1 is turned on, the sixth NMOS transistor NM6 is turned off, the fifth NMOS transistor NM5 is turned on, and the reference voltage is adjusted by the first reference voltageThe first reference voltage is switched to the second reference voltage, so that the turned-on first NMOS transistor NM1 generates a low-level delay signal (i.e., a voltage hysteresis window of the self-test signal terminal POK).
In a preferred embodiment, the comparison circuit 1 may further include a filter circuit; the filter circuit comprises an input end and two output ends, the input end of the filter circuit is connected with the drain electrode of the sixth NMOS tube NM6 and the drain electrode of the fifth NMOS tube NM5, the first output end of the filter circuit is connected with the in-phase end of the operational amplifier EA, and the second output end of the filter circuit is connected with a power ground GND.
Specifically, the filter circuit may further include: a third resistor R3 and a second capacitor C2.
A third resistor R3, one end of the third resistor R3 forming an input of the filter circuit;
and one end of the second capacitor C2 and the other end of the third resistor R3 are connected to form a first output end of the filter circuit, and the other end of the second capacitor C2 forms a second output end of the filter circuit.
The charging and discharging circuit 2 comprises four input ends and an output end, a second inverter INV2, a third inverter INV3, a second NMOS transistor NM2, a third PMOS transistor PM3, a second PMOS transistor PM2, a first capacitor C1, a fourth inverter INV4 and a fifth inverter INV5, and the charging and discharging circuit 2 is used for charging or discharging according to the state of the first level signal to generate a second level signal output from the output end of the charging and discharging circuit 2;
the input end of the second inverter INV2 forms the first input end of the charging and discharging circuit 2 and is connected with the output end of the comparison circuit 1;
a third inverter INV3 connected in series with the second inverter INV2, wherein an input end of the third inverter INV3 is connected to an output end of the second inverter INV 2;
a second NMOS transistor NM2, a gate of the second NMOS transistor NM2 is connected to the third inverter INV3, and a source of the second NMOS transistor NM2 is connected to a power ground GND;
a third PMOS transistor PM3, a drain of the third PMOS transistor PM3 being connected to a drain of the second NMOS transistor NM 2;
a second PMOS transistor PM2, a source of the second PMOS transistor PM2 forming a second input terminal of the charging and discharging circuit 2 and the input voltage terminal VINThe drain of the second PMOS transistor PM2 is connected to the source of the third PMOS transistor PM3, and the gate of the second PMOS transistor PM2 is connected to the gate of the third PMOS transistor PM3 to form the third input terminal and the bias voltage terminal V of the charge and discharge circuit 2BiasConnecting;
a first capacitor C1, one end of the first capacitor C1 is connected to the drain of the second NMOS transistor NM2 and the drain of the third PMOS transistor PM3, and the other end of the first capacitor C1 is connected to the source of the second NMOS transistor NM2 to form a fourth input end of the charge and discharge circuit 2, which is connected to the power ground GND;
an input end of the fourth inverter INV4, and an input end of the fourth inverter INV4 is connected to one end of the first capacitor C1;
the fifth inverter INV5 is connected in series with the fourth inverter INV4, an input end of the fifth inverter INV5 is connected with an output end of the fourth inverter INV4, and an output end of the fifth inverter INV5 forms an output end of the charging and discharging circuit 2.
An output circuit 3 including three input terminals and an output terminal, the first input terminal is connected with the output terminal of the charge and discharge circuit 2, the second input terminal is connected with the input voltage terminal VINThe third input end is connected to a power ground GND, the output end of the output circuit 3 is connected to the self-test signal end POK, and the output circuit 3 is configured to generate a self-test signal output from the output end of the output circuit 3 according to the second level signal.
Further, the output circuit 3 further includes: a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth resistor R5, a sixth resistor R6, and a fourth resistor R4.
A third NMOS transistor NM3, wherein the source of the third NMOS transistor NM3 is connected to a power ground GND;
a fourth NMOS transistor NM4, a gate of the fourth NMOS transistor NM4 and a gate of the third NMOS transistor NM3 are connected to form a first input terminal of the output circuit 3, and a source of the fourth NMOS transistor NM4 and a source of the third NMOS transistor NM3 are connected to form a third input terminal of the output circuit 3;
a fifth resistor R5, wherein one end of the fifth resistor R5 is connected to the drain of the third NMOS transistor NM 3;
a sixth resistor R6, one end of the sixth resistor R6 being connected to the drain of the fourth NMOS transistor NM4, the other end of the sixth resistor R6 being connected to the other end of the fifth resistor R5,
one end of the fourth resistor R4, the other end of the fifth resistor R5, and the other end of the sixth resistor R6 are connected to form an output end of the output circuit 3, and the other end of the fourth resistor R4 forms a second input end of the output circuit 3.
In this embodiment, when the second level signal output by the charge and discharge circuit 2 is a low level signal, the third NMOS 3 and the fourth NMOS 4 are both in the off state, and the voltage of the self-test signal terminal POK is input to the voltage terminal VINPulling up, and outputting a high level signal from a self-detection signal end POK of the output circuit 3; when the second level signal output by the charge and discharge circuit 2 is a high level signal, the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are both in a conducting state, the voltage output by the self-test signal terminal POK is pulled low, and finally the self-test signal output by the output circuit 3 is a delayed low level signal.
In the present embodiment, the POK circuit with delay function applied to the LDO utilizes the charging time period of the first capacitor C1 in the charging and discharging circuit 2 as the delay time of the POK circuit. By connecting a feedback voltage terminal VFBThe feedback voltage is compared with reference voltages (a first reference voltage and a second reference voltage) to obtain a high level or a low level, the waveform of the level signal is shaped through the two-stage inverter, and then a stable level signal is obtained to form a stable high level or a stable low level, so that the on-off of a second NMOS tube NM2 in the charging and discharging circuit 2 is controlled to realize the discharging or charging of the first capacitor C1. The output circuit is controlled according to different control levels output by the first capacitor C1 according to the voltage difference between the two ends of the first capacitor C1 before and after the first capacitor C1 is fully charged and dischargedThe third NMOS transistor NM3 and the fourth NMOS transistor NM4 in fig. 3 are turned on or off, and finally output a high or low level state. Meanwhile, the first reference voltage and the second reference voltage are utilized, the self-checking signal voltage hysteresis window of the self-checking signal terminal POK is realized, and the circuit has the advantages of simple structure, small chip occupation area and low cost.
The working principle of the POK circuit with the delay function applied to the LDO is as follows: the operational amplifier EA couples the input feedback voltage (the feedback voltage output by the LDO circuit) with the first reference voltage terminal VREF_LWhen the feedback voltage is higher than the first reference voltage, indicating that the output state of the LDO is normal, the operational amplifier EA outputs a low level signal, the first NMOS tube NM1 is turned off, the sixth NMOS tube NM6 is turned on, the fifth NMOS tube NM5 is turned off, a stable high level signal is output through the second inverter INV2 and the third inverter INV3, the second NMOS tube NM2 is turned on to discharge the first capacitor C1, the voltage across the first capacitor C1 is low, a stable low level signal is output through the output ends of the fourth inverter INV4 and the fifth inverter INV5, the third NMOS tube NM3 and the fourth NMOS tube NM4 are both in the turned off state, the voltage of the self-detection signal is pulled high by the input voltage, and the final output self-detection signal is a high level signal;
when the feedback voltage end VFBThe feedback voltage is lower than the first reference voltage end VREF_LWhen the first reference voltage is higher than the second reference voltage, the output state of the LDO is abnormal, the operational amplifier EA outputs a high voltage signal, the first NMOS transistor NM1 is turned on, the sixth NMOS transistor NM6 is turned off, the fifth NMOS transistor NM5 is turned on, and the reference voltage is output from the first reference voltage terminal VREF_LIs switched to a second reference voltage terminal VREF_HThereby generating a low-level delay signal (i.e., a voltage hysteresis window of the self-test signal at the self-test signal terminal POK), outputting a stable low level through the output terminals of the second inverter INV2 and the third inverter INV3, turning off the second NMOS 2, charging the first capacitor C1 when the third PMOS transistor PM3 and the second PMOS transistor PM2 are in the on state based on the bias voltage, so that the voltage across the first capacitor C1 becomes a high voltage, and generating a stable high level signal through the output terminals of the fourth inverter INV4 and the fifth inverter INV5The third NMOS transistor NM3 and the fourth NMOS transistor NM4 are both in a conducting state, the voltage of the self-test signal at the self-test signal terminal POK is pulled low, and the final output self-test signal is a delayed low-level signal.
The POK circuit outputs different control levels through different voltages at two ends of the first capacitor C1 before and after the first capacitor C1 is fully charged and discharged, and further the third PMOS tube PM3 and the second PMOS tube PM2 are switched on or switched off, so that the self-checking of the self-checking signal on the output state of the LDO circuit is finally effectively realized, and the charging time of the first capacitor C1 is the delay time of the self-checking signal.
Example two
The embodiment also provides a delayable LDO circuit, which comprises the POK circuit applied to the LDO with delay function.
The delayable LDO circuit shown in fig. 2 includes an LDO chip 4, a first resistor R1, and a second resistor R2, wherein a POK circuit applied to the LDO with a delay function is embedded in the LDO chip 4, an output voltage signal OUT of the LDO is divided by the first resistor R1 and the second resistor R2 to generate a feedback voltage via a feedback voltage terminal VFBAn inverting terminal electrically input to an operational amplifier EA of a POK circuit and a first reference voltage terminal VREF_LThe first reference voltage is compared, a self-detection signal end POK is generated through the processing of the POK circuit, whether the LDO circuit is normal or not is identified according to the level state of the self-detection signal end POK, if the self-detection signal end POK is a high level signal, the output state of the LDO circuit is normal, and if the self-detection signal end POK is a delayed low level signal, the output state of the LDO circuit is abnormal.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.

Claims (6)

1. A POK circuit applied to a band delay function in an LDO (low dropout regulator) comprises: the self-checking circuit comprises an input voltage end, a bias voltage end, a feedback voltage end, a self-checking signal end, a first reference voltage end, a second reference voltage end, a comparison circuit and an output circuit;
the comparison circuit comprises five input ends and an output end, wherein the first input end is connected with the feedback voltage end, the second input end is connected with the first reference voltage end, the third input end is connected with the second reference voltage end, the fourth input end is connected with the input voltage end, the fifth input end is connected with the power ground, the comparison circuit is used for adjusting the state of a first level signal at the output end of the comparison circuit according to the feedback voltage of the feedback voltage end, the first reference voltage of the first reference voltage end and the second reference voltage of the second reference voltage end, and the state of the first level signal comprises a high level signal and a low level delay signal;
it is characterized by also comprising:
the charge and discharge circuit comprises four input ends, an output end, a second phase inverter, a third phase inverter, a second NMOS tube, a third PMOS tube, a second PMOS tube, a first capacitor, a fourth phase inverter and a fifth phase inverter, and is used for charging or discharging according to the state of the first level signal to generate a second level signal output from the output end of the charge and discharge circuit;
the input end of the second phase inverter forms a first input end of the charge-discharge circuit and is connected with the output end of the comparison circuit;
the third inverter is connected with the second inverter in series, and the input end of the third inverter is connected with the output end of the second inverter;
the grid electrode of the second NMOS tube is connected with the output end of the third phase inverter, and the source electrode of the second NMOS tube is connected with a power ground;
the drain electrode of the third PMOS tube is connected with the drain electrode of the second NMOS tube;
the source electrode of the second PMOS tube forms a second input end of the charge-discharge circuit and is connected with the input voltage end, the drain electrode of the second PMOS tube is connected with the source electrode of the third PMOS tube, and the grid electrode of the second PMOS tube and the grid electrode of the third PMOS tube are connected to form a third input end of the charge-discharge circuit and connected with the bias voltage end;
one end of the first capacitor is connected with the drain electrode of the second NMOS tube and the drain electrode of the third PMOS tube, and the other end of the first capacitor is connected with the source electrode of the second NMOS tube to form a fourth input end of the charge-discharge circuit and connected with a power ground;
the input end of the fourth inverter is connected with one end of the first capacitor;
the fifth inverter is connected with the fourth inverter in series, the input end of the fifth inverter is connected with the output end of the fourth inverter, and the output end of the fifth inverter forms the output end of the charge-discharge circuit;
output circuit, including three input and an output, first input with charge and discharge circuit's output is connected, and the second input is connected the input voltage end, third input connection power ground, output circuit's output is connected the self-checking signal end, output circuit is used for the basis second level signal generates follows the self-checking signal of output circuit's output.
2. The POK circuit applied to the LDO band delay function of claim 1, wherein the comparison circuit further comprises:
the inverting end of the operational amplifier forms the first input end of the comparison circuit, and the power supply end of the operational amplifier forms the fourth input end of the comparison circuit;
the grid electrode of the first NMOS tube is connected with the output end of the operational amplifier, and the source electrode and the power ground end of the operational amplifier jointly form a fifth input end of the comparison circuit;
the input end of the first phase inverter is connected with the drain electrode of the first NMOS tube;
a grid electrode of the fifth NMOS tube is connected with the output end of the first phase inverter, and a source electrode of the fifth NMOS tube forms a third input end of the comparison circuit;
a gate of the sixth NMOS transistor is connected with the input terminal of the first inverter and the drain of the first NMOS transistor to form the output terminal of the comparison circuit, a source of the sixth NMOS transistor forms the second input terminal of the comparison circuit, and a drain of the sixth NMOS transistor is connected with the drain of the fifth NMOS transistor and the non-inverting terminal of the operational amplifier.
3. The POK circuit applied to the LDO band delay function of claim 2, wherein the comparison circuit further comprises a filter circuit;
the filter circuit comprises an input end and two output ends, the input end of the filter circuit is connected with the drain electrode of the sixth NMOS tube and the drain electrode of the fifth NMOS tube, the first output end of the filter circuit is connected with the in-phase end of the operational amplifier, and the second output end of the filter circuit is connected with the power ground.
4. The POK circuit applied to the LDO band delay function of claim 3, wherein the filter circuit further comprises:
one end of the third resistor forms an input end of the filter circuit;
and one end of the second capacitor is connected with the other end of the third resistor to form a first output end of the filter circuit, and the other end of the second capacitor forms a second output end of the filter circuit.
5. The POK circuit applied to the LDO with delay function of claim 1, wherein the output circuit further comprises:
a source electrode of the third NMOS tube is connected with a power ground;
a grid electrode of the fourth NMOS tube and a grid electrode of the third NMOS tube are connected to form a first input end of the output circuit together, and a source electrode of the fourth NMOS tube and a source electrode of the third NMOS tube are connected to form a third input end of the output circuit together;
one end of the fifth resistor is connected with the drain electrode of the third NMOS tube;
one end of the sixth resistor is connected with the drain electrode of the fourth NMOS tube, the other end of the sixth resistor is connected with the other end of the fifth resistor,
and one end of the fourth resistor, the other end of the fifth resistor and the other end of the sixth resistor are connected to form an output end of the output circuit, and the other end of the fourth resistor forms a second input end of the output circuit.
6. A delayable LDO circuit, comprising the POK circuit of claims 1-5 applied to a band delay function of the LDO.
CN202011476762.0A 2020-12-15 2020-12-15 POK circuit with delay function applied to LDO (Low dropout regulator) and LDO circuit Active CN112462836B (en)

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CN108512537A (en) * 2018-07-10 2018-09-07 上海艾为电子技术股份有限公司 A kind of electrification reset circuit and electrification reset device
CN208424329U (en) * 2018-07-24 2019-01-22 上海芯泽电子科技有限公司 One kind zero quiescent dissipation suitable for RFID chip powers on a little adjustable reset circuit
CN110212902A (en) * 2019-06-28 2019-09-06 成都信息工程大学 A kind of electrification reset circuit

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CN205015388U (en) * 2015-09-29 2016-02-03 龙威国际有限公司 Controllable formula low -voltage detection chip and power management chip delay
CN206331020U (en) * 2016-08-12 2017-07-14 上海太矽电子科技有限公司 The controllable undervoltage detection means of anti-interference delay
CN106533407A (en) * 2016-11-09 2017-03-22 上海华力微电子有限公司 Power on reset circuit
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