CN112462192A - ADC frequency increasing system and method for aviation cable fault detection based on TDR technology - Google Patents

ADC frequency increasing system and method for aviation cable fault detection based on TDR technology Download PDF

Info

Publication number
CN112462192A
CN112462192A CN202011218557.4A CN202011218557A CN112462192A CN 112462192 A CN112462192 A CN 112462192A CN 202011218557 A CN202011218557 A CN 202011218557A CN 112462192 A CN112462192 A CN 112462192A
Authority
CN
China
Prior art keywords
sampling
clock
ram
adc
fpga chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202011218557.4A
Other languages
Chinese (zh)
Inventor
蔡景
李海亮
康婷玮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nanjing University of Aeronautics and Astronautics
Original Assignee
Nanjing University of Aeronautics and Astronautics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanjing University of Aeronautics and Astronautics filed Critical Nanjing University of Aeronautics and Astronautics
Priority to CN202011218557.4A priority Critical patent/CN112462192A/en
Publication of CN112462192A publication Critical patent/CN112462192A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/08—Locating faults in cables, transmission lines, or networks

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

The invention discloses an ADC frequency increasing system and method for aviation cable fault detection based on TDR technology, and the ADC frequency increasing system comprises an FPGA module, an ADC sampling module and a cable to be detected, wherein an FPGA chip, a PLL, an RAM and an active crystal oscillator are configured in the FPGA module, the FPGA module transmits low-voltage detection pulses to the cable to be detected, then the PLL performs phase offset on a reference clock provided by the active crystal oscillator under the action of an offset clock control signal of the FPGA chip, the ADC sampling module performs multi-round sampling on reflection pulse signals in the cable to be detected by taking each offset clock as a sampling clock, and transmits sampling data to the RAM, and finally the RAM sequentially stores each sampling data according to a sampling sequence. According to the aviation cable fault detection ADC frequency increasing system and method based on the TDR technology, the ADC sampling frequency can be greatly increased, and therefore the aviation cable fault detection precision based on the TDR technology is greatly improved.

Description

ADC frequency increasing system and method for aviation cable fault detection based on TDR technology
Technical Field
The invention relates to an ADC sampling frequency increasing technology, in particular to an ADC frequency increasing system and method for aviation cable fault detection based on a TDR technology.
Background
The aviation cable is mainly used for connecting power supply equipment and a control system of the airplane and transmitting signals, the performance of the aviation cable directly influences the operation safety of the airplane, and more attention is paid to airworthiness approval and use and maintenance. In order to ensure the complete performance of the aviation cable, the faults of the aviation cable must be strictly detected and eliminated, but the number of the cables on the airplane is large, the fault concealment is high, and the detection space and the detection points are limited, so that the fault detection difficulty is high.
In the aspect of cable fault detection, a Time Domain Reflectometry-TDR (Time Domain Reflectometry) technology is mature, the technology judges the type and the position of a fault according to the relation between low-voltage emission pulses and reflection pulses, detection can be completed only by connecting one end of a cable, and operation is very convenient. The key problem of the cable fault detection technology based on the TDR technology is to locate the reflected pulse and identify the phase of the reflected pulse, and for the problem, an ADC (analog to digital converter) sampling method is mainly used at present. The ADC sampling frequency determines the fault detection precision to a great extent, and in order to achieve higher ADC sampling frequency, a delay line method and an ADC sampling module with higher precision are mainly used at present, but the problems of increased cost and system complexity exist. How to greatly improve the sampling frequency of the ADC without increasing the complexity and the cost of the system so as to achieve higher fault detection precision is a problem that needs to be solved by the existing cable fault detection technology based on the TDR technology.
Disclosure of Invention
The purpose of the invention is as follows: aiming at the problems that the ADC sampling frequency of aviation cable fault detection based on the TDR technology is limited by the highest sampling rate of a module at present and the detection precision is difficult to improve, the invention provides an Analog-to-Digital Converter (ADC) frequency increasing system and method for aviation cable fault detection based on the TDR technology.
The technical scheme is as follows: an ADC frequency increasing system for aviation cable fault detection based on TDR technology comprises a Field Programmable Gate Array (Field Programmable Gate Array-FPGA) module, an ADC sampling module and a cable to be detected, wherein,
an FPGA chip, a Phase Locked Loop (PLL), a Random Access Memory (RAM) and an active crystal oscillator are configured in the FPGA module; the active crystal oscillator is connected with the FPGA chip and the PLL; the PLL is connected with the FPGA chip; the tested cable module is connected with the FPGA chip and the ADC sampling module; the RAM is connected with the FPGA chip and the ADC sampling module; the active crystal oscillator is used for providing clock signals for the FPGA chip and the PLL; the PLL is used for generating an offset clock; the FPGA chip transmits low-voltage pulses to the tested cable module; the ADC sampling module is used for sampling the reflection pulse in the tested cable module and sending sampling data to the RAM; the RAM is used for storing the sampling data; the FPGA chip provides a clock signal, a write enable signal, a write address signal and a read address signal for the RAM so as to ensure normal read-write operation of the RAM.
An ADC frequency increasing method for aviation cable fault detection based on TDR technology comprises the following steps:
step S101, connecting the same end of a cable to be tested with cable interfaces of an FPGA module and an ADC sampling module;
s102, starting an FPGA module and carrying out reset operation;
step S103, setting ADC sampling frequency (n +1) fclkWherein f isclkFor the reference clock, n is 0,1, … …, and the ADC sampling frequency is set to be generally the frequency f of the reference clock (i.e. the clock signal provided by the active crystal oscillator)clkThe integer multiple of the offset clock control signal is generated by the FPGA chip according to the multiple relation of the offset clock control signal and is sent to the PLL;
step S104, under the action of the offset clock control signal, the PLL offsets the reference clock to obtain an offset clock, the clock of the reference clock after offsetting 1 phase unit is offset clock 1, the clock of the reference clock after offsetting two phase units is offset clock 2, and the clock of the reference clock after offsetting n phase units is offset clock n in the same way, so that one clock period T of the reference clockclkI.e. 1/fclkIs equivalently divided into (n +1) equal parts, one phase unit of which is
Figure BDA0002761259550000021
Step S105, the PLL sends the obtained offset clock signal to the FPGA chip, and the FPGA chip sends the offset clock signal required by each sampling round to the ADC sampling module and the RAM respectively, wherein the ADC sampling module takes the offset clock signal as a sampling clock, and the RAM takes the offset clock signal as an input and output clock;
s106, setting a write enable signal sent to the RAM by the FPGA chip to be 1;
step S107, sampling reflected pulses of the cable to be tested, wherein the frequency of transmitting low-voltage pulse signals into the cable to be tested by the FPGA chip is (n +1), so that (n +1) groups of sampling data are obtained, and (m +1) clock periods T are sampled in each group of samplingclkThe method includes the steps that (m +1) sampling points are set in total, wherein m is 0,1 and … …, while the FPGA chip transmits a low-voltage pulse signal for the first time, an ADC (analog-to-digital converter) sampling module starts sampling the reflected pulse signal by taking a reference clock as a sampling clock and transmits sampling data to an RAM (random access memory), and write addresses transmitted to the RAM by the FPGA chip are 1, n +2, 2(n +1) +1, … … and m (n +1) +1 respectively according to the sampling sequence of the sampling data; while the FPGA chip transmits a low-voltage pulse signal for the second time, the ADC sampling module starts sampling the detection signal by taking an offset clock 1 as a sampling clock and sends sampling data to the RAM, and the writing addresses which the FPGA chip should send to the RAM are respectively 2, n +3, 2(n +1) +2, … …, m (n +1) +2 according to the sampling sequence of each sampling data; and so on, storing the 3 rd to (n +1) th groups of sampling data in the RAM, thus obtaining the sampling data of (m +1) (n +1) sampling points in total, the total sampling period is (m +1), and the sampling period is TclkThen the equivalent sampling period Teq＝(m+1)Tclk/(m+1)(n+1)＝Tclk/(n +1), so the equivalent sampling frequency feqIs (n +1) fclkThereby completing one equivalent sampling;
s108, setting a write enable signal sent to the RAM by the FPGA chip to 0;
and step S109, when the sampling data stored in the RAM is read, the FPGA chip sends a read address signal to the RAM in sequence according to the storage address of each sampling data, and then all the sampling data can be read out.
Has the advantages that: according to the ADC frequency increasing system and method for aviation cable fault detection based on the TDR technology, the ADC sampling frequency can be greatly increased, and the precision of aviation cable fault detection is greatly improved.
Drawings
FIG. 1 is an architecture diagram of an ADC frequency-increasing system for aviation cable fault detection based on TDR technology;
fig. 2 is a timing diagram of an offset clock generated based on a PLL.
Detailed Description
The invention will be further described with reference to the accompanying drawings in which:
fig. 1 is an architecture diagram of an ADC frequency-increasing system for aviation cable fault detection based on the TDR technology provided in the present invention.
The ADC frequency increasing system for aviation cable fault detection based on the TDR technology in the embodiment comprises an FPGA module, an ADC sampling module and a cable to be detected; the FPGA module is internally provided with an FPGA chip, a PLL (phase locked loop), an RAM (random access memory) and an active crystal oscillator; in the FPGA module, the active crystal oscillator is connected with an FPGA chip and a PLL (phase locked loop), the PLL is connected with the FPGA chip, and the RAM is connected with the FPGA chip; the FPGA chip is respectively connected with the ADC sampling module and the tested cable module through an expansion port outside the FPGA module, and the RAM is connected with the ADC sampling module; and the SMA interface conversion crocodile clip of the ADC sampling module is connected with the cable to be tested.
Specifically, the FPGA module belongs to a high-speed digital component, an internal system needs to rely on a stable clock signal for normal work, and the active crystal oscillator is used for providing a clock signal for an FPGA chip and a PLL so as to ensure normal work of the FPGA chip and the PLL; the PLL carries out phase offset on a reference clock provided by the active crystal oscillator under the action of a control signal of the FPGA chip, and sends the obtained offset clock to the FPGA chip, and the FPGA chip sends the offset clock signal to the RAM and the ADC sampling module respectively to ensure normal work of the RAM and the ADC sampling module; the FPGA module transmits low-voltage pulses to the cable to be tested through an internal FPGA chip, so that the low-voltage pulse transmission control system is flexible in controlling the width of the low-voltage transmitted pulses and has good pulse characteristics; the ADC sampling module is used for sampling the reflected pulse in the tested cable module, a memory is not configured in the ADC sampling module, and sampling data need to be sent to an RAM built in the FPGA module; the FPGA chip provides a clock signal, a write enable signal, a write address signal and a read address signal for the RAM so as to control the normal read-write operation of the RAM.
Based on the above ADC frequency increasing system, this embodiment also discloses an ADC frequency increasing method for aviation cable fault detection based on the TDR technology, at first, the FPGA module transmits low-voltage detection pulses to a cable to be detected, then under the action of an offset clock control signal of the FPGA chip, the PLL performs phase offset on a reference clock provided by the active crystal oscillator, the ADC sampling module uses each offset clock as a sampling clock, performs multi-round sampling on a reflection pulse signal in the cable to be detected, and sends sampling data to the RAM, and finally the RAM sequentially stores each sampling data according to a sampling sequence, so that the ADC sampling frequency is greatly increased, thereby the aviation cable fault detection accuracy based on the TDR technology is greatly improved, which specifically includes the following steps:
step S101, connecting the same end of a cable to be detected with cable interfaces of an FPGA module and an ADC (analog to digital converter) sampling module, judging the type and the position of a fault according to the phase and time relation of a reflected pulse signal and a transmitted pulse signal by using a TDR-based cable fault detection technology, and connecting the FPGA module and the ADC sampling module to the same end of the cable to be detected in order to correctly detect the relation of the reflected pulse and the transmitted pulse;
step S102, starting an FPGA module and carrying out reset operation, wherein the reset operation mainly aims at control signals such as a write enable signal and a write address signal;
step S103, setting ADC sampling frequency (n +1) fclkWherein f isclkFor the reference clock, n is 0,1, … …, and the ADC sampling frequency is set to be generally the frequency f of the reference clock (i.e. the clock signal provided by the active crystal oscillator)clkThe integer multiple of the offset clock control signal is generated by the FPGA chip according to the multiple relation of the offset clock control signal and is sent to the PLL;
step S104, under the action of the offset clock control signal, the PLL carries out phase offset on the reference clock to obtain an offset clock, and the ADC sampling frequency (n +1) f set for equivalence is obtainedclkOne of the reference clocks is requiredClock period TclkEqually divided into (n +1) equal parts, each equal part being a phase unit, one phase unit being
Figure BDA0002761259550000051
As shown in fig. 2, an offset clock 1 is a clock shifted by 1 phase unit from a reference clock, an offset clock 2 is a clock shifted by two phase units from the reference clock, and similarly, an offset clock n is a clock shifted by n phase units, so that an offset clock signal is obtained;
step S105, in order to ensure that the sampling of the ADC sampling module on the reflected signal and the RAM storing the sampled data are synchronous, the same clock signal needs to be provided to the ADC sampling module and the RAM. The PLL sends the obtained offset clock signal to the FPGA chip, and the FPGA chip sends the offset clock signal required by each sampling to the ADC sampling module and the RAM respectively, wherein the ADC sampling module takes the offset clock signal as a sampling clock, and the RAM takes the offset clock signal as an input and output clock;
s106, setting a write enable signal sent to the RAM by the FPGA chip to be 1, and storing the received sampling data into a corresponding write address by the RAM when the write enable signal received by the RAM is set to be 1, or else, not storing the received sampling data by the RAM;
step S107, sampling reflected pulses of the cable to be tested, wherein the frequency of transmitting low-voltage pulse signals into the cable to be tested by the FPGA chip is (n +1), so that (n +1) groups of sampling data are obtained, and (m +1) clock periods T are sampled in each group of samplingclkThe method includes the steps that (m +1) sampling points are set in total, wherein m is 0,1 and … …, while the FPGA chip transmits a low-voltage pulse signal for the first time, an ADC (analog-to-digital converter) sampling module starts sampling the reflected pulse signal by taking a reference clock as a sampling clock and transmits sampling data to an RAM (random access memory), and write addresses transmitted to the RAM by the FPGA chip are 1, n +2, 2(n +1) +1, … … and m (n +1) +1 respectively according to the sampling sequence of the sampling data; while the FPGA chip transmits the low-voltage pulse signal for the second time, the ADC sampling module starts to sample the detection signal by taking the offset clock 1 as a sampling clock, and samples the numberAccording to the sampling sequence of each sampling data, the writing addresses which are sent to the RAM by the FPGA chip are respectively 2, n +3, 2(n +1) +2, … …, and m (n +1) + 2; and so on, storing the 3 rd to (n +1) th groups of sampling data in the RAM. Thus, the sampling data of (m +1) (n +1) sampling points are obtained, the total sampling period is (m +1), and the sampling period is TclkThen the equivalent sampling period Teq＝(m+1)Tclk/(m+1)(n+1)＝Tclk/(n +1), so the equivalent sampling frequency feqIs (n +1) fclkThereby completing one equivalent sampling;
s108, after sampling is finished, setting a write enable signal sent to the RAM by the FPGA chip to be 0 to prevent interference data from being written into the RAM;
and step S109, when the sampling data stored in the RAM is read, the FPGA chip sends a read address signal to the RAM in sequence according to the storage address of each sampling data, and then all the sampling data can be read out.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims (2)

1. The utility model provides an aviation cable fault detection's ADC frequency increase system based on TDR technique which characterized in that: comprises an FPGA module, an ADC sampling module and a cable to be tested, wherein,
an FPGA chip, a PLL, an RAM and an active crystal oscillator are configured in the FPGA module; the active crystal oscillator is connected with the FPGA chip and the PLL; the PLL is connected with the FPGA chip; the tested cable module is connected with the FPGA chip and the ADC sampling module; the RAM is connected with the FPGA chip and the ADC sampling module; the active crystal oscillator is used for providing clock signals for the FPGA chip and the PLL; the PLL is used for generating an offset clock; the FPGA chip transmits low-voltage pulses to the tested cable module; the ADC sampling module is used for sampling the reflection pulse in the tested cable module and sending sampling data to the RAM; the FPGA chip provides a clock signal, a write enable signal, a write address signal and a read address signal for the RAM so as to ensure normal read-write operation of the RAM.
2. An ADC frequency increasing method for aviation cable fault detection based on TDR technology is characterized by comprising the following steps:
step S101, connecting the same end of a cable to be tested with cable interfaces of an FPGA module and an ADC sampling module;
s102, starting an FPGA module and carrying out reset operation;
step S103, setting ADC sampling frequency (n +1) fclkWherein f isclkFor the reference clock, n is 0,1, … …, and the ADC sampling frequency is set to be generally the frequency f of the reference clock (i.e. the clock signal provided by the active crystal oscillator)clkThe integer multiple of the offset clock control signal is generated by the FPGA chip according to the multiple relation of the offset clock control signal and is sent to the PLL;
step S104, under the action of the offset clock control signal, the PLL offsets the reference clock to obtain an offset clock, the clock of the reference clock after offsetting 1 phase unit is offset clock 1, the clock of the reference clock after offsetting two phase units is offset clock 2, and the clock of the reference clock after offsetting n phase units is offset clock n in the same way, so that one clock period T of the reference clockclkI.e. 1/fclkIs equivalently divided into (n +1) equal parts, one phase unit of which is
Figure FDA0002761259540000011
Step S105, the PLL sends the obtained offset clock signal to the FPGA chip, and the FPGA chip sends the offset clock signal required by each sampling round to the ADC sampling module and the RAM respectively, wherein the ADC sampling module takes the offset clock signal as a sampling clock, and the RAM takes the offset clock signal as an input and output clock;
s106, setting a write enable signal sent to the RAM by the FPGA chip to be 1;
step S107, sampling the pulse reflected by the cable to be tested, wherein the frequency of transmitting a low-voltage pulse signal into the cable to be tested by the FPGA chip is (n +1),obtaining (n +1) groups of sampling data, and sampling (m +1) clock periods T in each group of samplingclkThe method includes the steps that (m +1) sampling points are set in total, wherein m is 0,1 and … …, while the FPGA chip transmits a low-voltage pulse signal for the first time, an ADC (analog-to-digital converter) sampling module starts sampling the reflected pulse signal by taking a reference clock as a sampling clock and transmits sampling data to an RAM (random access memory), and write addresses transmitted to the RAM by the FPGA chip are 1, n +2, 2(n +1) +1, … … and m (n +1) +1 respectively according to the sampling sequence of the sampling data; while the FPGA chip transmits a low-voltage pulse signal for the second time, the ADC sampling module starts sampling the detection signal by taking an offset clock 1 as a sampling clock and sends sampling data to the RAM, and the writing addresses which the FPGA chip should send to the RAM are respectively 2, n +3, 2(n +1) +2, … …, m (n +1) +2 according to the sampling sequence of each sampling data; and so on, storing the 3 rd to (n +1) th groups of sampling data in the RAM, thus obtaining the sampling data of (m +1) (n +1) sampling points in total, the total sampling period is (m +1), and the sampling period is TclkThen the equivalent sampling period Teq＝(m+1)Tclk/(m+1)(n+1)＝Tclk/(n +1), equivalent sampling frequency feqIs (n +1) fclkThereby completing one equivalent sampling;
s108, setting a write enable signal sent to the RAM by the FPGA chip to 0;
and step S109, when the sampling data stored in the RAM is read, the FPGA chip sends a read address signal to the RAM in sequence according to the storage address of each sampling data, and then all the sampling data can be read out.
CN202011218557.4A 2020-11-04 2020-11-04 ADC frequency increasing system and method for aviation cable fault detection based on TDR technology Pending CN112462192A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011218557.4A CN112462192A (en) 2020-11-04 2020-11-04 ADC frequency increasing system and method for aviation cable fault detection based on TDR technology

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011218557.4A CN112462192A (en) 2020-11-04 2020-11-04 ADC frequency increasing system and method for aviation cable fault detection based on TDR technology

Publications (1)

Publication Number Publication Date
CN112462192A true CN112462192A (en) 2021-03-09

Family

ID=74835115

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011218557.4A Pending CN112462192A (en) 2020-11-04 2020-11-04 ADC frequency increasing system and method for aviation cable fault detection based on TDR technology

Country Status (1)

Country Link
CN (1) CN112462192A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113206665A (en) * 2021-03-15 2021-08-03 新华三技术有限公司 Signal sampling method and device
CN117706255A (en) * 2024-02-03 2024-03-15 深圳市思派乐电子有限公司 Coaxial cable testing method, device and system

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101975625A (en) * 2010-09-27 2011-02-16 苏州光格设备有限公司 Distributed optical fiber temperature sensing system and measurement method thereof
CN102072980A (en) * 2010-11-29 2011-05-25 浙江工业大学 Optical fiber temperature compensator of electronic current transformer
JP2012161025A (en) * 2011-02-02 2012-08-23 Mitsubishi Electric Corp Cable diagnostic device and cable diagnostic method
CN103869291A (en) * 2014-04-02 2014-06-18 清华大学 Ku-band radar signal collecting system
CN104597802A (en) * 2014-11-28 2015-05-06 苏州工业职业技术学院 Super-high sampling rate of reproducible data collection system
CN106707103A (en) * 2016-12-12 2017-05-24 中国人民解放军海军航空工程学院 Hand-held automatic cable fault location device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101975625A (en) * 2010-09-27 2011-02-16 苏州光格设备有限公司 Distributed optical fiber temperature sensing system and measurement method thereof
CN102072980A (en) * 2010-11-29 2011-05-25 浙江工业大学 Optical fiber temperature compensator of electronic current transformer
JP2012161025A (en) * 2011-02-02 2012-08-23 Mitsubishi Electric Corp Cable diagnostic device and cable diagnostic method
CN103869291A (en) * 2014-04-02 2014-06-18 清华大学 Ku-band radar signal collecting system
CN104597802A (en) * 2014-11-28 2015-05-06 苏州工业职业技术学院 Super-high sampling rate of reproducible data collection system
CN106707103A (en) * 2016-12-12 2017-05-24 中国人民解放军海军航空工程学院 Hand-held automatic cable fault location device

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
王宇磊: "基于FPGA的光接收机数据恢复电路的设计与实现", 《中国优秀硕士学位论文全文数据库 信息科技辑》 *
陈客松 等: "《微计算机原理与接口 基于STM32处理器》", 31 July 2017, 电子科技大学出版社 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113206665A (en) * 2021-03-15 2021-08-03 新华三技术有限公司 Signal sampling method and device
CN117706255A (en) * 2024-02-03 2024-03-15 深圳市思派乐电子有限公司 Coaxial cable testing method, device and system
CN117706255B (en) * 2024-02-03 2024-04-12 深圳市思派乐电子有限公司 Coaxial cable testing method, device and system

Similar Documents

Publication Publication Date Title
CN112462192A (en) ADC frequency increasing system and method for aviation cable fault detection based on TDR technology
US7542857B2 (en) Technique for determining performance characteristics of electronic devices and systems
CN108401445A (en) For the circuit of time of measuring, method and related chip, system and equipment
CN106788566B (en) Transceiver with continuously variable chip rate based on Ethernet physical layer and transmission method
CN104407998A (en) High-speed ADC (Analog to Digital Converter) sampled data receiving and buffering method and system based on FPGA (Field Programmable Gate Array)
CN201181323Y (en) Logic analyzer
CN104135332A (en) GPS (Global Positioning System) time synchronization device used for high-power electromagnetic transmitter
CN110471880A (en) A kind of ARINC429 bus module and its data transmission method for supporting No. Label screening based on FPGA
CN113281610A (en) Electric power traveling wave fault location system
CN111090093A (en) PD radar emission waveform configuration method and device based on FPGA
CN105785456B (en) A kind of microcosmic magnetic resonance detection device and method
CN107066419B (en) Scalable adaptive NxN channel data communication system
CN105137295A (en) Cable fault detection device and test method
CN102014216B (en) Method and device for detecting transmission delay of channels of public switched telephone network
CN106992831A (en) A kind of communication system time synchronizer
CN100458715C (en) Device and method for monitoring handshake circuit
CN206710592U (en) Precise synchronization circuit between a kind of radar radio frequency unit
CN216133319U (en) Automatic calibration system for multipath time
CN101975966B (en) Towrope simulator board for geophysical exploration
CN101000590A (en) Method and system for reading data in memory
CN108255053B (en) Computer high accuracy time service device
CN111585742A (en) Multi-channel signal peak value synchronous detection system
CN110688083A (en) DDR 3-based high-speed data stream long-delay frequency storage forwarding method
CN212008913U (en) Forwarding type target simulator based on radio frequency direct mining technology
Zhang et al. Design and realization of remote synchronous data transmission system based on distributed architecture of serial concurrent bus

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20210309