CN112447589A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN112447589A CN112447589A CN202110133353.9A CN202110133353A CN112447589A CN 112447589 A CN112447589 A CN 112447589A CN 202110133353 A CN202110133353 A CN 202110133353A CN 112447589 A CN112447589 A CN 112447589A
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1068—Formation and after-treatment of conductors
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Abstract
The invention provides a semiconductor device and a manufacturing method thereof. In the manufacturing method, after a first conductive structure is formed in a first opening in a first insulating layer, a conductive covering layer is formed on the upper portion, the conductive covering layer is attached to the exposed surface of the first conductive structure and extends to the upper surface of the first insulating layer, then a second insulating layer and a second conductive structure located in the second insulating layer are formed on the conductive covering layer, and a first metal interconnection line in the first conductive structure is electrically connected with a second metal interconnection line in the second conductive structure. The conductive covering layer can fill up a gap between the first metal interconnection line and the first opening, and after the second conductive structure is formed, a cavity is not easy to generate at the top of the first opening, so that the performance of the semiconductor device is improved, and the service life of the semiconductor device is prolonged. The semiconductor device includes the above-described conductive cap layer disposed over a first opening in a semiconductor structure.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof.
Background
With the rapid development of large-scale integrated circuits, the fabrication process of integrated circuits becomes more and more complex and fine, and in order to increase the integration density, after a device structure is formed on a substrate such as a silicon wafer, metal interconnection technology is used to perform metal interconnection in a vertical space, and various elements manufactured on a semiconductor substrate are connected through metal interconnection lines to form a complete circuit system and provide contact points with external circuits of the semiconductor device. In order to suppress wiring delay, copper, which has a lower resistance than aluminum, is generally used as a material of the metal interconnection line. The damascene process is the main process for forming copper metal interconnection lines.
However, there are still some problems with the current metal interconnect line process. Taking the fabrication of a copper interconnect as an example, referring to fig. 1, first, a first insulating layer 10 is fabricated on a substrate on which a semiconductor device is formed, and a first copper interconnect 11 is formed in a trench in the first insulating layer 10; then, a planarization process (e.g., chemical mechanical polishing) is performed to planarize the upper surface of the first copper interconnection 11 and the upper surface of the first insulating layer 10, however, polishing of metal often requires a strong chemical etching to aid the mechanical polishing, and after the polishing is completed, the copper material at the boundary is easily etched and lost, so that a gap is generated between the top of the first copper interconnection 11 and the barrier layer 12 located around the top of the first copper interconnection 11, fig. 2 shows a cross-sectional photograph (SEM photograph) after the first copper interconnection 11 is formed in the first insulating layer 10, and the dotted circle in fig. 1 and 2 indicates the position of the gap; next, referring to fig. 3, a second insulating layer 20 is formed on the first insulating layer 10 in an overlapping manner, and a via hole 21 exposing the first copper interconnection line 11 is formed in the second insulating layer 20; then, referring to fig. 4, the via hole 21 in the second insulating layer 20 is filled with copper to form an upper second copper interconnection line 22, and the second copper interconnection line 22 is electrically connected to the lower first copper interconnection line 11. However, in this structure, since there is a gap between the top of the first copper interconnection 11 and the barrier layer 12 located therearound, a void is generated around the underlying first copper interconnection 11 after the second copper interconnection 22 is formed, fig. 5 shows an SEM photograph after the second copper interconnection 22 is formed, and the dotted circles in fig. 4 and 5 indicate the location of the void.
In addition, in the above manufacturing process, before filling the via hole 21 exposing the first copper interconnection line 11, wet cleaning is usually performed on the via hole 21 to remove impurities in the via hole 21 and an oxide layer on the copper surface, but during the cleaning process, due to the isotropic etching action of the acidic cleaning solution, a recess with an edge extending into the lower portion of the second insulating layer 21 may be formed on the top of the first copper interconnection line 11 in the actual semiconductor structure when filling the via hole 21, as shown in fig. 7. In this case, the cross-section of the semiconductor structure after filling the second copper interconnect 22 in the via 21 is shown in fig. 7. It can be seen that voids are still easily created at the top of the first copper interconnect line 11 (as indicated by the dashed circles in fig. 7).
In the use process of the semiconductor device (or the corresponding chip), the voids shown in fig. 4 and 7 may make the electrical property of the metal interconnection line unstable, and in a severe case, may cause leakage, and shorten the lifetime of the device.
Disclosure of Invention
In order to avoid the influence of cavity defects generated near metal interconnection lines on the performance and the service life of a semiconductor device in the prior art, the invention provides the semiconductor device and a manufacturing method thereof.
In one aspect, the present invention provides a method for manufacturing a semiconductor device, including the steps of:
providing a semiconductor structure, wherein the top layer of the semiconductor structure is a first insulating layer, a first opening is formed in the first insulating layer, a first conductive structure is filled in the first opening, and the first conductive structure comprises a first metal interconnection line;
forming a conductive covering layer on the first opening, wherein the conductive covering layer is attached to the exposed surface of the first conductive structure and extends to the upper surface of the first insulating layer;
forming a second insulating layer on the semiconductor structure, the second insulating layer covering the first insulating layer and the conductive capping layer;
forming a second opening penetrating through the second insulating layer, and controlling the depth of the second opening to expose at least the conductive covering layer; and the number of the first and second groups,
and filling a second conductive structure in the second opening, wherein the second conductive structure comprises a second metal interconnection line, and the second metal interconnection line is electrically connected with the first metal interconnection line.
Optionally, the first conductive structure further includes a first barrier layer formed on an inner wall of the first opening and surrounding the first metal interconnection line from a side surface and a bottom surface; in the step of forming the conductive capping layer on the first opening, the conductive capping layer adheres to exposed surfaces of the first metal interconnection line and the first barrier layer.
Optionally, before the second opening is filled with the second conductive structure, a step of performing wet cleaning on the second opening is further included.
Optionally, the second opening exposes the first metal interconnection line under the conductive cover layer, and the wet cleaning uses an acidic cleaning solution to remove an oxide on the surface of the first metal interconnection line.
Optionally, the depth of the second opening is controlled such that the second opening exposes the upper surface of the conductive cover layer and does not expose the first metal interconnection line.
Optionally, an orthographic projection of the second opening on the plane of the first insulating layer all falls within a range of the first opening.
Optionally, the material of the conductive covering layer comprises TaN, TiN, W2And N.
Optionally, the second insulating layer includes a first sub-insulating film and a second sub-insulating film sequentially stacked on the semiconductor structure, the first sub-insulating film is made of Nitride Doped Silicon Carbide (NDC), and the second sub-insulating film is made of a Low dielectric constant (Low-k) material.
In one aspect, the present invention provides a semiconductor device comprising:
the semiconductor structure comprises a semiconductor structure, wherein the top layer of the semiconductor structure is a first insulating layer, a first opening is formed in the first insulating layer, a first conductive structure is filled in the first opening, and the first conductive structure comprises a first metal interconnection line;
a conductive cap layer on the semiconductor structure, the conductive cap layer attached to an exposed surface of the first conductive structure and extending to an upper surface of the first insulating layer;
a second insulating layer covering the first insulating layer and the conductive cover layer, the second insulating layer having a second opening formed therein, the second opening exposing an upper surface of the conductive cover layer without exposing the first metal interconnection line; and the number of the first and second groups,
and the second conductive structure is filled in the second opening and comprises a second metal interconnection line which is electrically connected with the first metal interconnection line.
In one aspect, the present invention provides a semiconductor device comprising:
the semiconductor structure comprises a semiconductor structure, wherein the top layer of the semiconductor structure is a first insulating layer, a first opening is formed in the first insulating layer, a first conductive structure is filled in the first opening, and the first conductive structure comprises a first metal interconnection line;
a conductive cap layer on the semiconductor structure, the conductive cap layer attached to an exposed surface of the first conductive structure and extending to an upper surface of the first insulating layer;
a second insulating layer covering the conductive cover layer and the first insulating layer;
a second opening penetrating the conductive cover layer and the second insulating layer and exposing the first metal interconnection line; and the number of the first and second groups,
and the second conductive structure is filled in the second opening and comprises a second metal interconnection line which is electrically connected with the first metal interconnection line.
The invention provides a method for manufacturing a semiconductor device, which comprises the steps of forming a first conductive structure in a first opening in a first insulating layer, forming a conductive covering layer on the first insulating layer, attaching the conductive covering layer to the exposed surface of the first conductive structure and extending to the upper surface of the first insulating layer, forming a second insulating layer and a second conductive structure in the second insulating layer above the conductive covering layer, and electrically connecting a first metal interconnection line in the first conductive structure with a second metal interconnection line in the second conductive structure. The conductive covering layer can fill up gaps (or depressions) which are easily formed between the first metal interconnection lines and the first openings, and after the second conductive structure is formed, the top of the first opening is not easy to generate holes (namely, the risk of generating the holes near the metal interconnection lines is reduced), so that the performance of the semiconductor device is improved, and the service life of the semiconductor device is prolonged.
In addition, in the manufacturing method, the depth of the second opening is controlled to expose the conductive covering layer without exposing the first metal interconnection line, so that the first metal interconnection line is not easily damaged even if wet cleaning is performed before the second conductive structure is formed in the second opening, the risk that the manufactured semiconductor device generates a cavity near the metal interconnection line can be reduced, and the performance of the semiconductor device is improved and the service life of the semiconductor device is prolonged.
The semiconductor device provided by the invention comprises the conductive covering layer arranged on the first opening in the semiconductor structure, and the conductive covering layer can play a role in filling gaps (or depressions) which are easy to appear between the first metal interconnection line and the first opening, so that the performance of the semiconductor device is improved, and the service life of the semiconductor device is prolonged.
Drawings
Fig. 1 is a cross-sectional view illustrating a first copper interconnection formed in a first insulating layer according to a conventional method.
Fig. 2 is a cross-sectional photograph of a prior art method of forming a first copper interconnect line in a first insulating layer.
Fig. 3 is a schematic cross-sectional view of the first copper interconnect shown in fig. 1 after a via is formed therein.
Fig. 4 is a cross-sectional view of the second copper interconnect line formed in the via shown in fig. 3.
Fig. 5 is a photograph of a prior art method of forming a second copper interconnect line in a via over a first copper interconnect line.
Fig. 6 is a schematic cross-sectional view of the trench shown in fig. 3 after wet cleaning.
Fig. 7 is a cross-sectional view of the trench shown in fig. 6 after forming a second copper interconnect.
Fig. 8 is a flowchart illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Fig. 9 to 13 are schematic cross-sectional views of a semiconductor device according to an embodiment of the present invention during a manufacturing process.
Fig. 14 to 16 are schematic cross-sectional views of a semiconductor device according to another embodiment of the present invention during a manufacturing process.
Description of reference numerals:
(fig. 1 to 7) 10-a first insulating layer; 11-a first copper interconnect line; 12-a barrier layer; 20-a second insulating layer; 21-a through hole; 22-a second copper interconnect line;
(fig. 9-16) 100-a semiconductor structure; 110-a first insulating layer; 110 a-a first opening; 111-a first metal interconnect line; 112-a first barrier layer; 120-a conductive cover layer; 130-a second insulating layer; 131-a first sub-insulating film; 132 — second sub insulating film; 130 a-a second opening; 133-a second metal interconnect line; 134-second barrier layer.
Detailed Description
The semiconductor device and the method for fabricating the same according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, but merely as a convenient and clear aid in describing embodiments of the invention, which should not be construed as limited to the specific shapes of regions illustrated in the drawings. For the sake of clarity, in all the drawings for assisting the description of the embodiments of the present invention, the same components are denoted by the same reference numerals in principle, and the duplicated description thereof is omitted. The terms "first," "second," and the like in the following description are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances. For the sake of clarity, in all the drawings for assisting the description of the embodiments of the present invention, the same components are denoted by the same reference numerals in principle, and the duplicated description thereof is omitted.
As described in the background art, in the process of manufacturing a metal interconnection line at a later stage of semiconductor device manufacturing, a void defect is easily present in an opening region of a filled metal interconnection line, and the void defect affects electrical stability and even shortens the lifetime of the device. The present invention is proposed to avoid the influence of the void defect. The following first describes a method for manufacturing a semiconductor device of the present invention by way of example. The semiconductor device provided by the invention can be manufactured by the manufacturing method.
Fig. 8 is a flowchart illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. Referring to fig. 8, a method for manufacturing a semiconductor device according to an embodiment of the present invention includes the steps of:
s1: providing a semiconductor structure, wherein the top layer of the semiconductor structure is a first insulating layer, a first opening is formed in the first insulating layer, a first conductive structure is filled in the first opening, and the first conductive structure comprises a first metal interconnection line;
s2: forming a conductive covering layer on the first opening, wherein the conductive covering layer is attached to the exposed surface of the first conductive structure and extends to the upper surface of the first insulating layer;
s3: forming a second insulating layer on the semiconductor structure, the second insulating layer covering the first insulating layer and the conductive capping layer;
s4: forming a second opening penetrating through the second insulating layer, and controlling the depth of the second opening to expose at least the conductive covering layer;
s5: and filling a second conductive structure in the second opening, wherein the second conductive structure comprises a second metal interconnection line, and the second metal interconnection line is electrically connected with the first metal interconnection line.
Fig. 9 to 13 are schematic cross-sectional views of a semiconductor device according to an embodiment of the present invention during a manufacturing process. A method for manufacturing a semiconductor device according to an embodiment of the present invention is further described with reference to fig. 8 to 13.
Fig. 9 is a schematic cross-sectional view of a semiconductor structure obtained in a method of manufacturing a semiconductor device according to an embodiment of the present invention. Referring to fig. 8 and 9, step S1 is performed first, and a semiconductor structure 100 is provided, where the semiconductor structure 100 includes a first insulating layer 110, a first opening 110a is formed in the first insulating layer 110, and a first conductive structure is filled in the first opening 110a and includes a first metal interconnection 111.
In a manufacturing process of a semiconductor device, a process of forming a semiconductor device having a complete electrical function is generally divided into a front end of line (FEOL) process and a back end of line (BEOL) process according to a processing sequence, wherein the front end process is a process of forming a device structure on a semiconductor substrate, the process has high requirements on equipment and cleanliness, manufacturing processes such as a gate and a source/drain are completed in the front end process, the back end process is metal interconnection, and an interconnection function is realized by stacking an insulating layer and a metal layer on a structure in which the front end process is completed.
The manufacturing process of the semiconductor device of the embodiment mainly involves a back-end process. The semiconductor structure 100 provided in step S1 may be a structure that has completed the front-end-of-line process, and the semiconductor structure may include a semiconductor substrate and a semiconductor element, such as a memory cell and/or a logic circuit (e.g., MOSFET), formed by using the semiconductor substrate. The material of the semiconductor substrate may be silicon, germanium, silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, indium antimonide, or the like, or may be silicon-on-insulator (SOI) or germanium-on-insulator (GOI), or may be another material such as GaAs, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInAsP, or the like, or may be a combination of the above materials.
A first insulating layer 110 is formed on the semiconductor structure 100, and a first conductive structure is formed in the first insulating layer 110. The material of the first insulating layer 110 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride, such as silicon oxide doped with boron and/or phosphorus. Other insulating materials, such as Low dielectric constant (Low-k) materials with a dielectric constant lower than that of silicon oxide, can also be used for the first insulating layer 110.
The cross section of the first opening 110a in the first insulating layer 110 may be a hole (e.g., a TSV) or a trench, and in this embodiment, the first opening 110a is, for example, a trench extending in the plane of the first insulating layer 110, and metal interconnection is performed by forming a first conductive structure in the first opening 110 a. The first conductive structure may be electrically connected to an electrical contact region of a semiconductor element to be formed on the semiconductor structure 100. The first metal interconnection line 111 may be connected to other conductive elements, such as a metal interconnection line under the first insulating layer 110.
In this embodiment, the first conductive structure includes a first metal interconnection line 111. The top surface of the first metal interconnection line 111 is exposed for subsequent connection with an overlying metal interconnection line. The material of the first metal interconnection line 111 may include at least one of metal materials such as Cu (copper), W (tungsten), Co (cobalt), Ru (ruthenium), Mn (manganese), Ti (titanium), and Ta (tantalum). In the present embodiment, the first metal interconnection line 111 is, for example, a copper metal line, and the copper metal line may be formed in the first opening 110a by electroplating or chemical plating.
Optionally, before forming the first metal interconnection 111 in the first opening 110a, a conductive first barrier layer 112 may be deposited on the inner wall (including the sidewall and the bottom surface) of the first opening 110a, and the first barrier layer 112 may be formed of a conductive material such as Ta, Co, TaN, Ti, TiN, or a combination thereof. The first conductive structure includes a first barrier layer 112 surrounding the first metal interconnection line 111 from a side surface and a bottom surface, in addition to the first metal interconnection line 111 described above. The first barrier layer 112 helps to block diffusion of the material of the first metal interconnection line 111 into the first insulating layer 110, and helps to enhance adhesion of the first metal interconnection line 111 within the first opening 110 a.
In order to planarize the upper surface of the semiconductor structure 100, a planarization process (e.g., chemical mechanical polishing, CMP) is usually used to process the upper surface, and after the planarization process, material loss is likely to occur at the boundary between the first metal interconnection 111, the first barrier layer 112 and the first insulating layer 110 in the polished surface, so as to form a gap (or recess). In the case where the first barrier layer 112 having good adhesion is disposed on the inner surface of the first opening 110a, the gap is more easily generated at the interface between the first barrier layer 112 and the first metal interconnection 111 (see fig. 2). In some manufacturing processes, if the first barrier layer 112 is not disposed or the adhesion of the first barrier layer 112 is poor, a gap in a concave shape may be formed between the first opening 110a and the first metal interconnection line 111. As shown in fig. 4 and 5, if the second opening is directly formed on the first metal interconnection line 111 and the second metal interconnection line is filled, a void is easily formed at the gap at the top of the first metal interconnection line 111.
Fig. 10 is a schematic cross-sectional view illustrating a conductive cap layer formed on a semiconductor structure in a method for manufacturing a semiconductor device according to an embodiment of the present invention. Referring to fig. 8 and 10, next, step S2 is performed to form a conductive cover layer 120 on the first opening 110a, wherein the conductive cover layer 120 is attached to the exposed surface of the first conductive structure and extends to the upper surface of the first insulating layer 110.
In the present embodiment, one purpose of the conductive covering layer 120 is to fill the gap between the first metal interconnection 111 and the first opening 110a (especially, between the first metal interconnection 111 and the first barrier layer 112) to avoid the void defect generated in the first metal interconnection 111 region. Therefore, the conductive cover layer 120 is disposed corresponding to the range of the first opening 110a and attached to the exposed surface of the first conductive structure, that is, the conductive cover layer 120 covers not only the top surfaces of the first metal interconnection line 111 and the first barrier layer 112 (if any), but also the exposed side surfaces thereof, that is, attached to the exposed surface within the range of the first opening 110a, so that the material of the conductive cover layer 120 can fill the gap or recess on the surface of the first conductive structure after the planarization process, thereby reducing the risk of forming a void subsequently.
In order to avoid the problem of insufficient coverage caused by a large gap generated at the top of the first opening 110a or a large gap generated by damage of the material of the first insulating layer 110, the embodiment forms the range of the conductive cover layer 120 to extend outwards from the range of the first opening 110a to exceed the range of the first opening 110a by a certain amount. For example, the cross-sectional shape of the conductive cover layer 120 may be a similar shape (where the similar shape refers to that the two patterns are similar patterns) which is 1% to 20% larger than the cross-sectional shape of the top of the first opening 110a, but not limited thereto, the distance that the conductive cover layer 120 extends from the first opening 110a to the upper surface of the first insulating layer 110 may be set according to the actual situation of the semiconductor structure 100, for example, if other conductive structures (such as other metal interconnection lines) are further disposed on the surface of the first insulating layer 110, the conductive cover layer 120 should be prevented from being electrically connected with other conductive structures except the first conductive structure, that is, the range of the conductive cover layer 120 does not need to be set too large, and in an embodiment, the shortest distance between the outer edge of the conductive cover layer 120 and the boundary of the first opening 110a is greater than 0 and. In this embodiment, a first barrier layer 112 surrounding the first metal interconnection line 111 from the side and the bottom is further formed in the first opening 110a, and the conductive covering layer 120 is also formed by attaching to the exposed surface of the first barrier layer 112, so as to reduce the risk of generating voids on the exposed surface of the first barrier layer 112. The conductive cap layer 120 and the first barrier layer 112 may comprise the same material to improve the adhesion effect of the two.
The conductive cap layer 120 may be formed by Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), etc., or a combination thereof, and may be formed into a suitable shape by photolithography and etching. The conductive coating 120 can be applied with a filler having better adhesionThe porous and conductive material may include TaN, TiN, W2And N. The thickness of the conductive covering layer 120 is, for example, 50A-200A. After the conductive cap layer 120 is formed on the semiconductor structure 100, the upper surface of the conductive cap layer 120 is preferably higher than the upper surface of the first insulating layer 110, so as to avoid the formation of voids at the boundary of the first opening 110a after the upper conductive material is filled.
Fig. 11 is a schematic cross-sectional view illustrating a second insulating layer formed on a semiconductor structure in a method of manufacturing a semiconductor device according to an embodiment of the present invention. Referring to fig. 8 and 11, next, step S3 is performed to form a second insulating layer 130 on the semiconductor structure 100, wherein the second insulating layer 130 covers the conductive cover layer 120 and the exposed surface of the first insulating layer 110.
The second insulating layer 130 is used for disposing a second conductive structure electrically connected to the first conductive structure in a vertical direction of the semiconductor structure 100. The second insulating layer 130 may be made of a material similar to that of the first insulating layer 110. In this embodiment, in order to prevent the diffusion of the material (e.g., copper) of the first metal interconnection 111, the second insulating layer 130 has a double-layer structure, for example, and the double-layer structure includes a first sub-insulating film 131 having a better metal diffusion barrier capability, and the first sub-insulating film 131 may be formed of Silicon Carbide (NDC), or SiCN. In addition, the double-layer structure further includes a second sub-insulating film 132 disposed on the first sub-insulating film 131, and the second sub-insulating film 132 is made of a Low dielectric constant (Low-k) material to reduce a wiring delay (or RC delay). By "low dielectric constant" is meant a dielectric constant that is lower than silicon oxide (which is used in conventional devices to have a dielectric constant of about 4). The material of the second sub-insulating film 132 may include at least one of benzocyclobutene (BCB), silicon oxide containing a Methyl group, silicon oxyfluoride (SiOF), hsq (hydrogen Silsesquioxane), msq (Methyl Silsesquioxane), HMSQ (Hydride-Methyl Silsesquioxane), polyimide-based polymer, propyne ether-based polymer, cyclobutene-based polymer, and perfluorocarbon cyclobutene (PFCB). The thickness of the first sub-insulating film 131 may be set smaller than the thickness of the second sub-insulating film 132. The total thickness of the second insulating layer 130 may be determined according to the length of the metal interconnection line to be disposed. The first sub-insulating film 131 and the second sub-insulating film 132 may be formed by using a Physical Vapor Deposition (PVD), a Chemical Vapor Deposition (CVD), an Atomic Layer Deposition (ALD), or the like, or a combination thereof.
Fig. 12 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention after forming a second opening. Referring to fig. 8 and 12, step S4 is then performed to form a second opening 130a penetrating through the second insulating layer 130, and to control the depth of the second opening 130a so as to expose at least the conductive capping layer 120.
The second opening 130a formed in the second insulating layer 130 may be formed by photolithography and dry etching processes. The first opening 110a may be a hole or a groove in cross section. The second opening 130a of the present embodiment is, for example, a tsv (through Silicon via) hole. The cross section of the TSV hole can be circular, oval, polygonal and the like. At least a portion of the second opening 130a is located directly above the first opening 110a to facilitate short-distance interconnection, and an orthographic projection of the second opening 130a on the plane of the first insulating layer 110 at least covers a partial range of the first opening 110a, i.e. the width of the second opening 130a at least in one direction is smaller than that of the first opening 110 a. In this embodiment, the orthographic projection of the second opening 130a on the plane of the first insulating layer 110 is entirely within the range of the first opening 110a, i.e. the TSV is inserted in the first conductive structure, in this case, if the conductive covering layer 120 is not formed, more void defects are easily formed around the first metal interconnection line 111 after the second insulating layer covers the first conductive structure with a gap (or recess) on the top.
Referring to fig. 12, in the present embodiment, after forming the second opening 130a, the bottom surface of the second opening 130a only exposes the upper surface of the conductive cover layer 120. This prevents the material (e.g., copper) of the first metal interconnection line 111 from being oxidized before filling the second opening 130 a. The conductive cover layer 120 corresponding to the second opening 130a may be thinned by a certain thickness before forming the second opening 130 a.
Fig. 13 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention after a second conductive structure is formed. Referring to fig. 8 and 13, step S5 is then performed to fill a second conductive structure in the second opening 130a, where the second conductive structure includes a second metal interconnection line 133, and the second metal interconnection line 133 is electrically connected to the first metal interconnection line 111.
In order to avoid the influence of the impurities in the second opening 130a on the performance of the semiconductor device, the semiconductor structure with the second opening 130a formed therein may be cleaned before the second conductive structure is filled, since the first metal interconnection line 111 is covered by the conductive cover layer 120, the oxide layer does not need to be removed, and the cleaning solution may be a liquid without corrosion capability, such as deionized water only, and then dried.
The second conductive structure may include a second barrier layer 134 formed on an inner wall of the second opening 130a and a second metal interconnection line 133 surrounded from the side and the bottom by the second barrier layer 134. Referring to fig. 13, filling the second conductive structure in the second opening 130a may include the following processes: first, a second barrier layer 134 is formed along the inner wall (including the sidewall and the bottom surface) of the second opening 130a, and then a metal material is deposited on the surface of the second barrier layer 134 until the second opening 130a is filled, thereby obtaining a second metal interconnection line 133. The second barrier layer 134 may be formed of Ta, Co, TaN, Ti, TiN, or a combination thereof. The second metal interconnection line 133 may include at least one of Cu (copper), W (tungsten), Co (cobalt), Ru (ruthenium), Mn (manganese), Ti (titanium), and Ta (tantalum). The second barrier layer 134 helps prevent diffusion of the material of the second metal interconnection line 133 and helps improve adhesion of the second metal interconnection line 133 in the second opening 130 a. The second barrier layer 134 and the second metal interconnection line 133 may be formed using a Physical Vapor Deposition (PVD), a Chemical Vapor Deposition (CVD), an Atomic Layer Deposition (ALD), or the like, or a combination thereof. In this embodiment, the second metal interconnection line 133 is made of copper, and after the second barrier layer 134 is formed, a copper seed layer may be deposited in the second opening 130a, and then copper is deposited by using an electroplating or chemical plating process, so that the copper pillar in the second opening 130a is used as the second metal interconnection line 133. After the deposition of the second metal interconnection line 133 is completed, a planarization process may be employed to planarize the upper surfaces of the second metal interconnection line 133 and the second insulating layer 130. A metal interconnection line may be formed on the second opening 130a as required, and a conductive covering layer may be formed on the second opening 130a to fill up a gap between the top of the second metal interconnection line 133 and the second opening 130a, so as to reduce a risk of generating a void around the metal interconnection line.
In this embodiment, since the conductive capping layer 120 has conductivity, the second metal interconnection line 133 does not need to be directly contacted with the first metal interconnection line 111, but is electrically connected to the first metal interconnection line 111 through the second barrier layer 134 and the conductive capping layer 120.
The following describes the process of the manufacturing method of another embodiment of the present invention after forming the second opening.
Fig. 14 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention after forming a second opening. Referring to fig. 14, in another embodiment of the present invention, after forming the second opening 130a in the second insulating layer 130, the second opening 130a exposes the first metal interconnection line 111 under the conductive cap layer 120. The material of the first metal interconnection 111 may be oxidized before filling the second opening 130a, for example, copper oxide and cuprous oxide may be generated when copper is placed on the surface in air. Therefore, before the second opening 130a is filled with the second conductive structure, an acidic cleaning solution is preferably used to clean the second conductive structure so as to remove the oxide on the surface of the first metal interconnection line 111.
Fig. 15 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention after cleaning the second opening. Referring to fig. 15, in the cleaning process using the acidic cleaning solution, the concentration of the cleaning solution and the cleaning time may be controlled so that the oxide on the surface of the first metal interconnection line 111 is removed and the simple substance of the first metal interconnection line 111 is prevented from being removed as much as possible. In addition, in this embodiment, the conductive cover layer 120 is attached to the first conductive structure before the second insulating layer 130 is formed, so that after the second opening 130a is formed, the unexposed portion of the first metal interconnection line 111 is covered by the conductive cover layer 120, which can prevent the acidic cleaning solution from penetrating into the side surface of the first metal interconnection line 111 from the boundary, and slow down the etching action on the side surface of the first metal interconnection line 111, thereby helping to reduce the risk of forming a void at the boundary of the first opening 110a during the cleaning process.
Fig. 16 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention after a second conductive structure is formed. Referring to fig. 16 in addition to fig. 15, after the acidic cleaning solution is used for cleaning, a second conductive structure is formed in the second opening 130a, the second conductive structure includes a second metal interconnection line 133, and the second metal interconnection line 133 is electrically connected to the first metal interconnection line 111. The second barrier layer 134 may be formed on the side and bottom surfaces of the second metal interconnection 111 first, i.e., the second conductive structure may include the second barrier layer 134 formed on the inner surface of the second opening 130a and the second metal interconnection 133 surrounded by the second barrier layer 134 from the side and bottom surfaces. In this embodiment, after forming the second metal interconnection line 133, the second metal interconnection line 133 is electrically connected to the first metal interconnection line 111 through the second barrier layer 134.
In the method for manufacturing a semiconductor device described in the above embodiment, after forming the first conductive structure in the first opening 110a, the conductive covering layer 120 is formed on the semiconductor structure 100, and the conductive covering layer 120 is attached to the exposed surface of the first conductive structure and extends to the upper surface of the first insulating layer 110, that is, beyond the range of the first opening 110 a. Then, a second insulating layer 130 and a second conductive structure in the second insulating layer 130 are formed thereon. The conductive coating layer 120 may fill up a gap that is easily formed between the first metal interconnection line 111 and the first opening 110a, so that a cavity is not easily generated at the top of the first opening 110a, thereby facilitating to improve the performance of the manufactured semiconductor device and to prolong the lifetime of the semiconductor device. In addition, in the above manufacturing method, the depth of the second opening 130a is controlled to expose at least the conductive covering layer 120; under the condition that the first metal interconnection line 111 is not exposed, even if wet cleaning is carried out before the second metal interconnection line 133 is formed in the second opening 130a, the first metal interconnection line 111 is not easily damaged, the first metal interconnection line 111 can be prevented from being corroded by the wet cleaning solution, and a subsequent semiconductor device can be prevented from generating a cavity on the top of the second opening 130 a; under the condition that the first metal interconnection line 111 is exposed from the second opening 130a, due to the filling effect of the conductive covering layer 120, compared with the prior art, the damage to the first metal interconnection line 111 is smaller, the risk of generating a cavity at the top of the second opening 130a caused by a wet cleaning solution can be reduced, and the performance of the manufactured semiconductor device can be improved and the service life of the semiconductor device can be prolonged.
One embodiment of the present invention relates to a semiconductor device. The semiconductor device may be formed by the method for manufacturing the semiconductor device shown in fig. 8 to 13, or may be formed by another method. Referring to fig. 9 to 13, the semiconductor device includes a semiconductor structure 100, and a conductive capping layer 120, a second insulating layer 130, and a second conductive structure disposed in the second insulating layer 130 on the semiconductor structure 100; the top layer of the semiconductor structure 100 is a first insulating layer 110, a first opening 110a is formed in the first insulating layer 110, a first conductive structure is filled in the first opening 110a, and the first conductive structure includes a first metal interconnection line 111; the conductive cover layer 120 is attached to the exposed surface of the first conductive structure and extends to the upper surface of the first insulating layer 110; the second insulating layer 130 covers the first insulating layer 110 and the conductive cover layer 120, a second opening 130a is formed in the second insulating layer 130, and the second opening 130a exposes the upper surface of the conductive cover layer 120 without exposing the first metal interconnection line 111; a second conductive structure is disposed in the second opening 130a, the second conductive structure including a second metal interconnection line 133, the second metal interconnection line 133 being electrically connected to the first metal interconnection line 111 through a second barrier layer 134 and a conductive capping layer 120. As for each component in the semiconductor device, the explanation in the manufacturing method of the semiconductor device shown in fig. 9 to 13 can be referred to.
In yet another embodiment, the present invention is also directed to a semiconductor device. The semiconductor device can be formed by the method for manufacturing the semiconductor device shown in fig. 8 to 11 and 14 to 16, but can be formed by other methods. Referring to fig. 8 to 11, and 14 to 16, the semiconductor device includes:
a semiconductor structure 100, a top layer of the semiconductor structure 100 being a first insulating layer 110, a first opening 110a being formed in the first insulating layer 110, a first conductive structure being filled in the first opening 110a, the first conductive structure including a first metal interconnection line 111;
a conductive cap layer 120 on the semiconductor structure 100, the conductive cap layer 120 attached to an exposed surface of the first conductive structure and extending to an upper surface of the first insulating layer;
a second insulating layer 130 covering the conductive capping layer 120 and the first insulating layer 110;
a second opening 130a, wherein the second opening 130a penetrates through the conductive cover layer 120 and the second insulating layer 130, and exposes the first metal interconnection line 111; and the number of the first and second groups,
and a second conductive structure filled in the second opening 130a, the second conductive structure including a second metal interconnection line 133, the second metal interconnection line 133 being electrically connected to the first metal interconnection line 111.
The main difference between the semiconductor device in this embodiment (see fig. 16) and the semiconductor device in the previous embodiment (see fig. 13) is that when the second opening 130a is formed, only the upper surface of the conductive cover layer 120 is exposed, and the second conductive structure needs to be electrically connected to the first conductive structure through the conductive cover layer 120. The second opening 130a in the semiconductor device of the latter embodiment is deeper than the second opening 130a in the former embodiment, thereby also exposing the first metal interconnection line 111 under the conductive cap layer 120, and the second conductive structure can be directly electrically connected with the first conductive structure. Although the exposed first metal interconnection line 111 is oxidized, due to the good adhesion protection of the conductive cover layer 120, when the second opening 130a is cleaned by using the isotropic cleaning solution with certain etching property, the risk that the first metal interconnection line 111 is over-etched to form a cavity on the side surface thereof can be reduced.
The semiconductor device described in the embodiments of the present invention includes the conductive coating 120 disposed on the first opening 110a, and the conductive coating 120 may fill a gap (or a recess) at the top of the first opening 110a, thereby improving the performance of the semiconductor device and prolonging the lifetime of the semiconductor device.
It should be noted that the embodiments in this specification are described in a progressive manner, each part is mainly described as a difference from the previous part, and the same and similar parts can be understood by referring to each other.
The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art can make possible the variations and modifications of the technical solutions of the present invention using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention belong to the protection scope of the technical solutions of the present invention.
Claims (10)
1. A method for manufacturing a semiconductor device, comprising:
providing a semiconductor structure, wherein the top layer of the semiconductor structure is a first insulating layer, a first opening is formed in the first insulating layer, a first conductive structure is filled in the first opening, and the first conductive structure comprises a first metal interconnection line;
forming a conductive covering layer on the first opening, wherein the conductive covering layer is attached to the exposed surface of the first conductive structure and extends to the upper surface of the first insulating layer;
forming a second insulating layer on the semiconductor structure, the second insulating layer covering the first insulating layer and the conductive capping layer;
forming a second opening penetrating through the second insulating layer, and controlling the depth of the second opening to expose at least the conductive covering layer; and the number of the first and second groups,
and filling a second conductive structure in the second opening, wherein the second conductive structure comprises a second metal interconnection line, and the second metal interconnection line is electrically connected with the first metal interconnection line.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the first conductive structure further comprises a first barrier layer formed on an inner wall of the first opening and surrounding the first metal interconnection line from a side surface and a bottom surface; in the step of forming the conductive capping layer on the first opening, the conductive capping layer adheres to exposed surfaces of the first metal interconnection line and the first barrier layer.
3. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of performing wet cleaning on the second opening before the second conductive structure is filled in the second opening.
4. The method of claim 3, wherein the second opening exposes the first metal interconnection line under the conductive cap layer, and wherein the wet cleaning uses an acidic cleaning solution to remove an oxide on the surface of the first metal interconnection line.
5. The method of manufacturing a semiconductor device according to claim 1, wherein a depth of the second opening is controlled such that the second opening exposes an upper surface of the conductive cap layer without exposing the first metal interconnection line.
6. The method for manufacturing a semiconductor device according to claim 1, wherein an orthographic projection of the second opening on the plane of the first insulating layer entirely falls within a range of the first opening.
7. A method for fabricating a semiconductor device according to any of claims 1 to 6, wherein the material of the conductive cap layer comprises TaN, TiN, W2And N.
8. The method for manufacturing a semiconductor device according to any one of claims 1 to 6, wherein the second insulating layer includes a first sub-insulating film and a second sub-insulating film which are formed on the semiconductor structure in this order, the material of the first sub-insulating film is nitride-doped silicon carbide, and the material of the second sub-insulating film is a low dielectric constant material.
9. A semiconductor device, comprising:
the semiconductor structure comprises a semiconductor structure, wherein the top layer of the semiconductor structure is a first insulating layer, a first opening is formed in the first insulating layer, a first conductive structure is filled in the first opening, and the first conductive structure comprises a first metal interconnection line;
a conductive cap layer on the semiconductor structure, the conductive cap layer attached to an exposed surface of the first conductive structure and extending to an upper surface of the first insulating layer;
a second insulating layer covering the first insulating layer and the conductive cover layer, the second insulating layer having a second opening formed therein, the second opening exposing an upper surface of the conductive cover layer without exposing the first metal interconnection line; and the number of the first and second groups,
and the second conductive structure is filled in the second opening and comprises a second metal interconnection line which is electrically connected with the first metal interconnection line.
10. A semiconductor device, comprising:
the semiconductor structure comprises a semiconductor structure, wherein the top layer of the semiconductor structure is a first insulating layer, a first opening is formed in the first insulating layer, a first conductive structure is filled in the first opening, and the first conductive structure comprises a first metal interconnection line;
a conductive cap layer on the semiconductor structure, the conductive cap layer attached to an exposed surface of the first conductive structure and extending to an upper surface of the first insulating layer;
a second insulating layer covering the conductive cover layer and the first insulating layer;
a second opening penetrating the conductive cover layer and the second insulating layer and exposing the first metal interconnection line; and the number of the first and second groups,
and the second conductive structure is filled in the second opening and comprises a second metal interconnection line which is electrically connected with the first metal interconnection line.
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