CN112445695A - Tool for quickly generating test description file and application thereof - Google Patents
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Abstract
The invention relates to a tool for quickly generating a test instruction file, which comprises a test algorithm module, a design parameter module, a template file module and a test instruction file generation module; the test algorithm module can import a test algorithm file and provide a test algorithm for selecting a template file; the design parameter module can import a design parameter file; the design parameter file comprises a plurality of rows of design parameters, and each row of design parameters comprises information of the device to be tested and parameters of the device to be tested in the test chip; the tool for formulating the test configuration file can check the information of the test configuration items and prompt problems when the problems are detected.
Description
Technical Field
The present invention relates to the field of integrated circuit wafer testing, and more particularly, to a tool for rapidly generating a test instruction file and an application thereof.
Background
The integrated circuit manufacturing process is complicated and lengthy, and it usually needs tens or even hundreds of processes from a semiconductor single chip to a wafer finished product, and any process step deviation or environmental change in the whole manufacturing process will affect the final product performance and finished product of the integrated circuit chip. Therefore, the electrical test is an important component of chip manufacturing throughout the whole integrated circuit production process, and the yield, reliability and production process of the product are controlled by extracting and analyzing the effective information of the test data, which is an irreplaceable and very effective means.
During design and manufacturing, Wafer Acceptance Testing (WAT) is important in wafer-level chip testing. After wafer manufacturing is completed, a computer is usually used to control a tester, the tester is connected to a test object through a probe card placed in a probe station, probes on the probe card are contacted with bonding pads connected with a device to be tested to form a test path, and then the test object is matched with the tester to achieve the test purpose, so as to obtain test data of the device to perform failure analysis.
In preparation for the WAT test, a test plan (TestPlan) needs to be defined first according to the purpose of the test. At present, a Wafer-level Spec is generally formulated first, then information of PadNumber, Module Name, Device Name, Group, Algorithm, Input, Output and the like of a test is manually determined item by item according to a design structure to generate a TestSpec, and then a test plan is generated by compiling an obtained Spec file. Obviously, in the creation of a test plan, the work of making TestSpec is tedious and time-consuming, and once the input conditions are changed or test plans of different formats need to be generated to adapt to different testers, the rework needs to be reversed, so that the work efficiency is low.
Disclosure of Invention
The invention mainly aims to overcome the defects in the prior art and provide a TestSpec generation tool capable of effectively reducing the time for formulating the TestSpec and application thereof. In order to solve the technical problem, the solution of the invention is as follows:
the tool for rapidly generating the test Spec comprises a test algorithm module, a design parameter module, a template file module and a test specification file generation module;
the test algorithm module can import a test algorithm file (AlgoFile) and provide a test algorithm for selecting a template file;
the design parameter module can import a design parameter file (InputFile); the design parameter file comprises a plurality of rows of design parameters, and each row of design parameters comprises information of the device to be tested and parameters of the device to be tested in the test chip;
the template file module provides a template file editing environment and can acquire template items through manual editing or import template files to acquire the template items; the Template file (Template) comprises a plurality of Template items, each Template item selects a test algorithm and provides an assignment relation for generating information in the test item (TestItem) (the assignment is not a narrow numerical value and means that a field is assigned with a field value);
the test instruction file generation module can select a corresponding test algorithm according to the template item, and generate a plurality of test items (a plurality of testitems can be formed by analyzing one template item and one InputFile comprising a plurality of lines of design parameters) according to the assignment relational expression in the template item and the imported design parameter file, so as to realize the generation of the test instruction file;
wherein, the test instruction file (TestSpec) comprises a plurality of test items (TestItem), each test item is used for defining condition information for executing an electrical test on the device to be tested.
The tool for rapidly generating the test description file solves the problems of complexity and time consumption of the testSpec setting work, and can conveniently and rapidly generate the test description file.
As a further improvement, the template items comprise an assignment relational expression of a Module Name (Module Name), an assignment relational expression of a Device Name (Device Name), an assignment relational expression of Input information (Input), an assignment relational expression of Pad information (Pad Number), an assignment relational expression of Output information (Output), and a selected test Algorithm (Algorithm).
As a further improvement, the template item further includes at least one of Condition information (Condition), Group number (Group), and failure threshold (Limit); the condition information provides judgment conditions for screening the test items; the group number is used to define the group to which the test item belongs; the failure threshold is used to define a failure parameter threshold.
As a further refinement, the test item (TestItem) comprises information: the Module Name (Module Name) is used for representing the Module to which the device to be tested belongs and is obtained according to the information in the design parameters and the assignment relation of the Module Name in the template; the Device Name is used for representing the type of the Device to be tested (the type is a preset self-defined type, for example, the Device Name is MOD17_ N, and represents a type of NMOS tube in a module MOD 17), and the Device Name is obtained according to information in design parameters and an assignment relational expression of the Device Name in a template; the test Algorithm (Algorithm) is used for selecting the corresponding test Algorithm so as to determine the test content executed on the device to be tested and is defined by the template; input information (Input) used for defining test Input conditions for the device to be tested and obtained according to the information in the design parameters and the assignment relation of the Input information in the template; pad information (Pad Number) used for representing a Pad connected with a pin of a device to be tested and obtained according to the assignment relational expression of the information in the design parameters and the Pad information in the template; and the Output information (Output) is used for determining the test Output of the device to be tested and is obtained according to the information in the design parameters and the assignment relation of the Output information in the template item.
As a further improvement, the test item further includes at least one of Group number (Group) and failure threshold (Limit); the group number is used to indicate the group to which the test item belongs (for test items belonging to the same group to be put together for execution), and is defined by the template; the failure threshold is used for screening the test result parameters to distinguish and display failure parameters, and is defined by the template.
As a further improvement, in the template file module, the edited template file can be exported for repeated import use or modification. The tool for rapidly generating the test instruction file can reduce a lot of unnecessary operations and improve the working efficiency by supporting the import and export of a template file which is a middleware for formulating the test instruction file.
As a further improvement, the test instruction file generation module supports exporting test instruction files with different formats to match different test machines; the test instruction file generation module also provides a format editing environment of the test instruction file, and the test instruction file in the edited format is exported after the format editing is completed, so that the universality of the tool is greatly expanded.
As a further improvement, the test instruction file generation module can check the generated test items (the checking content includes whether the information in the test items is matched with the selected test algorithm, namely, whether the test items including the information can be tested by using the test algorithm is judged), and when the problem exists, the problem prompt is carried out.
The method for rapidly generating the test instruction file is characterized in that the tool for rapidly generating the test instruction file is used for importing a test algorithm and a design parameter file, and manually editing a template item or importing the template file to realize automatic generation of the test instruction file. The method can automatically generate the TestSpec to replace the situation that the original manual setting information is generated to generate the TestSpec, and solves the problems of complexity and time consumption of the TestSpec setting work.
A tool for generating a test plan is provided, which is characterized in that the tool can be used for making a description file required by the test plan and compiling a generated test plan (TestPlan); the specification files required by the test plan include a wafer information specification file (position information for defining the Die and Module to be tested) and a test specification file (TestSpec); the tool for rapidly generating the test instruction file is integrated in the tool for generating the test plan and is used for making the test instruction file.
As a further improvement, the tool for generating the test plan supports the derivation of the test plan in different formats to match different test machines.
According to the tool for generating the test plan, the tool for quickly generating the test description file is integrated, the original testSpec generated by manually setting information is updated to the testSpec which is generated by using tool software and can be repeatedly used, and the efficiency of planning the test plan can be greatly improved.
The test method is used for controlling a tester to perform electrical test on a device to be tested, and comprises the following steps:
step (1): a test machine obtains a test plan; the test plan is compiled and generated by using the tool for generating the test plan;
step (2): setting parameters of a probe station to complete needle alignment, and forming a test path by a tester through a probe card arranged in the probe station and a device to be tested on a test chip;
and (3): applying a test configuration file (Recipe Config) in a test machine, automatically setting test conditions and selecting a test plan for the test machine, and executing a test;
and (4): and finishing the test if all the test plans are finished.
As a further improvement, the test configuration file is formulated by a tool for formulating the test configuration file, and the tool for formulating the test configuration file comprises a creation module, an editing module and an input and output module; the creation module can add test configuration items; the test configuration item is used for a testing machine to set test conditions and select a test plan; the editing module can modify, copy and delete the test configuration items; the input and output module can carry out import and export operations on the test configuration file; the test configuration file comprises a plurality of test configuration items. The tool for formulating the test configuration file is used for creating and modifying the test configuration file (Recipe Config), so that the time cost can be effectively saved, the error risk can be reduced, the exported test configuration file can be reused, and the labor cost in the aspect of editing the test configuration file can be reduced.
As a further improvement, the test configuration item includes information:
identification id (recipe id): a unique ID for identification; test Algorithm (Algorithm File): acquiring a test algorithm (all test algorithms are stored in a test algorithm directory, and the test algorithms are selected from the test algorithm directory to be acquired), and defining an algorithm main body for testing; test Plan (Test Plan File): obtaining a test plan (all test plans are stored in a test plan directory, and a test plan is selected from the test plan directory to be obtained), and providing wafer information and test items; wafer specification information: selecting a Die and a Module from wafer information provided by a test plan; test Specification information (Test Spec): test items are selected from the test items provided by the test plan.
Preferably, the test configuration item further includes probe station wafer product information: the system is used for determining the wafer model identified by the probe station; more preferably, the test configuration item further includes failure threshold information: and acquiring a failure threshold (all failure threshold files are stored in a failure threshold file directory, and the failure threshold files are selected from the failure threshold file directory to be acquired) for screening test result parameters to distinguish and display failure parameters.
As a further improvement, the tool for formulating the test configuration file can check the information of the test configuration items, and when the problem exists, the problem is prompted. The content of the check comprises: confirming whether a file selected from various file directories exists; whether necessary information in the test configuration item is set or not is judged, the necessary information refers to identification ID, a test algorithm, a test plan, wafer level description information, grain level description information and test description information, and if the test configuration item comprises probe station wafer product information, the probe station wafer product information is also necessary information; the configuration item is tested for its unique identification ID.
As a further improvement, the editing module can also perform application sequence sorting operation on the test configuration items.
As a further improvement, the input/output module supports importing and exporting test configuration files of different formats to match different test machines; the input and output module also provides a format editing environment of the test configuration file, and the test configuration file of the edited format is exported after the format editing is finished.
Drawings
FIG. 1 is a schematic diagram of the tool for rapidly generating a test instruction file according to the present invention.
FIG. 2 is a diagram of an embodiment of the tool for rapidly generating test specification files of the present invention.
FIG. 3 is an implementation of a template item.
FIG. 4 is one implementation of a test specification file.
Fig. 5 is a flowchart of a conventional test.
FIG. 6 is a flow chart of the test provided by the present invention.
FIG. 7 is a schematic diagram of the structure and environment of the tool for creating test configuration files according to the present invention.
FIG. 8 is a diagram of an embodiment of a tool for formulating a test configuration file according to the present invention.
Detailed Description
The invention is described in further detail below with reference to the following detailed description and accompanying drawings:
as shown in fig. 1, the present embodiment provides a tool for quickly generating a test instruction file, which includes a test algorithm module, a design parameter module, a template file module, and a test instruction file generating module, and as shown in fig. 2, is an operation interface of an embodiment of the tool for quickly generating a test instruction file.
The test algorithm module can import a test algorithm file (AlgoFile), and can refer to the AlgoFile import function in fig. 2, so as to provide a test algorithm for selecting a template file.
The design parameter module can import a design parameter file (InputFile), which can refer to an InputFile import function in fig. 2. The design parameter file includes a plurality of line design parameters, each line design parameter includes information of the Device to be tested and parameters of the Device to be tested in the test chip, and refer to information such as Module, Cell Name, Device Name, Frame, Row, Column, High, Low, L, W, and the like displayed after the InputFile is imported in the example in fig. 2.
The template file module provides a template file editing environment and can acquire template items through manual editing or import template files to acquire the template items; the template file module can also export the edited template file for repeated import use or modification; reference may be made specifically to the Import Template, Export Template functions, and edit function areas of Template in FIG. 2. The Template file (Template) includes several Template items, each of which selects a test algorithm and provides an assignment relation for generating information in the test item (TestItem) (the assignment here is not a narrowly defined numerical value, and means that a field is assigned a field value). The template items comprise an assignment relational expression of a Module Name (Module Name), an assignment relational expression of a Device Name (Device Name), an assignment relational expression of Input information (Input), an assignment relational expression of Pad information (Pad Number), an assignment relational expression of Output information (Output), and a selected test Algorithm (Algorithm). In some embodiments, the template item further includes Condition information (Condition) that provides a judgment Condition for screening the test item, a Group number (Group) for defining a Group to which the test item belongs, and a failure threshold (Limit) for defining a failure parameter threshold; fig. 3 is a specific template item.
The test instruction file generation module can select a corresponding test algorithm according to the template item, and generate a plurality of test items according to the assignment relational expression in the template item and the imported design parameter file to realize the generation of the test instruction file; a plurality of test items can be formed by analyzing one template item and one InputFile comprising a plurality of rows of design parameters. The test instruction file generation module can also check the generated test items: whether the information in the test item is matched with the selected test algorithm or not is judged, namely whether the test item comprising the information can be tested by using the test algorithm or not is judged; when the existence of a problem is detected, problem prompt is performed, and the Verify function in fig. 2 can be referred to. The test instruction file generation module supports exporting test instruction files in different formats, and editors can select the exporting format according to specific needs so as to match different test machines, specifically referring to the Generator Spec function in FIG. 2; the test instruction file generation module also provides a format editing environment of the test instruction file, and the test instruction file in the edited format is exported after the format editing is completed.
The test instruction file (TestSpec) comprises a plurality of test items (TestItem), each test item is used for defining condition information for executing an electrical test on the device to be tested: the Module Name (Module Name) is used for representing the Module to which the device to be tested belongs and is obtained according to the information in the design parameters and the assignment relational expression of the Module Name in the template item; the Device Name is used for representing the type of the Device to be tested (the type is a preset self-defined type, for example, the Device Name is MOD17_ N, and represents a type of NMOS tube in a module MOD 17), and the Device Name is obtained according to information in the design parameters and an assignment relational expression of the Device Name in the template item; the test Algorithm (Algorithm) is used for selecting the corresponding test Algorithm so as to determine the test content executed on the device to be tested and is defined by the template item; input information (Input) used for defining test Input conditions for the device to be tested and obtained according to the information in the design parameters and the assignment relational expression of the Input information in the template items; pad information (Pad Number) used for representing a Pad connected with a pin of a device to be tested and obtained according to the information in the design parameters and the assignment relational expression of the Pad information in the template item; and the Output information (Output) is used for determining the test Output of the device to be tested and is obtained according to the information in the design parameters and the assignment relation of the Output information in the template item. In some embodiments, the test items further include a Group number (Group) and a failure threshold (Limit); the Group number (Group) is used to indicate the Group to which the test item belongs (performed together for test items belonging to the same Group), and is defined by the template item; the failure threshold (Limit) is used for screening the test result parameters to distinctively display the failure parameters, and the failure threshold is defined by the template item; FIG. 4 is a specific TestSpec.
Furthermore, the present embodiment also provides a method for quickly generating a test instruction file, which uses the above tool for quickly generating a test instruction file, imports a test algorithm and a design parameter file, and manually edits a template item or imports a template file to realize automatic generation of the test instruction file. The method can automatically generate the TestSpec to replace the situation that the original manual setting information is generated to generate the TestSpec, and solves the problems of complexity and time consumption of the TestSpec setting work.
Still further, a tool for generating a test plan can be used to create a specification file required for the test plan and compile a generated test plan (TestPlan); the specification files required by the test plan include a wafer information specification file (for defining the position information of the Die and Module to be tested) and a test specification file (TestSpec); the tool for rapidly generating the test instruction file is integrated in the tool for generating the test plan and used for making the test instruction file. The tool for rapidly generating the test instruction file is integrated in the tool for generating the test plan, so that the problems of complexity and time consumption of the testSpec setting work are solved, the test instruction file can be conveniently and rapidly generated, and the generation efficiency of the test plan is effectively improved; the tool for generating the test plan also supports the derivation of the test plan in different formats so as to match different test machines.
Furthermore, the present embodiment provides a testing method for controlling a tester to perform an electrical test on a device under test, including the following steps:
step (1): a test machine obtains a test plan; the test plan is compiled and generated by using the tool for generating the test plan;
step (2): setting parameters of a probe station to complete needle alignment, and forming a test path by a tester through a probe card arranged in the probe station and a device to be tested on a test chip;
and (3): applying a test configuration file (Recipe Config) in a test machine, automatically setting test conditions and selecting a test plan for the test machine, and executing a test;
and (4): and finishing the test if all the test plans are finished.
Illustratively, this embodiment further provides a tool for creating a test configuration file (Recipe Config), where the test configuration file (Recipe Config) includes a plurality of test configuration items, and the test configuration items are used by the application to perform setting of test conditions and selection of a test plan for the test machine. As shown in FIG. 7, the tool for formulating the test configuration file comprises a creation module, an editing module and an input/output module, and as shown in FIG. 8, an operation interface of one embodiment of the tool for formulating the test configuration file is shown.
The creating module may Add a test configuration item, which may refer to the Add function in fig. 8, where the created test configuration item includes information:
identification id (recipe id): a unique ID for identification;
test Algorithm (Algorithm File): selecting a test algorithm from a test algorithm catalog (all test algorithms are stored under the test algorithm catalog), and defining an algorithm main body of the test;
test Plan (Test Plan File): selecting a test plan from a test plan catalog (all test plans are stored in the test plan catalog), and providing wafer information and test items;
wafer specification information: selecting a Die and a Module from wafer information provided by a test plan;
test Specification information (Test Spec): test items are selected from the test items provided by the test plan.
In some embodiments, the test configuration items further include probe station wafer product information (Prober Recipe) and failure threshold information (Limit File); the probe station wafer product information is used for determining the wafer model identified by the probe station; the failure threshold information is used for acquiring a failure threshold (all failure threshold files are stored in a failure threshold file directory, and the failure threshold files are selected from the failure threshold file directory to be acquired), so as to screen test result parameters to distinguish and display failure parameters.
The editing module can modify, Copy and Delete the test configuration item, and refer to the Edit, Copy and Delete functions in fig. 8. In some embodiments, the editing module can also perform a sorting operation of the application order on the test configuration items.
The input/output module can perform Import and Export operations on the test configuration file, and refer to the Import and Export functions in fig. 8. The input and output module supports importing and exporting test configuration files with different formats so as to match different test machines; the input and output module also provides a format editing environment of the test configuration file, and the test configuration file of the edited format is exported after the format editing is finished.
The tool for formulating the test configuration file can check the information of the test configuration items: confirming whether a file selected from various file directories exists; whether necessary information in the test configuration item is set or not is judged, the necessary information refers to identification ID, a test algorithm, a test plan, wafer level description information, grain level description information and test description information, and if the test configuration item comprises probe station wafer product information, the probe station wafer product information is also necessary information; the configuration item is tested for its unique identification ID. When the existence of the problem is detected, problem prompt is carried out. In the step (3) of the test method, the test configuration file set in advance by the application is directly selected in the test process, so that the total time of the test process can be effectively saved. Because in the conventional test flow shown in fig. 5, each test requires manual setting of test conditions and manual selection of a required test plan, these manual operations add a certain time cost to the whole flow of the test; in addition, the manual setting of the test conditions and the manual selection of the required test plan are generally completed by manually editing the test configuration (Recipe configuration) file in the external text format, which has the disadvantages of huge content, easy error in modifying the file content, difficult maintenance, and once error occurs, the normal operation of the whole test process is affected. In the test method, the test configuration file set in advance is selected for application, the test conditions set and the test plan selected in the traditional process can be automatically applied, and the method can refer to fig. 6, so that human errors generated when the test conditions and the test plan are manually set each time are effectively avoided, and the total time of the test process is saved.
Finally, it should be noted that the above-mentioned list is only a specific embodiment of the present invention. It is obvious that the present invention is not limited to the above embodiments, but many variations are possible. All modifications which can be derived or suggested by a person skilled in the art from the disclosure of the present invention are to be considered within the scope of the invention.
Claims (10)
1. A tool for rapidly generating a test instruction file is characterized by comprising a test algorithm module, a design parameter module, a template file module and a test instruction file generation module;
the test algorithm module can import a test algorithm file and provide a test algorithm for selecting a template file;
the design parameter module can import a design parameter file; the design parameter file comprises a plurality of rows of design parameters, and each row of design parameters comprises information of the device to be tested and parameters of the device to be tested in the test chip;
the template file module provides a template file editing environment and can acquire template items through manual editing or import template files to acquire the template items; the template file comprises a plurality of template items, each template item selects a test algorithm and provides an assignment relational expression for generating information in the test item;
the test instruction file generation module can select a corresponding test algorithm according to the template item, and generate a plurality of test items according to the assignment relational expression in the template item and the imported design parameter file to realize the generation of the test instruction file;
the test instruction file comprises a plurality of test items, and each test item is used for defining condition information for executing an electrical test on the device to be tested.
2. The tool of claim 1, wherein the template items comprise module name assignment relationships, device name assignment relationships, input information assignment relationships, pad information assignment relationships, output information assignment relationships, and selected test algorithms.
3. The tool of claim 2, wherein the test items comprise information about:
module name: the module used for representing the device to be tested is obtained according to the information in the design parameters and the assignment relation of the module name in the template item;
device name: the device name assignment method is used for representing the type of a device to be tested and obtaining the type according to information in design parameters and an assignment relation of device names in template items;
and (3) testing an algorithm: the method is used for selecting a corresponding test algorithm to determine the test content executed on the device to be tested, and the test content is defined by a template item;
inputting information: the system comprises a template item, a test input condition and a parameter setting module, wherein the template item is used for defining the test input condition of a device to be tested and is obtained according to the assignment relational expression of information in design parameters and input information in the template item;
pad information: the template item is used for representing a bonding pad connected with a pin of a device to be tested and obtaining the bonding pad according to the information in the design parameters and the assignment relational expression of the bonding pad information in the template item;
outputting information: and the evaluation relation is obtained according to the information in the design parameters and the assignment relation of the output information in the template item.
4. The tool for rapidly generating the test instruction file as claimed in claim 1, wherein the template file module can export the edited template file for repeated import use or modification.
5. The tool for rapidly generating the test instruction file according to claim 1, wherein the test instruction file generation module supports exporting test instruction files with different formats to match different test machines; the test instruction file generation module also provides a format editing environment of the test instruction file, and the test instruction file in the edited format is exported after the format editing is completed.
6. The tool for rapidly generating the test instruction file as claimed in claim 1, wherein the test instruction file generation module can check the generated test items and prompt questions when the problems exist.
7. A method for rapidly generating a test instruction file, characterized in that, the tool for rapidly generating a test instruction file according to any one of claims 1 to 6 is used to import a test algorithm and a design parameter file, and manually edit a template item or import a template file to realize automatic generation of the test instruction file.
8. A tool for generating a test plan is characterized by being used for making a description file required by the test plan and compiling the generated test plan; the description files required by the test plan comprise a wafer information description file and a test description file; the tool for rapid test specification file generation of any one of claims 1 to 6 integrated in the tool for generating a test plan for formulating a test specification file.
9. The tool of claim 8, wherein the tool supports exporting test plans in different formats to match different test tools.
10. A test method is used for controlling a tester to perform electrical test on a device to be tested, and is characterized by comprising the following steps:
step (1): a test machine obtains a test plan; the test plan is compiled and generated using the tool for generating a test plan of claim 8;
step (2): setting parameters of a probe station to complete needle alignment, and forming a test path by a tester through a probe card arranged in the probe station and a device to be tested on a test chip;
and (3): applying a test configuration file in a test machine, automatically setting test conditions and selecting a test plan for the test machine, and executing a test;
and (4): and finishing the test if all the test plans are finished.
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