CN112445375A - Display device - Google Patents

Abstract

The present application relates to a display device. The display device includes a display panel and an input sensing panel, wherein the display panel includes a plurality of pixels and display pads connected to the pixels, the input sensing panel is on the display panel, and the input sensing panel includes an input sensing layer, an electrostatic sensing circuit, and a floating pattern circuit, wherein the input sensing layer includes a sensing electrode for sensing an input, a sensing line connected to the sensing electrode, and a sensing pad connected to the sensing line, the electrostatic sensing circuit is spaced apart from the sensing pad, and the floating pattern circuit is electrically insulated from the input sensing layer and includes a bridge pattern. The bridge pattern is connected to the electrostatic sensing circuit.

Description

Display device

Cross Reference to Related Applications

This application claims priority and benefit from korean patent application No. 10-2019-0109658, filed on 4/9/2019, the entire contents of which are incorporated herein by reference.

Technical Field

Aspects of exemplary embodiments of the present disclosure relate to an input sensing panel having improved durability and a display device including the same.

Background

The display device may include a display panel displaying an image and an input sensing panel sensing an external input. The input sensing panel may include a sensing electrode, a sensing line, and a sensing pad. The sense lines may transmit and/or receive signals.

The above information disclosed in this background section is for enhancement of understanding of the background of the disclosure, and therefore, it may contain information that does not form the prior art.

Disclosure of Invention

One or more exemplary embodiments of the present disclosure relate to an input sensing panel having improved durability and a display device including the same.

According to one or more exemplary embodiments of the present disclosure, a display device includes a display panel and an input sensing panel, wherein the display panel includes a plurality of pixels and display pads connected to the pixels, the input sensing panel is on the display panel, and the input sensing panel includes an input sensing layer, an electrostatic sensing circuit, and a floating pattern circuit, wherein the input sensing layer includes a sensing electrode configured to sense an input, a sensing line connected to the sensing electrode, and a sensing pad connected to the sensing line, the electrostatic sensing circuit is spaced apart from the sensing pad, and the floating pattern circuit is electrically insulated from the input sensing layer and includes a bridge pattern. The bridge pattern is connected to the electrostatic sensing circuit.

In an embodiment, the floating pattern circuit may include a resistance test pattern and an alignment pattern connected to the resistance test pattern.

In an embodiment, the electrostatic sensing circuit may include: a first electrostatic sensing pad and a second electrostatic sensing pad spaced apart from the first electrostatic sensing pad, and the sensing pad is between the first electrostatic sensing pad and the second electrostatic sensing pad; a first electrostatic sensing line surrounding a portion of the sensing electrode and including one end connected to the first electrostatic sensing pad; and a second electrostatic sensing line surrounding the other portion of the sensing electrode and including one end connected to the second electrostatic sensing pad. The other end of the first electrostatic sensing line and the other end of the second electrostatic sensing line may be spaced apart from each other.

In an embodiment, the bridge pattern may connect one of the first and second electrostatic sensing pads to the resistance test pattern.

In an embodiment, the bridge pattern may connect one of the first and second electrostatic sensing lines to the alignment pattern.

In an embodiment, the input sensing panel may further include a dummy pattern between the electrostatic sensing circuit and the floating pattern circuit.

In an embodiment, the dummy pattern may have one of a polygonal shape, an elliptical shape, and a circular shape.

In an embodiment, an input sensing panel may include a first conductive layer on a display panel, a first insulating layer covering the first conductive layer, and a second conductive layer on the first insulating layer.

In an embodiment, the first conductive layer may include a metal, the second conductive layer may include a transparent conductive material, and the bridge pattern may be defined as a portion of the first conductive layer.

In an embodiment, the second conductive layer may include a metal, the first conductive layer may include a transparent conductive material, and the bridge pattern may be defined as a portion of the second conductive layer.

In an embodiment, the display apparatus may further include: an active area defined in a first direction and a second direction crossing the first direction, the active area configured to provide light generated from the display panel; and a peripheral region surrounding the effective region. The display pad may be arranged at one side of the peripheral region in the first direction, and the sensing pad and the floating pattern circuit may be arranged at the other side of the peripheral region in the first direction to be spaced apart from the display pad in the second direction, and the active area is located between the display pad and the sensing pad and the floating pattern circuit.

In an embodiment, the display apparatus may further include a coupling member, and the display panel and the input sensing panel may be combined with each other by the coupling member.

In an embodiment, the input sensing panel may be directly disposed on the display panel.

Drawings

The above and other aspects and features of the present disclosure will become more apparent to those skilled in the art by the following detailed description of exemplary embodiments with reference to the attached drawings, in which:

fig. 1 is a perspective view of a display device according to an embodiment of the present disclosure;

fig. 2 is an exploded perspective view of a display device according to an embodiment of the present disclosure;

fig. 3A is a cross-sectional view of a display module according to an embodiment of the present disclosure;

fig. 3B is a cross-sectional view of a display module according to an embodiment of the present disclosure;

fig. 4A is a plan view of a display panel according to an embodiment of the present disclosure;

fig. 4B is an equivalent circuit diagram of a pixel according to an embodiment of the present disclosure;

FIG. 5 is a plan view of an input sensing panel according to an embodiment of the present disclosure;

fig. 6A is an enlarged view illustrating an area of an input sensing panel according to an embodiment of the present disclosure;

FIG. 6B is a cross-sectional view taken along line I-I' of FIG. 6A;

FIG. 6C is a cross-sectional view of an input sensing panel according to an embodiment of the present disclosure;

fig. 7 is an enlarged view illustrating an area of an input sensing panel according to an embodiment of the present disclosure;

fig. 8 is an enlarged view illustrating an area of an input sensing panel according to an embodiment of the present disclosure; and

fig. 9A to 9C are plan views of dummy patterns according to one or more embodiments of the present disclosure.

Detailed Description

Exemplary embodiments will hereinafter be described in more detail with reference to the accompanying drawings, wherein like reference numerals denote like elements throughout. This disclosure may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey aspects and features of the disclosure to those skilled in the art. Accordingly, processes, elements, and techniques not necessary to fully understand the aspects and features of the disclosure may not be described by those of ordinary skill in the art. Unless otherwise indicated, like reference numerals refer to like elements throughout the drawings and written description, and thus, the description thereof may not be repeated.

In the drawings, the relative sizes of elements, layers and regions may be exaggerated and/or simplified for clarity. Spatially relative terms, such as "under," "below," "lower," "beneath," "above," "upper" and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "beneath" can encompass both an orientation of above and below. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the spirit and scope of the present disclosure.

It will be understood that when an element or layer is referred to as being "on," "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or one or more intervening elements or layers may be present. Further, it will also be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting of the disclosure. As used herein, the singular forms "a" and "an" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," "including," "has," "having" and "has," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. When following an element of a list, expressions such as "at least one of …" modify the element of the entire list rather than modifying individual elements of the list.

As used herein, the terms "substantially," "about," and similar terms are used as approximate terms and not as degree terms, and are intended to leave margins for inherent deviations in measured or calculated values that will be recognized by those of ordinary skill in the art. In addition, "may" used in describing an embodiment of the present disclosure means "one or more embodiments of the present disclosure. As used herein, the terms "use," "using," and "using" may be understood as being synonymous with the terms "utilizing," "utilizing," and "utilizing," respectively. Additionally, the term "exemplary" is intended to mean exemplary or illustrative.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Fig. 1 is a perspective view of a display device according to an embodiment of the present disclosure. Fig. 2 is an exploded perspective view of a display device according to an embodiment of the present disclosure.

Referring to fig. 1 and 2, the display device EA may be a device activated according to an electrical signal. The display device EA may be implemented by (or used in) various electronic devices. For example, the display device EA may be used for large electronic devices such as televisions, monitors, external billboards, and the like, and small and/or medium electronic devices such as smart phones, tablet computers, personal computers, notebook computers, personal digital terminals, car navigation units (e.g., car navigation devices), game machines, portable electronic devices, cameras, and the like. However, the present disclosure is not limited thereto, and the above-described electronic devices are provided only as various examples, and thus, the display device EA may be used for other suitable electronic equipment and/or electronic devices without departing from the spirit and scope of the present disclosure. Hereinafter, as an illustrative example, the display device EA will be described as being included in a smart phone.

The display apparatus EA may display the image IM in the third direction DR3 (e.g., toward the third direction DR3) on the display surface FS parallel or substantially parallel to each of the first direction DR1 and the second direction DR 2. The image IM may include a still image and/or a moving image (e.g., a moving image). In fig. 1, as an illustrative example, the image IM is shown to include a clock and various icons. The display surface FS on which the image IM is displayed may correspond to a front surface of the display device EA, and may also correspond to a front surface of the window panel WP.

As used herein, a front surface (e.g., a top surface) or a back surface (e.g., a bottom surface) of each member may be defined in accordance with (e.g., based on) a direction in which the image IM is displayed (e.g., toward a direction in which the image IM is displayed). For example, the front and back surfaces may face away from each other in the third direction DR3 (e.g., may be opposing surfaces). The normal direction of each of the front and rear surfaces may be parallel or substantially parallel to the third direction DR 3. The directions indicated as the first direction DR1, the second direction DR2 and the third direction DR3 may be opposite and, therefore, may be modified differently to different suitable directions. Hereinafter, the first to third directions may be directions indicated by a first direction DR1, a second direction DR2, and a third direction DR3 shown in the drawings, and may be respectively represented by the same reference symbols. As used herein, the terms "on a plane" and "in plan view" may refer to a view from third direction DR3 (e.g., a view from a plane in third direction DR 3).

The display device EA may include a window panel WP, an anti-reflection panel RPP, a display module (e.g., a display or display assembly) DM, and a housing HU. In the present embodiment, the window panel WP and the case HU may be coupled to each other to define the appearance of the display device EA.

The window panel WP may comprise an optically transparent insulating material. For example, the window panel WP can comprise glass and/or plastic. The window panel WP may have a single-layer structure or a multi-layer structure. For example, the window panel WP may include a plurality of plastic films that may be bonded to each other by using an adhesive, or may include a glass substrate and a plastic film that may be bonded to each other by using an adhesive.

As described above, the front surface FS of the window panel WP may define the front surface of the display device EA. The front surface FS may include a transmissive area TA and a bezel area BZA. The transmissive area TA may be an optically transparent area. For example, the transmissive area TA may be an area having a visible light transmittance of about 90% or more.

The bezel area BZA may be an area having a light transmittance relatively smaller than that of the transmissive area TA. The bezel area BZA may define the shape of the transmission area TA. For example, the bezel area BZA may be disposed adjacent to the transmission area TA, and may at least partially surround the transmission area TA (e.g., surround the periphery of the transmission area TA).

The bezel area BZA may have a suitable or desired color (e.g., a predetermined color). The bezel area BZA may cover the peripheral area NAA of the display module DM to prevent or substantially prevent the peripheral area NAA from being visible from the outside. However, the present disclosure is not limited thereto. For example, in the window panel WP according to the embodiment of the present disclosure, the bezel region BZA may be omitted.

The anti-reflective panel RPP can be disposed below (e.g., under or below) the window panel WP. The anti-reflection panel RPP may reduce the reflectivity of external light incident thereon from the upper side of the window panel WP. However, the present disclosure is not limited thereto. For example, in the embodiment of the present disclosure, the anti-reflection panel RPP may be omitted or may be provided as a component included in the display module DM.

The display module DM may display the image IM and may sense an external input. The display module DM includes a front surface IS including an active area AA and a peripheral area NAA. The active area AA may be an area activated according to an electrical signal. The peripheral area NAA may at least partially surround the active area AA (e.g., around the periphery of the active area AA). However, the present disclosure is not limited thereto. For example, in various embodiments, the peripheral area NAA may be omitted, the peripheral area NAA in one direction may be omitted, or the peripheral area NAA may be adjacent to only two or fewer sides of the active area AA.

In the embodiment shown in fig. 2, the effective area AA may be an area in which the image IM is displayed, and may also be an area in which an external input is sensed. The transmissive area TA may overlap at least the effective area AA. For example, the transmissive area TA may overlap the entire surface of at least a portion of the active area AA. Accordingly, the user may observe the image IM through the transmissive area TA and/or may provide an external input through the transmissive area TA. However, the present disclosure is not limited thereto. For example, an area of the effective area AA in which the image IM is displayed and an area of the effective area AA in which an external input is sensed may be separated from each other, but is not limited to a specific embodiment.

The peripheral area NAA may be an area covered by the bezel area BZA. The peripheral area NAA may be adjacent to the effective area AA. The peripheral area NAA may at least partially surround the active area AA (e.g., around the periphery of the active area AA). A driving circuit and/or a driving line for driving the effective area AA may be disposed in the peripheral area NAA.

The display module DM may include a display panel DP and an input sensing panel ISL. In addition, the display module DM may include driving circuits CF1, CF2, and MB electrically connected to the display panel DP and the input sensing panel ISL.

The display panel DP may include (e.g., may be) a component (e.g., a component) that generates or substantially generates the image IM. The image IM generated by the display panel DP can be seen from the outside by the user through the transmissive area TA.

The input sensing panel ISL may sense an external input applied from the outside. As described above, the input sensing panel ISL may sense an external input provided to the window panel WP.

The driving circuits CF1, CF2, and MB may be electrically connected to the display panel DP and the input sensing panel ISL. The driving circuits CF1, CF2, and MB may include a main circuit board MB, a first circuit board CF1, and a second circuit board CF 2.

The first circuit board CF1 may be electrically connected to the display panel DP. The first circuit board CF1 may connect the display panel DP to the main circuit board MB. In this embodiment, the first circuit board CF1 may be provided as a flexible circuit film. However, the present disclosure is not limited thereto. For example, in other embodiments, the first circuit board CF1 may not be connected to the main circuit board MB, and/or the first circuit board CF1 may be a rigid circuit board.

The first circuit board CF1 may be connected to pads (e.g., display pads) of the display panel DP, which are disposed in the peripheral area NAA. The first circuit board CF1 supplies an electric signal for driving the display panel DP to the display panel DP. The electrical signal may be generated in the first circuit board CF1, or may be generated in the main circuit board MB.

The second circuit board CF2 may be electrically connected to the input sensing panel ISL. The second circuit board CF2 may connect the input sensing panel ISL to the main circuit board MB. In this embodiment, the second circuit board CF2 may be provided as a flexible circuit film. However, the present disclosure is not limited thereto. For example, the second circuit board CF2 may not be connected to the main circuit board MB, and/or the second circuit board CF2 may be a rigid circuit board.

The second circuit board CF2 may be connected to pads (e.g., sensing pads) of the input sensing panel ISL disposed in the peripheral area NAA. The second circuit board CF2 provides the input sensing panel ISL with an electrical signal for driving the input sensing panel ISL. The electric signal may be generated in the second circuit board CF2, or may be generated in the main circuit board MB.

The main circuit board MB may include various driving circuits for driving the display module DM and a connector for supplying power. Each of the first circuit board CF1 and the second circuit board CF2 may be connected to the main circuit board MB. According to an embodiment of the present disclosure, the display module DM may be controlled (e.g., may be easily controlled) by one main circuit board MB. However, the present disclosure is not limited thereto. For example, in the display module DM according to an embodiment of the present disclosure, the display panel DP and the input sensing panel ISL may be connected to different main boards, respectively, or one of the first circuit board CF1 and the second circuit board CF2 may not be connected to one main circuit board MB, but is not limited to a specific embodiment.

The first circuit board CF1 and the second circuit board CF2 may be bent in a direction toward the rear surface of the display panel DP. In this case, the first contact portion CN1 of the second circuit board CF2 may be connected to the second contact portion CN2 of the main circuit board MB in a state where the first circuit board CF1 and the second circuit board CF2 are bent.

In this embodiment, the first circuit board CF1 and the second circuit board CF2 may be disposed at sides of the display module DM different from each other (e.g., disposed in or on sides of the display module DM different from each other). For example, the first circuit board CF1 and the second circuit board CF2 may be spaced apart from each other in the second direction DR2, and the effective area AA is located between the first circuit board CF1 and the second circuit board CF 2. Accordingly, the second circuit board CF2 may be disposed at one side of the display module DM adjacent to the first edge DM-E1 of the display module DM, and the first circuit board CF1 may be disposed at the other side of the display module DM adjacent to the second edge DM-E2 of the display module DM. In an embodiment, the first edge DM-E1 may be spaced apart from the second edge DM-E2 in the second direction DR 2. However, the present disclosure is not limited thereto. For example, in another embodiment, the first circuit board CF1 and the second circuit board CF2 may be disposed at the same side of the display module DM as each other.

According to this embodiment, since the first circuit board CF1 and the second circuit board CF2 may be disposed at different sides of the display module DM from each other, the peripheral area NAA (e.g., an unnecessary portion of the peripheral area NAA) may be reduced. Accordingly, a display module DM including a reduced bezel (e.g., a narrow bezel) may be provided.

The housing HU may be coupled to the window panel WP. The housing HU may be coupled to the window panel WP to provide a suitable or desired interior space (e.g., a predetermined interior space). The display module DM may be accommodated in the inner space.

The housing HU may include a material having relatively high rigidity. For example, the housing HU may include glass, plastic, and/or metal, or may include a plurality of frames and/or plates made of a combination of glass, plastic, and/or metal. The casing HU may protect or substantially protect (e.g., may stably protect) components (e.g., components) of the display device EA that may be accommodated in the internal space from external impact.

Fig. 3A is a cross-sectional view of a display module according to an embodiment of the present disclosure. Fig. 3B is a cross-sectional view of a display module according to an embodiment of the present disclosure.

Referring to fig. 3A, a display module (e.g., a display or a display assembly) DM may include a display panel DP, an input sensing panel ISL, and a coupling member SLM.

The display panel DP according to the embodiment of the present disclosure may be an emissive type display panel, but the present disclosure is not limited thereto. For example, the display panel DP may be an organic light emitting display panel, a quantum dot light emitting display panel, a liquid crystal display panel, or the like.

The display panel DP may include the first substrate BS1, the display circuit layer ML-D, and the display element layer EML. The input sensing panel ISL may include a second substrate BS2 and a sensing circuit layer ML-T.

Each of the first substrate BS1 and the second substrate BS2 may be a silicon substrate, a plastic substrate, an insulating film, or a laminated structure including a plurality of insulating layers.

The display circuit layer ML-D may be disposed on the first substrate BS 1. The display circuit layer ML-D may include a plurality of insulating layers, a plurality of conductive layers, and a semiconductor layer. The plurality of conductive layers of the display circuit layer ML-D may define (e.g., may constitute) signal lines and/or control circuits of the pixels.

The display element layer EML may be disposed on the display circuit layer ML-D. The display element layer EML may be a layer that generates light and/or controls light transmittance. For example, the display element layer EML of the organic light emitting display panel may include an organic light emitting material. The display element layer EML of the quantum dot light emitting display panel may include at least one of quantum dots, quantum rods, and the like. The display element layer EML of the liquid crystal display panel may include a liquid crystal layer.

The second substrate BS2 may be disposed on the display element layer EML. A space (e.g., a predetermined space) may be defined between the second substrate BS2 and the display element layer EML. The space may be filled with air and/or an inert gas. In embodiments of the present disclosure, the space may be filled with a filler, such as, for example, a silicone-based polymer, an epoxy-based resin, or an acrylic-based resin.

The sensing circuit layer ML-T may be disposed on the second substrate BS 2. The sensing circuit layer ML-T may include a plurality of insulating layers and a plurality of conductive layers. The plurality of conductive layers may define (e.g., may constitute) a sensing electrode to sense an external input, a sensing line connected to the sensing electrode, and/or a sensing pad connected to the sensing line.

The coupling member SLM may be arranged between the first substrate BS1 and the second substrate BS 2. The coupling member SLM may couple the first substrate BS1 to the second substrate BS 2. The coupling member SLM may include an organic material such as a photo-curing resin or a photo-plastic resin, for example, or may include an inorganic material such as a frit seal, for example, but the disclosure is not limited thereto.

Referring to fig. 3B, a display module (e.g., a display or display assembly) DM-1 may include a display panel DP-1 and an input sensing unit (e.g., an input sensing layer) ISL-1. The input sensing unit ISL-1 may be referred to as an input sensing layer.

The display panel DP-1 may include the first substrate BS1, the display circuit layer ML-D, the display element layer EML, and the thin film encapsulation layer ECL. The input sensing cell ISL-1 may include a base layer ECL and a sensing circuit layer ML-T. The thin film encapsulation layer ECL and the base layer ECL may be the same layer.

According to an embodiment of the present disclosure, the display panel DP-1 and the input sensing unit ISL-1 may be formed through a continuous process. In other words, the sensing circuit layer ML-T may be directly disposed on the thin film encapsulation layer ECL.

Fig. 4A is a plan view of a display panel according to an embodiment of the present disclosure. Fig. 4B is an equivalent circuit diagram of a pixel according to an embodiment of the present disclosure.

Referring to fig. 4A, the display panel DP may include a plurality of pixels PX, a plurality of signal lines GL, DL, PL, and ECL, and a plurality of display pads PDD.

The effective area AA of the display panel DP may be an area in which an image is displayed, and the peripheral area NAA may be an area in which a driving circuit and/or a driving line is disposed. In fig. 4A, the effective area AA and the peripheral area NAA of the display panel DP are shown. A plurality of pixels PX may be disposed in the effective area AA.

A plurality of signal lines GL, DL, PL and ECL may be connected to the pixels PX to transmit electrical signals to the pixels PX. As an example, the scanning lines GL, the data lines DL, the power lines PL, and the emission control lines ECL among the signal lines provided in the display panel DP are shown in fig. 4A. However, the present disclosure is not limited thereto. For example, the signal line may further include an initialization voltage line, but the present disclosure is not limited thereto.

Referring to fig. 4B, a signal circuit diagram of one pixel PX among a plurality of pixels PX is shown as a representative example. Fig. 4B shows an example of the pixel PX connected to the ith scan line GLi and the ith emission control line ECLi (where i is a natural number).

The pixel PX may include a light emitting element EE and a pixel circuit CC. The pixel circuit CC may include a plurality of transistors T1 to T7 and a capacitor CP. The plurality of transistors T1 through T7 may be formed by a Low Temperature Polysilicon (LTPS) process or a Low Temperature Poly Oxide (LTPO) process.

The pixel circuit CC may control the amount of current flowing in the light emitting element EE in response to a data signal. The light emitting element EE may emit light having a desired luminance (e.g., a predetermined luminance) corresponding to the amount of current supplied from the pixel circuit CC. In this case, the level (e.g., voltage level or potential level) of the first power ELVDD may be set to be greater than the level (e.g., voltage level or potential level) of the second power ELVSS. The light emitting element EE may include an organic light emitting element or a quantum dot light emitting element.

Each of the plurality of transistors T1 through T7 may include an input electrode (e.g., a source electrode), an output electrode (e.g., a drain electrode), and a control electrode (e.g., a gate electrode). For convenience, as used in this specification, one of the input electrode and the output electrode may be referred to as a first electrode, and the other of the input electrode and the output electrode may be referred to as a second electrode.

A first electrode of the first transistor T1 may be connected to the first power source ELVDD via a fifth transistor T5. The second electrode of the first transistor T1 may be connected to the anode electrode of the light emitting element EE via the sixth transistor T6. In this specification, the first transistor T1 may be referred to as a driving transistor.

The first transistor T1 may control the amount of current flowing in the light emitting element EE according to the voltage applied to the control electrode of the first transistor T1.

The second transistor T2 may be connected between the data line DL and the first electrode of the first transistor T1. A control electrode of the second transistor T2 may be connected to the ith scan line GLi. When the ith scan signal is applied to the ith scan line GLi, the second transistor T2 may be turned on to electrically connect the data line DL to the first electrode of the first transistor T1.

The third transistor T3 may be connected between the second electrode of the first transistor T1 and the control electrode of the first transistor T1. A control electrode of the third transistor T3 may be connected to the ith scan line GLi. When the ith scan signal is supplied to the ith scan line GLi, the third transistor T3 is turned on to electrically connect the second electrode of the first transistor T1 to the control electrode of the first transistor T1. Accordingly, when the third transistor T3 is turned on, the first transistor T1 is diode-connected (e.g., the first transistor T1 is diode-connected).

The fourth transistor T4 may be connected between the node ND and an initialization power generating unit (e.g., an initialization power supply). The control electrode of the fourth transistor T4 may be connected to the (i-1) th scan line GLi-1. When the (i-1) th scan signal is supplied to the (i-1) th scan line GLi-1, the fourth transistor T4 is turned on to supply the initialization voltage Vint to the node ND.

The fifth transistor T5 may be connected between the power line PL and the first electrode of the first transistor T1. A control electrode of the fifth transistor T5 may be connected to the ith emission control line ECLi.

The sixth transistor T6 may be connected between the second electrode of the first transistor T1 and the anode electrode of the light emitting element EE. A control electrode of the sixth transistor T6 may be connected to the ith emission control line ECLi.

The seventh transistor T7 may be connected between the initialization power generation unit and the anode electrode of the light emitting element EE. A control electrode of the seventh transistor T7 may be connected to the (i +1) th scan line GLi + 1. When the (i +1) th scan signal is supplied to the (i +1) th scan line GLi +1, the seventh transistor T7 is turned on to supply the initialization voltage Vint to the anode electrode of the light emitting element EE.

The seventh transistor T7 may improve the black display capability of the pixel PX. For example, when the seventh transistor T7 is turned on, the parasitic capacitor of the light emitting element EE may be discharged. Therefore, when black luminance is realized, the light emitting element EE may not emit light due to the leakage current from the first transistor T1, and thus, black display performance may be improved.

Although fig. 4B illustrates that the control electrode of the seventh transistor T7 may be connected to the (i +1) th scan line GLi +1, the present disclosure is not limited thereto. For example, in another embodiment of the present disclosure, the control electrode of the seventh transistor T7 may be connected to the ith scan line GLi or the (i-1) th scan line GLi-1.

Capacitor CP may be disposed between power line PL and node ND. The capacitor CP stores a voltage corresponding to the data signal. When the fifth transistor T5 and the sixth transistor T6 are turned on, the amount of current flowing through the first transistor T1 may be determined according to the voltage stored in the capacitor CP.

However, the present disclosure is not limited to the equivalent circuit diagram of the pixel PX shown in fig. 4B. For example, according to another embodiment of the present disclosure, the pixel PX may have various suitable structures and/or shapes capable of causing the light emitting element EE to emit light. Although each of the transistors T1 to T7 is illustrated as a PMOS transistor in fig. 4B, the present disclosure is not limited thereto. For example, in another embodiment of the present disclosure, each of the transistors T1 to T7 of the pixel circuit CC may be implemented as an NMOS transistor (e.g., may be constituted by an NMOS transistor). In another example, in an embodiment of the present disclosure, the transistors T1 to T7 of the pixel circuit CC may be implemented as any suitable combination of NMOS transistors and PMOS transistors (e.g., may be composed of any suitable combination of NMOS transistors and PMOS transistors).

Referring again to fig. 4A, the power pattern VDD may be disposed in the peripheral area NAA. In this embodiment, the power supply pattern VDD may be connected to a plurality of power lines PL. Accordingly, the display panel DP may include the power supply pattern VDD to supply the same or substantially the same first power signal to the plurality of pixels PX.

The display pad PDD may include a first pad D1 and a second pad D2. The first pad D1 may be provided in plurality, and a plurality of first pads D1 may be respectively connected to the data lines DL. The second pad D2 may be connected to the power supply pattern VDD, and may be electrically connected to the power line PL. The display panel DP may supply an externally supplied (e.g., externally supplied) electric signal to the pixels PX through the display pads PDD. The display pad PDD may further include pads for receiving other electrical signals in addition to the first and second pads D1 and D2, but the present disclosure is not limited thereto.

Fig. 5 is a plan view of an input sensing panel according to an embodiment of the present disclosure. Fig. 6A is an enlarged view illustrating one region of an input sensing panel according to an embodiment of the present disclosure. FIG. 6B is a cross-sectional view taken along line I-I' of FIG. 6A; fig. 6C is a cross-sectional view of an input sensing panel according to an embodiment of the present disclosure.

Referring to fig. 5, the input sensing panel ISL may include a second substrate BS2 (see fig. 3A), a first sensing electrode TE1, a second sensing electrode TE2, a plurality of sensing lines TL1, TL2, and TL3, a plurality of sensing pads TP1, TP2, and TP3, electrostatic sensing cells (e.g., electrostatic sensors or electrostatic sensing circuits) ED1, ED2, EL1, and EL2, and floating pattern cells (e.g., floating pattern circuits) PT including bridge patterns PB. The first sensing electrode TE1, the second sensing electrode TE2, the plurality of sensing lines TL1, TL2, and TL3, and the plurality of sensing pads TP1, TP2, and TP3 according to the present embodiment may be defined as an input sensing unit (e.g., an input sensing layer or an input sensing circuit). The input sensing unit may be included in the sensing circuit layer ML-T described with reference to fig. 3A or 3B (e.g., may constitute the sensing circuit layer ML-T).

An active area AA-I and a peripheral area NAA-I may be defined on the second substrate BS 2. The peripheral area NAA-I may at least partially surround the active area AA-I (e.g., surround the periphery of the active area AA-I).

The first and second sensing electrodes TE1 and TE2 may be disposed in the active area AA-I. The input sensing panel ISL may obtain information corresponding to an external input through a capacitance change between the first sensing electrode TE1 and the second sensing electrode TE 2.

The first sensing electrode TE1 may include a first sensing pattern SP1 and a first connection pattern BP 1. The first sensing electrode TE1 may extend in the first direction DR1 and may be arranged along the second direction DR 2. The first sensing patterns SP1 may be arranged to be spaced apart from each other in the first direction DR 1. The at least one first connection pattern BP1 may be connected to two first sensing patterns SP1 adjacent to each other.

The second sensing electrode TE2 may include a second sensing pattern SP2 and a second connection pattern BP 2. The second sensing electrode TE2 may extend in the second direction DR2, and may be arranged along the first direction DR 1. The second sensing patterns SP2 may be arranged to be spaced apart from each other in the second direction DR 2. The at least one second connection pattern BP2 may be connected to two second sensing patterns SP2 adjacent to each other.

The sense lines TL1, TL2, and TL3 may be disposed in the peripheral region NAA-I. The sense lines TL1, TL2, and TL3 may include a first sense line TL1, a second sense line TL2, and a third sense line TL 3.

The first sensing line TL1 may be connected to the first sensing electrode TE 1. The second sensing line TL2 may be connected to one end of the second sensing electrode TE 2. The third sensing line TL3 may be connected to the other end of the second sensing electrode TE 2. The other end of the second sensing electrode TE2 may be an end opposite to one end of the second sensing electrode TE 2.

According to one or more embodiments of the present disclosure, the second sensing electrode TE2 may be connected to the second sensing line TL2 and the third sensing line TL 3. Accordingly, the sensitivity with respect to the area of the second sensing electrode TE2 may be maintained or substantially maintained (e.g., may be uniformly maintained), wherein the second sensing electrode TE2 may have a relatively longer length than the length of the first sensing electrode TE 1. However, the present disclosure is not limited thereto. For example, in an embodiment, the third sensing line TL3 may be omitted, but the disclosure is not limited thereto.

The sense pads TP1, TP2 and TP3 may be arranged in the peripheral region NAA-I. The sensing pads TP1, TP2, and TP3 may include a first sensing pad TP1, a second sensing pad TP2, and a third sensing pad TP 3. The first sensing pad TP1 may be connected to the first sensing line TL1 and may be electrically connected to the first sensing electrode TE 1. The second sense pad TP2 may be connected to the second sense line TL2, and the third sense pad TP3 may be connected to the third sense line TL 3. Accordingly, the second and third sensing pads TP2 and TP3 may be electrically connected to the second sensing electrode TE 2.

In this embodiment, the sensing pads TP1, TP2, and TP3 and the display pad PDD of the display panel DP may be disposed at different sides (e.g., in or on the sides) of the display module DM (e.g., see fig. 2) from each other. For example, the sensing pads TP1, TP2, and TP3 may be disposed to be spaced apart from the display pad PDD in the second direction DR2, and the active areas AA-I are located between the sensing pads TP1, TP2, and TP3 and the display pad PDD. Accordingly, the sensing pads TP1, TP2, and TP3 may be disposed at one side (e.g., in or on one side) of the display module DM adjacent to the first edge DM-E1 of the display module DM, and the display pad PDD may be disposed at the other side (e.g., in or on the other side) of the display module DM adjacent to the second edge DM-E2 of the display module DM, the second edge DM-E2 being spaced apart from the first edge DM-E1 in the second direction DR 2. For convenience, the display panel DP, the first circuit board CF1, and the display pad PDD are shown in fig. 5 by dotted lines.

The electrostatic sensing units ED1, ED2, EL1, and EL2 may be disposed in the peripheral region NAA-I. The electrostatic sensing cells ED1, ED2, EL1, and EL2 may include a first electrostatic sensing pad ED1, a second electrostatic sensing pad ED2, a first electrostatic sensing line EL1, and a second electrostatic sensing line EL 2.

The first and second electrostatic sensing pads ED1 and ED2 may be spaced apart from each other with the sensing pads TP1, TP2, and TP3 interposed between the first and second electrostatic sensing pads ED1 and ED 2. For example, the first electrostatic sensing pad ED1 may be disposed between the first sensing pad TP1 and the floating pattern unit PT, and the second electrostatic sensing pad ED2 may be disposed to be spaced apart from the third sensing pad TP 3. One end of the first electrostatic sensing line EL1 may be connected to the first electrostatic sensing pad ED1, and one end of the second electrostatic sensing line EL2 may be connected to the second electrostatic sensing pad ED 2.

In an embodiment, the first and second electrostatic sensing lines EL1 and EL2 may surround the sensing electrodes TE1 and TE2 (e.g., surround the periphery of the sensing electrodes TE1 and TE 2). For example, the first electrostatic sensing line EL1 may surround the right side (e.g., the right side of the effective area AA-I) of each of the sensing electrodes TE1 and TE2 (e.g., surround the periphery of the right side described above), and the second electrostatic sensing line EL2 may surround the left side (e.g., the left side of the effective area AA-I) of each of the sensing electrodes TE1 and TE2 (e.g., surround the periphery of the left side described above). The other ends of the first and second electrostatic sensing lines EL1 and EL2 may be spaced apart from each other. Accordingly, the first electrostatic sensing line EL1 and the second electrostatic sensing line EL2 can be electrically insulated from each other.

According to one or more embodiments of the present disclosure, the electrostatic sensing cells ED1, ED2, EL1, and EL2 surrounding the sensing electrodes TE1 and TE2 (e.g., surrounding the periphery of the sensing electrodes TE1 and TE 2) may be arranged to determine (e.g., easily determine) whether the input sensing cell is damaged by static electricity flowing from the outside to the input sensing cell.

The floating pattern unit PT may include a bridge pattern PB and a plurality of patterns RR, BR, and AM, which will be described in more detail below. The floating pattern unit PT (e.g., a floating pattern) may be electrically insulated from the input sensing unit. In fig. 6A, an example in which the floating pattern unit PT is disposed at an edge of the input sensing panel ISL and adjacent to the first electrostatic sensing pad ED1 is shown.

The floating pattern unit PT may be disposed within the floating region PTA. In the process of forming the input sensing panel ISL, the floating region PTA may be a region electrically insulated from the input sensing cells and provided with patterns RR, BR, and AM, which may be required for process convenience.

The patterns RR, BR, and AM included in the floating pattern unit PT may be electrically connected to each other, and thus, each of the sensing pads TP1, TP2, and TP3 and the electrostatic sensing pads ED1 and ED2 may have a relatively large area.

The floating pattern unit PT may be electrically connected to components (e.g., one component) of the electrostatic sensing units ED1, ED2, EL1, and EL2 through the bridge pattern PB. For example, as shown in fig. 5, the floating pattern unit PT and the first electrostatic sensing pad ED1 may be connected to each other by a bridge pattern PB.

Referring to fig. 6A, in an embodiment, the floating pattern unit PT may include a resistance test pattern RR, an alignment pattern AM, and a connection pattern BR. The resistance test pattern RR, the alignment pattern AM, and the connection pattern BR may be electrically insulated from the input sensing cell.

The alignment pattern AM may be used to align pads (not shown) disposed on the second circuit board CF2 (see, for example, fig. 2) and the sensing pads TP1, TP2, and TP3, or may be used to identify the positions of the pads when signals are applied to the electrostatic sensing cells ED1, ED2, EL1, and EL2 or to the resistance test pattern RR. Although shown as having in FIG. 6A

One alignment pattern AM of the shape, but the present disclosure is not limited thereto. For example, the alignment pattern AM may be provided in plurality, and/or may have various suitable shapes, but the present disclosure is not limited thereto.

The resistance test pattern RR may be disposed adjacent to the first electrostatic sensing pad ED 1. The resistance test pattern RR may include (e.g., may be) pads for determining whether the second circuit board CF2 (e.g., see fig. 2) is bonded to the sensing pads TP1, TP2, and TP 3. Although one resistance test pattern RR is illustrated in fig. 6A, the present disclosure is not limited thereto, and the resistance test pattern RR may be provided in plurality.

The connection pattern BR may connect the resistance test pattern RR to the alignment pattern AM. For convenience, the connection pattern BR is described as a separate constituent (e.g., a separate component), but the patterns constituting the floating pattern unit PT may be formed through the same or substantially the same process. Thus, the patterns may comprise the same or substantially the same material as each other and may be provided on the same insulating layer.

The floating pattern unit PT may be disposed adjacent to an outermost side of the input sensing panel ISL, and may have a larger area than that of each of the relatively adjacent pads TP1, TP2, TP3, ED1, and ED2, so that static electricity flowing from the outside may be charged in the floating pattern unit PT (e.g., may be easily charged in the floating pattern unit PT). Static electricity charged in the floating pattern unit PT may flow into the adjacent sensing lines TL1, TL2, and TL3, and/or may flow into one constituent part (e.g., one component) of the input sensing unit, which may cause a defect of the input sensing panel ISL.

In fig. 6A, an example in which static electricity charged in the alignment pattern AM of the floating pattern unit PT flows into the first sensing line TL1 to cause the defect SP is shown as a dotted arrow.

According to one or more embodiments of the present disclosure, the floating pattern unit PT may be connected to the electrostatic sensing units ED1, ED2, EL1, and EL2 electrically insulated from the input sensing unit to provide a path through which static electricity charged in the floating pattern unit PT may be introduced into the electrostatic sensing units ED1, ED2, EL1, and EL 2. Accordingly, a path through which static electricity charged in the floating pattern unit PT is introduced into the input sensing unit may be blocked or substantially blocked to reduce defects of the input sensing panel ISL that may be caused by the static electricity. Accordingly, a display device having improved reliability can be provided.

Referring to fig. 6B, the sensing circuit layer ML-T of the input sensing panel ISL according to an embodiment of the present disclosure may include a first insulating layer TIL1, a second insulating layer TIL2, a first conductive layer TC1, and a second conductive layer TC 2. Although examples of constituent parts (e.g., components) corresponding to the sensing circuit layer ML-T disposed on the second substrate BS2 of fig. 3A are shown in fig. 6B and 6C, the present disclosure is not limited thereto. For example, components (e.g., components) corresponding to the sensing circuit layer ML-T of FIGS. 6B and 6C may be equally or substantially equally applied to the sensing circuit layer ML-T of FIG. 3B. In this case, the constituent parts (e.g., components) corresponding to the sensing circuit layer ML-T shown in fig. 6B and 6C may be disposed on the base layer (e.g., thin film encapsulation layer) ECL as shown in fig. 3B, instead of the second substrate BS2 shown in fig. 6B and 6C.

The first conductive layer TC1 is disposed on the second substrate BS 2. In an embodiment, the first conductive layer TC1 may include a metal material. For example, the first conductive layer TC1 may include molybdenum, silver, titanium, copper, aluminum, or a combination (e.g., an alloy) thereof. In an embodiment, the alloy may be, for example, molybdenum niobium.

When the first conductive layer TC1 includes a metal, the first conductive layer TC1 may be defined as a portion of the first connection pattern BP1, the first sensing line TL1, the electrostatic sensing pads ED1 and ED2, the electrostatic sensing lines EL1 and EL2, and a portion of the floating pattern unit PT (e.g., a portion of the bridge pattern PB, the connection pattern BR, and the resistance test pattern RR) among constituent portions (e.g., components) of the input sensing panel ISL shown in fig. 5. In an embodiment, the connection pattern BR and the bridge pattern PB may be disposed at the same layer as each other (e.g., disposed in or on the same layer as each other).

Fig. 6B shows an exemplary cross-sectional view taken along line I-I' of fig. 6A, showing a first sensing line TL1 of sensing lines TL1, TL2, and TL3, a first electrostatic sensing pad ED1 of electrostatic sensing pads ED1 and ED2, and a first electrostatic sensing line EL1 of electrostatic sensing lines EL1 and EL 2.

The first insulating layer TIL1 may cover the first conductive layer TC 1. The first insulating layer TIL1 may include an inorganic material, for example, including at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide.

The second conductive layer TC2 may be disposed on the first insulating layer TIL 1. In an embodiment, the second conductive layer TC2 may include a transparent conductive material. As used in this specification, transparent may refer to a light transmittance that is greater than or equal to a reference (e.g., a predetermined reference). For example, the reference may be about 90%, but the disclosure is not limited thereto. The second conductive layer TC2 may include a transparent conductive oxide, for example, including at least one of Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Indium Gallium Oxide (IGO), and Indium Gallium Zinc Oxide (IGZO), or including a mixture/compound thereof. However, the present disclosure is not limited thereto.

When the second conductive layer TC2 includes a transparent conductive material, the second conductive layer TC2 may be defined as sensing patterns SP1 and SP2, remaining portions of the second connection pattern BP2, the electrostatic sensing pads ED1 and ED2, and remaining portions of the floating pattern unit PT (e.g., remaining portions of the resistance test pattern RR and the alignment pattern AM) in constituent parts (e.g., components) of the input sensing panel ISL of fig. 5.

In an embodiment, the first sensing pattern SP1 and the first connection pattern BP1 may be connected to each other through a contact hole extending through (e.g., passing through) the first insulating layer TIL 1.

The second insulating layer TIL2 may cover the second conductive layer TC 2. The second insulating layer TIL2 may include an inorganic material, for example, including at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide.

Referring to fig. 6C, the sensing circuit layer ML-T0 of the input sensing panel ISL-0 according to an embodiment of the present disclosure may include a first insulating layer TIL1-0, a second insulating layer TIL2-0, a first conductive layer TC1-0, and a second conductive layer TC 2-0. The first and second insulating layers TIL1-0 and TIL2-0 may be the same or substantially the same as the first and second insulating layers TIL1 and TIL2 described with reference to FIG. 6B.

In an embodiment, the first conductive layer TC1-0 may include a transparent conductive material, and the second conductive layer TC2-0 may include a metal.

Since the first conductive layer TC1-0 includes a transparent conductive material, the first conductive layer TC1-0 may be defined as sensing patterns SP1 and SP2, a portion of the second connection pattern BP2, the electrostatic sensing pads ED1-0 and ED2-0, and a portion of the floating pattern unit (e.g., the floating pattern circuit) PT-0 (e.g., a portion of the resistance test pattern RR-0 and the alignment pattern AM-0) in the constituent parts (e.g., components) of the input sensing panel ISL of fig. 5.

When the second conductive layer TC2-0 includes a metal, the second conductive layer TC2-0 may be defined as the remaining portions of the first connection pattern BP1, the first sensing line TL1-0, the electrostatic sensing pads ED1-0 and ED2-0, the electrostatic sensing lines EL1-0 and EL2-0, and the floating pattern unit PT-0 (e.g., the remaining portions of the bridge pattern PB-0, the connection pattern BR-0, and the resistance test pattern RR-0) in the constituent parts (e.g., components) of the input sensing panel ISL of fig. 5. In an embodiment, the connection pattern BR-0 and the bridge pattern PB-0 may be formed at the same layer as each other (e.g., formed in or on the same layer as each other).

In an embodiment, the first sensing pattern SP1 and the first connection pattern BP1 may be connected to each other through a contact hole extending through (e.g., passing through) the first insulation layer TIL 1.

FIG. 6C illustrates an exemplary cross-sectional view taken along line I-I' of FIG. 6A, showing a first sensing line TL1-0 of sensing lines TL1-0, TL2 and TL3, a first electrostatic sensing pad ED1-0 of electrostatic sensing pads ED1-0 and ED2, and a first electrostatic sensing line EL1-0 of electrostatic sensing lines EL1-0 and EL 2.

Fig. 7 is an enlarged view illustrating a region of an input sensing panel according to an embodiment of the present disclosure. Fig. 8 is an enlarged view illustrating a region of an input sensing panel according to an embodiment of the present disclosure. The same/similar reference numerals are used for components that are the same as or substantially the same as (or similar to) those of fig. 1 to 6C, and thus, redundant description thereof may be simplified or may not be repeated.

Referring to fig. 7, the bridge pattern PB-1 according to the embodiment may be connected to the alignment pattern AM and the first electrostatic sensing line EL 1.

According to an embodiment, the bridge pattern PB-1 may be connected to a portion of the alignment pattern AM closest to the first sensing line TL 1. For example, the bridge pattern PB-1 may be connected to a protruding portion of the alignment pattern AM extending toward (e.g., facing) the first sensing line TL1, and the bridge pattern PB-1 may be disposed on the first electrostatic sensing line EL1 to prevent or substantially prevent (e.g., effectively prevent) static electricity introduced from the outside from being introduced into the first sensing line TL 1. However, the present disclosure is not limited thereto. For example, when the bridge pattern PB-1 is connected to a region of the alignment pattern AM protruding adjacent to the input sensing cell and is connected to the second electrostatic sensing line EL2 to provide a path through which static electricity introduced from the outside flows through the electrostatic sensing cells ED1, ED2, EL1, and EL2, the connection position and/or shape of the bridge pattern PB-1 may not be limited to a specific embodiment.

Referring to fig. 8, according to an embodiment, the input sensing panel ISL (see fig. 5) may further include a dummy pattern DMP disposed between the floating pattern unit PT and the electrostatic sensing units ED1 and EL1 and electrically insulated from the input sensing unit. The dummy patterns DMP may be disposed in plurality and may be spaced apart from each other in the first direction DR1 and the second direction DR 2.

The dummy patterns DMP may be disposed at the same layer as that of the bridge pattern PB (e.g., disposed in or on the same layer as that of the bridge pattern PB). The dummy pattern DMP may include a metal.

When the input sensing panel ISL includes the dummy pattern DMP, the dummy pattern DMP may be disposed between the floating pattern unit PT and the electrostatic sensing units ED1 and EL1, so that static electricity charged in the floating pattern unit PT may be introduced into the dummy pattern DMP, thereby providing a display device having improved reliability.

Fig. 9A to 9C are plan views of dummy patterns according to one or more embodiments of the present disclosure. The same/similar reference numerals are used to denote components and/or configurations that are the same as or substantially the same as (or similar to) those of fig. 1 to 6C and 8, and thus, redundant description thereof may be simplified or may not be repeated.

Referring to fig. 9A to 9C, in an embodiment, the dummy patterns DMP- ｃA may be disposed in ｃA triangular shape. In an embodiment, the dummy patterns DMP-B may be disposed in an elliptical shape. In an embodiment, the dummy patterns DMP-C may be disposed in a trapezoidal shape. However, the present disclosure is not limited thereto. For example, the dummy patterns may be disposed in a polygonal shape and/or a circular shape, may be disposed in a plurality, and/or may have different shapes such that the dummy patterns may be disposed in different shapes from each other, but the present disclosure is not limited thereto.

Referring to fig. 2 and 5, although the circuit boards CF1 and CF2 according to one or more embodiments of the present disclosure are described as being disposed on the edges DM-E1 and DM-E2 of the display module DM that are different from each other, the present disclosure is not limited thereto. For example, the circuit boards CF1 and CF2 may be disposed on edges of the display module DM adjacent to each other, but the present disclosure is not limited thereto.

According to one or more exemplary embodiments of the present disclosure, the floating pattern unit may be connected to the electrostatic sensing unit electrically insulated from the input sensing unit to provide a path through which static electricity charged in the floating pattern unit may flow into the electrostatic sensing unit. Accordingly, a path through which static electricity charged in the floating pattern unit may be introduced into the input sensing unit may be blocked or substantially blocked to prevent or reduce a defect of the input sensing panel due to the static electricity. Accordingly, a display device having improved reliability can be provided.

Although a few exemplary embodiments have been described, those skilled in the art will readily appreciate that various modifications may be made in the exemplary embodiments without departing from the spirit and scope of the present disclosure. It should be understood that the description of features or aspects within each embodiment should generally be considered as applicable to other similar features or aspects in other embodiments, unless described otherwise. It is therefore to be understood that the foregoing is illustrative of various exemplary embodiments and is not to be construed as limited to the specific exemplary embodiments disclosed herein, and that various modifications to the disclosed exemplary embodiments, as well as other exemplary embodiments, are intended to be included within the spirit and scope of the present disclosure as defined by the appended claims and their equivalents.

Claims (13)

1. A display device, comprising:

a display panel including a plurality of pixels and a display pad connected to the pixels; and

an input sensing panel on the display panel, and the input sensing panel includes:

an input sensing layer comprising:

a sensing electrode configured to sense an input;

a sensing line connected to the sensing electrode; and

a sensing pad connected to the sensing line;

an electrostatic sensing circuit spaced apart from the sensing pad; and

a floating pattern circuit electrically insulated from the input sensing layer and including a bridge pattern,

wherein the bridge pattern is connected to the electrostatic sensing circuit.

2. The display device according to claim 1, wherein the floating pattern circuit includes a resistance test pattern and an alignment pattern connected to the resistance test pattern.

3. The display device according to claim 2, wherein the electrostatic sensing circuit comprises:

a first electrostatic sensing pad and a second electrostatic sensing pad spaced apart from the first electrostatic sensing pad, and the sensing pad is located between the first electrostatic sensing pad and the second electrostatic sensing pad;

a first electrostatic sensing line surrounding a portion of the sensing electrode and including one end connected to the first electrostatic sensing pad; and

a second electrostatic sensing line surrounding the other portion of the sensing electrode and including one end connected to the second electrostatic sensing pad,

wherein the other end of the first electrostatic sensing line and the other end of the second electrostatic sensing line are spaced apart from each other.

4. The display apparatus of claim 3, wherein the bridge pattern connects one of the first and second electrostatic sensing pads to the resistance test pattern.

5. The display device of claim 3, wherein the bridge pattern connects one of the first and second electrostatic sense lines to the alignment pattern.

6. The display device of claim 1, wherein the input sensing panel further comprises a dummy pattern between the electrostatic sensing circuit and the floating pattern circuit.

7. The display device of claim 6, wherein the dummy pattern has one of a polygonal shape, an elliptical shape, and a circular shape.

8. The display device of claim 1, wherein the input sensing panel comprises:

a first conductive layer on the display panel;

a first insulating layer covering the first conductive layer; and

a second conductive layer on the first insulating layer.

9. The display device according to claim 8, wherein the first conductive layer comprises a metal,

the second conductive layer comprises a transparent conductive material, an

The bridge pattern is defined as a portion of the first conductive layer.

10. The display device according to claim 8, wherein the second conductive layer comprises a metal,

the first conductive layer comprises a transparent conductive material, an

The bridge pattern is defined as a portion of the second conductive layer.

11. The display device of claim 1, further comprising:

an active area defined in a first direction and a second direction crossing the first direction, the active area configured to provide light generated from the display panel; and

a peripheral area surrounding the active area,

wherein the display pads are arranged at one side of the peripheral area along the first direction, an

Wherein the sensing pad and the floating pattern circuit are arranged at the other side of the peripheral region along the first direction to be spaced apart from the display pad in the second direction, and the active region is located between the sensing pad and the floating pattern circuit and the display pad.

12. The display device of claim 1, further comprising a coupling member,

wherein the display panel and the input sensing panel are combined with each other by the coupling member.

13. The display device of claim 1, wherein the input sensing panel is disposed directly on the display panel.

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