CN112433589B - Double-margin DSP anti-reset locking circuit - Google Patents
Double-margin DSP anti-reset locking circuit Download PDFInfo
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- CN112433589B CN112433589B CN202011192641.3A CN202011192641A CN112433589B CN 112433589 B CN112433589 B CN 112433589B CN 202011192641 A CN202011192641 A CN 202011192641A CN 112433589 B CN112433589 B CN 112433589B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
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Abstract
The invention relates to a double margin DSP anti-lock circuit, comprising: the circuit comprises a main DSP circuit, a standby DSP circuit, a JTAG port circuit, a crystal oscillator circuit, a watchdog circuit and a CPLD circuit. When the JTAG port is connected with the programming device, no matter the standby CPU RESET signal RES and the watchdog RESET signal RESET, the main DSP can not be RESET, and the DSP is prevented from being locked during programming. When the programming device is not connected to the JTAG port, the RST signal can be enabled to be low level by any signal of RES and RESET, and the main DSP is RESET. The circuit of the invention avoids the locking of the DSP caused by human misoperation of a double-margin DSP circuit, and is simple and reliable.
Description
Technical Field
The invention belongs to the technical field of double-margin DSP application, relates to a DSP anti-lock circuit, and particularly relates to a double-margin DSP programming anti-lock circuit.
Background
In the technical field of double-margin DSP application, in order to prevent DSP programs from running away and ensure the normal operation of a system, an external hardware watchdog circuit is required. In order to ensure that the main DSP and the standby DSP of the double-margin DSP work normally, a reset signal is generated between the main DSP and the standby DSP.
Under normal conditions, the program can output a dog feeding signal, and the watchdog circuit can not output a reset signal. Meanwhile, if the handshake of the main DSP and the standby DSP is normal, the standby DSP can not output a reset signal. When the main DSP burns the program, the watchdog and the standby DSP can output reset signals to cause the main DSP to be locked.
Therefore, when a program is programmed in a traditional double-margin DSP programming mode, a reset signal needs to be shielded through a jumper wire. The mode is complex to operate, if human negligence occurs, the DSP can be locked due to program burning when the reset signal is not shielded, and faults such as poor contact and the like can exist after the jumper wire is used for a long time, so that the reset signal is not effectively shielded.
Disclosure of Invention
The invention aims to solve the problems, the invention provides a safe and reliable dual-margin DSP anti-reset locking circuit, and the problem of locking when a DSP burns a program due to reset signal shielding failure caused by human errors or device failure is solved.
The technical scheme of the invention is as follows:
a dual margin DSP anti-reset deadlock circuit, comprising: the circuit comprises a main DSP circuit, a standby DSP circuit, a JTAG port circuit, a crystal oscillator circuit, a watchdog circuit and a CPLD circuit;
the method is characterized in that: in the process of programming a program in a main DSP circuit, after a crystal oscillation signal CLK generated by a crystal oscillation circuit is connected into a CPLD circuit, a watchdog circuit outputs a RESET signal RESET to the CPLD circuit, a standby DSP circuit outputs a RESET signal RES to the CPLD circuit, a JTAG port circuit outputs a TCK signal to the CPLD circuit, and after the signals are logically processed in the CPLD circuit, the main DSP RESET signal RST is output to the main DSP circuit.
The CPLD circuit is characterized by comprising a counter U1, an OR gate U2, a D trigger U3, an OR gate U4, an AND gate U5 and a NOT gate U6; wherein, TCK signal inputs CLK pin of the counter U1; four paths of output signals QA-QD of the counter U1 are connected with the input of the OR gate U2; the output of the OR gate U2 is connected with a D pin of a D trigger U3; a crystal oscillation signal CLK generated by the crystal oscillation circuit is connected with an ENA pin of a D trigger U3; the crystal oscillator circuit generates a crystal oscillator signal CLK which is connected with a zero clearing pin CLRN of the counter U1 after passing through the NOT gate U6; an output pin Q of the D trigger U3 is connected with an input pin of an OR gate U4; the RESET signal RES of the DSP circuit and the RESET signal RESET of the watchdog circuit are connected with the other input pin of the OR gate U4 after passing through the AND gate U5; or gate U4 outputs reset signal RST.
When the JTAG port circuit is connected with the writer, TCK signals of the JTAG port circuit are input into a counter U1, a CLK pin of the counter U1 has a clock signal at the moment, at least one pin of QA-QD outputs high level, and the high level is output to a D pin of a D trigger U3 after passing through an OR gate U4; the crystal oscillator circuit outputs a CLK signal, and the CLK signal enables a Q pin of the D trigger U3 to output a high level of a D pin; at this time, one input of the or gate U4 is at a high level, and no matter the reset signal REST of the watchdog circuit and the reset signal of the standby DSP circuit are at a high level or a low level, the output signal RST can only be at a high level, and the main DSP circuit cannot be reset, so that it is ensured that the main DSP circuit does not have a reset signal when programming a program, and the main DSP cannot be locked due to the reset signal when programming the program.
The TCK signal of the JTAG port circuit is a 10MHZ clock signal.
The crystal oscillator circuit is characterized by outputting 1MHZ CLK signals.
The method is characterized in that when the JTAG port circuit is not connected with a writer, the CLK pin of the counter U1 has no clock signal at the moment, the CLK signal output by the crystal oscillator circuit enables the counter U1 to count and clear, QA-QD outputs low level, the low level is output to the D pin of the D trigger U3 after passing through an OR gate U4, the crystal oscillator circuit outputs the CLK signal, and the CLK signal enables the Q pin of the D trigger U3 to output the low level of the D pin; the output signal RST of the or gate U4 is related to the states of the reset signal REST of the watchdog circuit and the reset signal RES of the standby DSP circuit, and the main DSP circuit can be reset.
The crystal oscillator circuit is characterized in that the crystal oscillator circuit outputs 1MHZ CLK signals.
Characterized in that the main DSP circuit is RESET when either one of the RESET and RES signals is active.
The invention has the beneficial effects that:
the circuit has no jumper wire or switching switch and other devices, and does not need complex operation when programming. The locking of the DSP during program programming caused by reset signal shielding failure caused by human error or device failure is avoided. The circuit can be realized by devices in the existing system without adding new devices. The difficulty of design change is reduced, and the circuit design cost is reduced.
Drawings
FIG. 1 is a schematic diagram of a dual margin DSP anti-reset lock-up circuit
CPLD circuit logic schematic of FIG. 2
Detailed Description
The connection structure of the present invention will be described in detail with reference to the accompanying drawings and examples.
As shown in fig. 1, the dual margin DSP anti-reset deadlock circuit of the present invention includes: the circuit comprises a main DSP circuit, a standby DSP circuit, a JTAG port circuit, a crystal oscillator circuit, a watchdog circuit and a CPLD circuit; in the process of programming a program in a main DSP circuit, a crystal oscillator circuit generates a crystal oscillator signal CLK, the crystal oscillator signal CLK is connected into a CPLD circuit, a watchdog circuit outputs a RESET signal RESET to the CPLD circuit, a spare DSP circuit outputs a RESET signal RES to the CPLD circuit, a JTAG port circuit outputs a TCK signal to the CPLD circuit, and after the signals are logically processed in the CPLD circuit, the signals output a main DSP RESET signal RST to the main DSP circuit.
As shown in fig. 2, the CPLD circuit includes a counter U1, an or gate U2, a D flip-flop U3, an or gate U4, an and gate U5, and a not gate U6; wherein, TCK signal inputs CLK pin of the counter U1; four output signals QA-QD of the counter U1 are connected with the input of the OR gate U2; the output of the OR gate U2 is connected with a D pin of a D trigger U3; a crystal oscillation signal CLK generated by the crystal oscillation circuit is connected with an ENA pin of a D trigger U3; the crystal oscillator circuit generates a crystal oscillator signal CLK which is connected with a zero clearing pin CLRN of the counter U1 after passing through the NOT gate U6; an output pin Q of the D trigger U3 is connected with an input pin of the OR gate U4; the RESET signal RES of the DSP circuit and the RESET signal RESET of the watchdog circuit are connected with the other input pin of the OR gate U4 after passing through the AND gate U5; or gate U4 outputs a reset signal RST.
When the JTAG port circuit is connected with the writer, the TCK signal of the JTAG port circuit is a 10MHZ clock signal, the CLK pin of the counter U1 has a clock signal at the moment, at least one pin QA-QD outputs high level, and the high level is output to the D pin of the D trigger U3 after passing through the OR gate U4; the crystal oscillator circuit outputs a 1MHZ CLK signal, and the CLK signal enables a Q pin of a D trigger U3 to output a high level of a D pin; at this time, one input of the or gate U4 is at a high level, and no matter the reset signal REST of the watchdog circuit and the reset signal of the standby DSP circuit are at a high level or a low level, the output signal RST can only be at a high level, and the main DSP circuit cannot be reset, so that it is ensured that the main DSP circuit does not have a reset signal when programming the program, and the main DSP cannot be locked due to the reset signal when programming the program.
When the JTAG port circuit is not connected with the writer, the CLK pin of the counter U1 has no clock signal at the moment, the CLK signal output by the crystal oscillator circuit enables the counter U1 to count and clear, QA-QD outputs low level, the low level is output to the D pin of the D trigger U3 after passing through an OR gate U4, the crystal oscillator circuit outputs 1MHZ CLK signal, and the CLK signal enables the Q pin of the D trigger U3 to output the low level of the D pin; the output signal RST of the or gate U4 is related to the states of the RESET signal REST of the watchdog circuit and the RESET signal RES of the standby DSP circuit, the main DSP circuit can be RESET, and when either of the RESET and RES signals is active, the main DSP circuit is RESET.
Claims (7)
1. A dual margin DSP anti-reset deadlock circuit, comprising: the circuit comprises a main DSP circuit, a standby DSP circuit, a JTAG port circuit, a crystal oscillator circuit, a watchdog circuit and a CPLD circuit;
the method is characterized in that in the process of programming a program by a main DSP circuit, after a crystal oscillation signal CLK generated by a crystal oscillation circuit is connected to a CPLD circuit, a watchdog circuit outputs a RESET signal RESET to the CPLD circuit, a spare DSP circuit outputs a RESET signal RES to the CPLD circuit, a JTAG port circuit outputs a TCK signal to the CPLD circuit, and after the signals are logically processed in the CPLD circuit, the main DSP circuit outputs a main DSP RESET signal RST;
the CPLD circuit comprises a counter U1, an OR gate U2, a D trigger U3, an OR gate U4, an AND gate U5 and a NOT gate U6; wherein, TCK signal inputs CLK pin of the counter U1; four paths of output signals QA-QD of the counter U1 are connected with the input of the OR gate U2; the output of the OR gate U2 is connected with a D pin of a D trigger U3; a crystal oscillation signal CLK generated by the crystal oscillation circuit is connected with an ENA pin of a D trigger U3; the crystal oscillator circuit generates a crystal oscillator signal CLK which is connected with a zero clearing pin CLRN of the counter U1 after passing through the NOT gate U6; an output pin Q of the D trigger U3 is connected with an input pin of the OR gate U4; the RESET signal RES of the DSP circuit and the RESET signal RESET of the watchdog circuit are connected with the other input pin of the OR gate U4 after passing through the AND gate U5; or gate U4 outputs a reset signal RST.
2. The dual-margin DSP anti-reset deadlock circuit as claimed in claim 1, wherein when the JTAG port circuit is connected to the writer, the TCK signal of the JTAG port circuit is inputted to the counter U1, at this time, the CLK pin of the counter U1 has a clock signal, at least one of the QA-QD pins outputs a high level, and the high level is outputted to the D pin of the D flip-flop U3 after passing through the OR gate U4; the crystal oscillator circuit outputs a CLK signal, and the CLK signal enables a Q pin of the D trigger U3 to output a high level of a D pin; at this time, one input of the or gate U4 is at a high level, and no matter the reset signal REST of the watchdog circuit and the reset signal of the standby DSP circuit are at a high level or a low level, the output signal RST can only be at a high level, and the main DSP circuit cannot be reset, so that it is ensured that the main DSP circuit does not have a reset signal when programming the program, and the main DSP cannot be locked due to the reset signal when programming the program.
3. The dual margin DSP anti-reset deadlock circuit of claim 2, wherein the TCK signal of the JTAG port circuit is a 10MHZ clock signal.
4. The dual margin DSP anti-reset deadlock circuit of claim 3, wherein the crystal oscillator circuit outputs a 1MHZ CLK signal.
5. The double-margin DSP reset-prevention deadlock circuit as claimed in claim 1, wherein when the JTAG port circuit is not connected to the writer, the CLK pin of the counter U1 has no clock signal, the CLK signal output by the crystal oscillator circuit enables the counter U1 to count and clear, the QA-QD outputs a low level, the low level is output to the D pin of the D flip-flop U3 after passing through an OR gate U4, the crystal oscillator circuit outputs the CLK signal, and the CLK signal enables the Q pin of the D flip-flop U3 to output the low level of the D pin; the output signal RST of the or gate U4 is related to the states of the reset signal REST of the watchdog circuit and the reset signal RES of the standby DSP circuit, and the main DSP circuit can be reset.
6. The dual margin DSP anti-reset deadlock circuit of claim 5, wherein the crystal oscillator circuit outputs a 1MHZ CLK signal.
7. The dual-margin DSP anti-RESET lockout circuit of claim 6 wherein the main DSP circuit is RESET when either of the RESET and RES signals is active.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011192641.3A CN112433589B (en) | 2020-10-30 | 2020-10-30 | Double-margin DSP anti-reset locking circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011192641.3A CN112433589B (en) | 2020-10-30 | 2020-10-30 | Double-margin DSP anti-reset locking circuit |
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| CN112433589B true CN112433589B (en) | 2022-11-01 |
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2020
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