CN112416436A

CN112416436A - Information processing method, information processing apparatus, and electronic device

Info

Publication number: CN112416436A
Application number: CN202011403652.1A
Authority: CN
Inventors: 胡世文
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2020-12-02
Filing date: 2020-12-02
Publication date: 2021-02-26
Anticipated expiration: 2040-12-02
Also published as: CN112416436B

Abstract

An information processing method, an information processing apparatus, and an electronic device. The information processing method includes: acquiring reading information of a history reading request, wherein the history reading request indicates first storage information which is requested to be read by a processor core at a history moment, and the reading information comprises a history virtual address and a history physical address of the first storage information; predicting a predicted virtual address where the second storage information requested to be read by the processor core at a future moment is located according to the historical virtual address; judging whether the predicted virtual address and the historical virtual address are in the same virtual address page or not; and in response to the predicted virtual address being in the same virtual address page as the historical virtual address, determining a first predicted physical address from the historical virtual address, the historical physical address, and the predicted virtual address. The information processing method can improve timeliness of pre-extraction of information.

Description

Information processing method, information processing apparatus, and electronic device

Technical Field

Embodiments of the present disclosure relate to an information processing method, an information processing apparatus, and an electronic device.

Background

Instruction data prefetching is one of the key technologies to improve the performance of high-performance Central Processing Units (CPUs). The cache can only hold data that has been recently accessed by the CPU core. When reading data that has never been accessed or kicked out due to cache size limitations, the CPU core still needs to wait tens or even hundreds of clock cycles, causing performance loss. The instruction and data prefetching can prefetch the data to be used in advance according to the data access rule, so that the clock period of the CPU core waiting for the data is reduced, and the overall performance of the CPU is improved.

Disclosure of Invention

At least one embodiment of the present disclosure provides an information processing method, including: obtaining reading information of a history reading request, wherein the history reading request is sent by a processor core of a processor, the history reading request indicates that the processor core requests to read first storage information at a history moment, the reading information comprises a history virtual address and a history physical address of the first storage information, and the history physical address corresponds to the history virtual address; predicting a predicted virtual address where the second storage information requested to be read by the processor core at a future moment is located according to the historical virtual address; judging whether the predicted virtual address and the historical virtual address are in the same virtual address page or not; and responding to the fact that the predicted virtual address and the historical virtual address are in the same virtual address page, and determining a first predicted physical address according to the historical virtual address, the historical physical address and the predicted virtual address, wherein the first predicted physical address corresponds to the predicted virtual address.

For example, in an information processing method provided by an embodiment of the present disclosure, in response to a predicted virtual address being in the same virtual address page as a historical virtual address, determining a first predicted physical address according to the historical virtual address, the historical physical address, and the predicted virtual address includes: and in response to the predicted virtual address and the historical virtual address being in the same virtual address page, taking the sum of the offset between the predicted virtual address and the historical physical address as the first predicted physical address.

For example, in an information processing method provided by an embodiment of the present disclosure, a processor includes a multi-level cache including at least a first-level cache and a second-level cache, the first-level cache being one of the multi-level caches that is electrically connected to a processor core and directly transmits data to the processor core, the second-level cache being one of the multi-level caches that is electrically connected to the first-level cache and transmits data to the processor core through the first-level cache, and the method further includes: determining a target cache of the second storage information, wherein the target cache comprises a first-level cache or a second-level cache; judging whether the predicted virtual address and the historical virtual address are in the same virtual address page, including: and responding to the fact that the target cache is a second-level cache, and judging whether the predicted virtual address and the historical virtual address are in the same virtual address page.

For example, in an information processing method provided in an embodiment of the present disclosure, a processor further includes a prefetcher, and the method further includes: the prefetcher generates a first prefetching request according to the first predicted physical address, wherein the first prefetching request is used for requesting to store second storage information stored in the first predicted physical address into the second-level cache; the prefetcher sends a first prefetch request to a second-level cache; and the second-level cache responds to the first pre-fetching request and caches second storage information corresponding to the first predicted physical address into the second-level cache.

For example, in an information processing method provided by an embodiment of the present disclosure, caching, by a second-level cache, second storage information corresponding to a first predicted physical address in response to a first prefetch request, in the second-level cache, the caching method includes: the second-level cache responds to the first pre-fetching request and determines whether second storage information corresponding to the first predicted physical address is cached in the second-level cache or not; discarding the first prefetch request in response to the second level cache having cached second storage information corresponding to the first predicted physical address; and in response to the second-level cache not caching the second storage information corresponding to the first predicted physical address, the second-level cache extracts the second storage information corresponding to the first predicted physical address from a next-level cache or a memory and stores the second storage information in the second-level cache.

For example, in an information processing method provided by an embodiment of the present disclosure, a prefetcher sends a first prefetch request to a second-level cache, including: the prefetcher sends a first prefetch request to a prefetch queue to store the first prefetch request through the prefetch queue; and in response to the second level cache having free space, the prefetch queue sends a first prefetch request to the second level cache.

For example, in an information processing method provided by an embodiment of the present disclosure, a prefetcher sends a first prefetch request to a second-level cache, and the method further includes: in response to the memory space of the prefetch queue being full, the first prefetch request is discarded or other prefetch requests in the prefetch queue are replaced with the first prefetch request.

For example, in an information processing method provided in an embodiment of the present disclosure, a processor further includes an address translation pipeline, and the method further includes: and in response to the predicted virtual address not being in the same virtual address page as the historical virtual address, performing address translation on the predicted virtual address through an address translation pipeline to obtain a second predicted physical address.

For example, in an information processing method provided in an embodiment of the present disclosure, the information processing method further includes: the address translation pipeline generates a second pre-fetching request according to the second predicted physical address and sends the second pre-fetching request to the pre-fetching queue; the prefetch queue responds to the second prefetch request and sends the second prefetch request to the second-level cache; the second-level cache responds to the second prefetching request and determines whether second storage information corresponding to the second predicted physical address is cached in the second-level cache or not; discarding the second prefetch request in response to second storage information corresponding to the second predicted physical address having been cached in the second level cache; and in response to that the second storage information corresponding to the second predicted physical address is not cached in the second-level cache, the second-level cache extracts the second storage information corresponding to the second predicted physical address from a next-level cache or a memory and stores the second storage information in the second-level cache.

For example, in an information processing method provided by an embodiment of the present disclosure, in a case where a plurality of predicted virtual addresses are provided and the plurality of predicted virtual addresses are within the same virtual address page, in response to the predicted virtual addresses not being in the same virtual address page as a historical virtual address, address translation is performed on the predicted virtual addresses through an address translation pipeline to obtain second predicted physical addresses, the method includes: responding to the fact that the plurality of predicted virtual addresses are not in the same virtual address page with the historical virtual address, and performing address translation on the selected predicted virtual address in the plurality of predicted virtual addresses through an address translation pipeline to obtain a second predicted physical address; and determining a second predicted physical address corresponding to the other predicted virtual address except the selected predicted virtual address in the plurality of predicted virtual addresses according to the second predicted physical address corresponding to the selected predicted virtual address.

For example, in the information processing method provided by an embodiment of the present disclosure, the selected predicted virtual address is a predicted virtual address that is first accessed by the processor core among the plurality of predicted virtual addresses predicted by the prefetcher.

For example, in the information processing method provided in an embodiment of the present disclosure, the prefetch queue and the address translation pipeline share the same interface of the address cache, or the prefetch queue and the address translation pipeline occupy different interfaces in the address cache respectively.

For example, in an information processing method provided in an embodiment of the present disclosure, the information processing method further includes: in response to the target cache being the first level cache, sending a third prefetch request to the address translation pipeline such that the third prefetch request reaches the address translation pipeline, the third prefetch request including the predicted virtual address; the address translation pipeline translates the predicted virtual address to a third predicted physical address in response to the third prefetch request and generates a fourth prefetch request from the third predicted physical address; determining whether second storage information corresponding to the third predicted physical address is cached in the first-level cache; discarding the fourth prefetch request in response to the second storage information corresponding to the third predicted physical address having been cached in the first level cache; in response to that second storage information corresponding to the third predicted physical address is not cached in the first-level cache, sending a fourth prefetch request to the address cache, so that the address cache sends the fourth prefetch request to the second-level cache; the second level cache fetches second storage information corresponding to the third predicted physical address in response to a fourth prefetch request from the address cache and sends the fetched second storage information to the address cache, such that the address cache sends the fetched second storage information to the first level cache.

For example, in an information processing method provided in an embodiment of the present disclosure, determining whether a predicted virtual address and a historical virtual address are in the same virtual address page includes: determining the size of a page of a virtual address page where the historical virtual address is located; and judging whether the predicted virtual address and the historical virtual address are in the same virtual address page or not based on the size of the page of the virtual address page.

At least one embodiment of the present disclosure also provides an information processing apparatus including: an acquisition unit configured to acquire read information of a history read request, the history read request being transmitted by a processor core of a processor, the history read request indicating that the processor core requests to read first storage information at a history time, the read information including a history virtual address and a history physical address of the first storage information, the history physical address corresponding to the history virtual address; the prediction unit is configured to predict a prediction virtual address where the second storage information requested to be read by the processor core at a future moment is located according to the historical virtual address; a judging unit configured to judge whether the predicted virtual address and the historical virtual address are in the same virtual address page; and an address determination unit configured to determine a first predicted physical address from the historical virtual address, the historical physical address, and the predicted virtual address in response to the predicted virtual address being in the same virtual address page as the historical virtual address, the first predicted physical address corresponding to the predicted virtual address.

At least one embodiment of the present disclosure also provides an electronic device including: the processor is used for realizing the instructions of the information processing method provided by any embodiment of the disclosure.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.

FIG. 1 shows a schematic flow diagram of a CPU core reading instructions or data;

FIG. 2 shows a schematic flow diagram for prefetching data information using a prefetcher;

fig. 3 is a flowchart illustrating an information processing method according to at least one embodiment of the disclosure;

fig. 4A illustrates a flow chart of another information processing method provided by at least one embodiment of the present disclosure;

fig. 4B illustrates a schematic flow chart of an information processing method provided by at least one embodiment of the present disclosure;

fig. 5 is a flowchart illustrating another information processing method according to at least one embodiment of the present disclosure;

fig. 6 shows a flowchart of another information processing method provided by at least one embodiment of the present disclosure;

fig. 7 shows a schematic block diagram of an information processing apparatus provided in at least one embodiment of the present disclosure;

fig. 8 is a schematic block diagram of an electronic device provided by some embodiments of the present disclosure; and

fig. 9 is a schematic block diagram of another electronic device provided by some embodiments of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

In a general CPU architecture, instructions and data of a program are stored in a memory, and the operating frequency of a CPU core is much higher than that of the memory. Therefore, acquiring data or instructions from the memory requires hundreds of CPU core clocks, which often causes the CPU core to idle due to the inability to continue running the relevant instructions, resulting in performance loss. Therefore, modern high-performance CPU cores all include a multi-level cache architecture to store recently accessed data, and meanwhile, a prefetcher is used to discover the access rule of CPU data to prefetch the data and instructions to be accessed into a cache in advance. If the prefetched instruction is an instruction, it is called an instruction prefetcher, and if the prefetched instruction is data, it is called a data prefetcher. An L1 (first level) cache prefetcher may prefetch instructions or data into a first level cache. However, due to the limited cache capacity of L1, aggressive L1 cache prefetching replaces otherwise useful instructions or data in the L1 cache, resulting in overall performance loss. To address this, since the capacity of the L2 (second level) cache is much larger than the capacity of the L1 cache, the L2 cache prefetcher or the L1/L2 composite prefetcher may choose to prefetch these instructions or data into the L2 cache before prefetching into the L1 cache. The L2 cache prefetcher may prefetch instructions or data into the second level cache, and the L1/L2 synthetic prefetcher may choose to prefetch these instructions or data into the L2 cache first or into the L1 cache.

For example, L1 prefetchers may include an L1I (L1 Instructions ) prefetcher and an L1D (L1 Data ) prefetcher. An L1I prefetcher is used to prefetch instructions and an L1D prefetcher is used to prefetch data. It is to be understood that the prefetchers herein may be either L1I prefetchers or L1D prefetchers.

In addition, modern operating systems often support multiple processes running simultaneously. To simplify multi-process management and enhance security, applications use a complete virtual address, for example, 32-bit applications have at most 2^32 ^ 4GB of virtual address space available. The virtual address space is mapped into a plurality of memory pages, each having its own physical memory address. For example, a contiguous segment of virtual addresses is mapped to a memory page, which is referred to as a virtual address page in this disclosure.

When a program accesses instructions and data, the virtual addresses of the programs must be translated into physical addresses, whether the access of the program is legal or not is detected, and then the program goes to a memory or a cache to obtain corresponding data to be transmitted to a CPU core. The process of converting a virtual address to a physical address is called address translation. The mapping of virtual addresses to physical addresses is stored in tables in memory, and accessing these tables in memory also requires hundreds of clocks. To reduce these memory accesses, the CPU core uses multiple levels of cache to hold the most recently used mappings, and these specific caches are called Table Lookaside Buffers (TLBs).

Fig. 1 shows a schematic flow diagram of a CPU core reading instructions or data.

As shown in fig. 1, the CPU core reading the instruction or data includes steps S110 to S180.

Step S110: the CPU core gives a virtual address of the instruction or data that needs to be read.

Step S120: the virtual address is translated to a physical address using an address translation pipeline and a determination is made as to whether the first level cache caches instructions or data corresponding to the physical address. An address translation pipeline may be included in the CPU that translates virtual addresses to physical addresses. The address translation pipeline may include, for example, logic circuitry to perform operations in accordance with arithmetic logic, which may translate virtual addresses into physical addresses in accordance with a series of operations performed by the arithmetic logic.

For example, the address translation pipeline may translate a virtual address to a physical address by accessing a virtual address to physical address mapping cached by the TLB.

For example, the address translation pipeline may send a request to the first level cache to obtain a plurality of tags in the first level cache, where each tag in the plurality of tags may be a hash of a physical address cached in the first level cache. The address translation pipeline may then hash the physical address to obtain a hash value and compare the hash value to the plurality of tags retrieved from the first level cache. If the hash value is contained in the plurality of tags, it indicates that the instruction or data corresponding to the physical address is cached in the first-level cache. If the hash value is not contained in the tags, it indicates that the first-level cache does not cache the instruction or data corresponding to the physical address.

If the instruction or data corresponding to the physical address is cached in the first-level cache, step S130 and step S140 are performed. If the first-level cache does not cache the instruction or data corresponding to the physical address, steps S150 to S180 are performed.

Step S130: a read request is sent to the first level cache.

Step S140: and the first-level cache responds to the read request, fetches the instruction or the data corresponding to the physical address from the first-level cache, and sends the instruction or the data corresponding to the physical address to the CPU core so as to respond to the read request.

Step S150: and applying for a storage space from the address cache, wherein the storage space is used for storing relevant information of the read request. The Address cache may be, for example, a Missing Address Buffer (abbreviated as MAB) or a Missing Status Handling Register (abbreviated as MSHR).

The MAB or MSHR may be used to cache information about a read request in the event that the first level cache does not cache the read request or prefetch the instructions or data requested to be read by the request. That is, when a request is made to the next-level cache in the case that the instruction or data requested by a read request or prefetch request is not in the first-level cache, the information related to the read request or prefetch request may be stored in the MAB until the next-level cache returns the data information of the read request or prefetch request.

For example, in step S150, an entry of MAB may be applied to the MAB, so that the MAB allocates a storage space, and the read request is sent to the MAB.

Step S160: the MAB sends a read request to the second level cache.

Step S170: and the second-level cache acquires the instruction or the data corresponding to the physical address and returns the instruction or the data corresponding to the physical address to the MAB.

Step S180: the MAB sends the instruction or data corresponding to the physical address to the first-level cache, so that the instruction or data corresponding to the physical address reaches the first-level cache, so that the first-level cache performs step S40, that is, sends the instruction or data corresponding to the physical address to the CPU core.

Fig. 2 shows a schematic flow diagram for prefetching data information using a prefetcher. The prefetcher may be, for example, an L1/L2 synthetic prefetcher.

As shown in FIG. 2, synthesizing prefetcher prefetch data information using L1/L2 may include steps S210-S240, steps S251-S254, steps S261-S262, and steps S270-S280.

Step S210: the CPU core gives a virtual address of the instruction or data that needs to be read.

Step S220: translating the virtual address into a physical address using an address translation pipeline, and sending a read request including the physical address to the first level cache and the L1/L2 synthetic prefetcher, causing the L1/L2 synthetic prefetcher to train the virtual address as a historical virtual address and using the historical virtual address to obtain a predicted virtual address, and causing the first level cache to return an instruction or data corresponding to the physical address to the CPU core in response to the read request.

Step S230: the L1/L2 synthetic prefetcher trains all or part of the historical virtual addresses to predict the predicted virtual address of instructions or data that the CPU core will fetch in the future.

Step S240: and translating the address of the predicted virtual address to obtain a predicted physical address, generating a prefetch request according to the predicted physical address, and determining whether the first-level cache caches the instruction or data corresponding to the predicted physical address. This step S240 is similar to step S120 described above with reference to fig. 1, and is not described again here.

In the case where the instruction or data corresponding to the predicted physical address is cached in the first level cache, the prefetch request is discarded.

In the case that the first-level cache does not cache the instruction or data corresponding to the physical address, if the prefetch request is an L1 prefetch request, steps S251 to S254 are performed for prefetching the instruction or data into the L1 cache. If the prefetch request is an L2 prefetch request, steps S261-S263 are performed for prefetching instructions or data into the L2 cache.

Step S251: apply for a MAB entry to the address cache MAB, cause the MAB to allocate the MAB entry, and send the aforementioned L1 prefetch request to the MAB.

Step S252: the MAB sends an L1 prefetch request to the second level cache.

Step S253: and the second-level cache acquires the instruction or the data corresponding to the predicted physical address and returns the instruction or the data corresponding to the predicted physical address to the MAB. The second level cache, for example, may obtain the instruction or data corresponding to the predicted physical address from the next level cache or itself. The second level cache may perform steps S270 and S280 to obtain the instruction or data corresponding to the predicted physical address from a next level cache, such as a last level cache, for example.

Step S254: and the MAB sends the instruction or the data corresponding to the physical address to the first-level cache, so that the instruction or the data corresponding to the predicted physical address is cached in the first-level cache.

Step S261: the L2 prefetch request is sent to the prefetch queue to send an L2 prefetch request to the second level cache by the prefetch queue.

Step S262: the prefetch queue sends an L2 prefetch request to the second level cache.

Step S263: the second level cache determines whether the instruction or data corresponding to the predicted physical address in the L2 prefetch request is already cached in itself. If cached in itself, the L2 prefetch request is discarded. If not, step S270 and step S280 are executed, so that the instruction or data corresponding to the predicted physical address in the L2 prefetch request is cached in the second-level cache.

Step S270: a prefetch request is sent to a next level cache, e.g., a last level cache, to retrieve instructions or data corresponding to the predicted physical address from the next level cache.

Step S280: and the last-level cache sends the acquired instruction or data to the second-level cache.

As shown in fig. 1 and 2, in the high-performance CPU, a prefetch process (hereinafter referred to as "prefetch") of an instruction or data corresponding to a predicted virtual address predicted by the prefetcher shares an address translation pipeline with a normal read process (hereinafter referred to as "normal read") of an instruction or data corresponding to a virtual address issued by the CPU core. In a high frequency, high performance CPU, the address translation pipeline may be multi-staged. Since prefetching has a lower priority than normal reads, a prefetch may need to wait multiple clock cycles to enter the address translation pipeline, and address translation itself may need multiple pipeline clock cycles, such that a prefetch requires multiple clocks to be issued to the next level of cache. Prefetching is time-efficient, corresponding CPU core accesses occur quickly, and latency caused by address translation often causes the prefetched data to arrive at the first-level cache too late, thereby causing prefetching invalidation.

At least one embodiment of the disclosure provides an information processing method, an information processing device and an electronic device. The information processing method can determine the predicted physical address according to the historical physical address, and the predicted physical address does not need to be obtained through an address translation pipeline, so that the time delay of address translation for prefetching can be reduced, and the prefetching timeliness is improved.

Fig. 3 shows a flowchart of an information processing method according to at least one embodiment of the present disclosure. As shown in fig. 3, the information processing method includes steps S310 to S340.

Step S310: reading information of the history reading request is acquired. The history read request is sent by a processor core of the processor, the history read request indicates first storage information requested to be read by the processor core at the history time, the read information includes a history virtual address and a history physical address of the first storage information, and the history physical address corresponds to the history virtual address.

Step S320: and predicting the predicted virtual address where the second storage information requested to be read by the processor core at the future time is located according to the historical virtual address.

Step S330: and judging whether the predicted virtual address and the historical virtual address are in the same virtual address page.

Step S340: and in response to the predicted virtual address being in the same virtual address page as the historical virtual address, determining a first predicted physical address from the historical virtual address, the historical physical address, and the predicted virtual address. The first predicted physical address corresponds to the predicted virtual address.

Under the condition that the predicted virtual address and the historical virtual address are in the same virtual address page, the information processing method can determine the first predicted physical address corresponding to the predicted virtual address according to the historical physical address corresponding to the historical virtual address, so that address translation of the predicted virtual address is not needed, delay caused by address translation is at least partially avoided, and prefetching effectiveness is improved. In addition, because the address translation pipeline is frequently required to be shared with the prefetching for normal instruction and data reading, the information processing method reduces address translation for prefetching, reduces address reading time delay for normal reading, and reduces power consumption required for address translation prefetching.

With step S310, the history read request may be, for example, a read request including a history virtual address issued by the CPU core at a history time. The read information of the history read request may include, for example, a history virtual address and a history physical address. The historical physical address may be obtained, for example, by address translation of a historical virtual address.

For example, it may be that the CPU core issues each read request to an address translation pipeline, which in turn processes each read request to translate the virtual address in each read request to a physical address. The address translation pipeline then sends the prefetcher the virtual address, physical address, and other information corresponding to each read request. The read requests serve as historical read requests, virtual addresses corresponding to the read requests serve as historical virtual addresses, and physical addresses obtained through translation of the historical virtual addresses serve as historical physical addresses, so that the prefetcher can be trained by the historical virtual addresses. In step S310, read information from the address translation pipeline may be received, for example, by the prefetcher. The prefetcher may be an L1 cache prefetcher, an L2 cache prefetcher, an L1/L2 combined prefetcher, or other prefetchers, and may be a prefetch-instruction prefetcher for prefetching instructions or a data prefetcher for prefetching data.

The first storage information may be, for example, an instruction or data that the CPU core requests to read at a history time.

In step S320, for example, the prefetcher may train the historical virtual address to obtain a rule of the historical virtual address, so as to predict a predicted virtual address to be accessed by the CPU core according to the rule, where the predicted physical address corresponding to the predicted virtual address stores the second storage information.

For example, the historical virtual addresses include 0X 00000000, 0X 00000002, 0X 00000004, 0X 00000006, then the prefetcher may predict that the predicted virtual address to which the CPU core will be accessing is 0X 00000008.

For prefetchers, using historical virtual address training to obtain access laws for CPU cores has the following benefits over using historical physical addresses. 1. The virtual address may be used by the prefetcher without undergoing address translation. 2. Training the prefetcher with virtual addresses may discover read regularity across memory pages. However, two virtual address pages with continuous virtual addresses may be allocated as discontinuous physical addresses, and the prefetcher trained by using the physical addresses can only detect the reading rule in one memory page, so that the accuracy and the effectiveness of the rule found by the prefetcher are limited. 3. Training the prefetcher with virtual addresses may generate prefetches across memory pages. A prefetcher trained using physical addresses cannot generate a physical address of an untrained memory page.

For step S330, for example, the size of the page of the virtual address page where the historical virtual address is located may be determined, and based on the size of the page of the virtual address page, it may be determined whether the predicted virtual address and the historical virtual address are in the same virtual address page.

For example, the address range of each virtual address page may be determined according to the page size of the virtual address page, so as to determine whether the historical virtual address and the predicted virtual address are in the same address range. If the predicted virtual address and the historical virtual address are in the same address range, the predicted virtual address and the historical virtual address are judged to be in the same virtual address page.

For example, the virtual addresses are numbered from 0, the number of reference bits to shift right may be determined according to the page size of the virtual address page, so that the predicted virtual address is shifted right and the historical virtual address is shifted right according to the number of reference bits to shift right. If the two values obtained after the right shift of the predicted virtual address and the right shift of the historical virtual address are the same, the predicted virtual address and the historical virtual address are in the same virtual address page.

For example, the virtual address is numbered from 0, and the page size of the virtual address page is 4KB, since the 12 th power of 2 is equal to 4KB, it is possible to compare whether the values of the predicted virtual address right-shifted by 12 bits and the historical virtual address right-shifted by 12 bits are equal to determine whether the predicted virtual address and the historical virtual address are in the same virtual address page. If the values obtained by right shifting the predicted virtual address by 12 bits and the historical virtual address by 12 bits are equal, it can be determined that the predicted virtual address and the historical virtual address are in the same virtual address page.

It is to be understood that although the page size of the virtual address page is 4KB in the above embodiments, the present disclosure is not limited to a virtual address page of 4 KB. If one system can support the page sizes of a plurality of virtual address pages, the sizes of the corresponding pages can be sent to the prefetcher when the prefetcher is trained, so that the prefetcher judges whether the historical virtual address and the predicted virtual address are in the same virtual address page or not according to the page sizes, the percentage of prefetching requests which do not need address translation can be further increased, and the application range and the performance of the information processing method provided by the disclosure are improved.

For step S340, if the predicted virtual address is in the same virtual address page as the historical virtual address, the first predicted physical address may be determined from the historical virtual address, the historical physical address, and the predicted virtual address.

In some embodiments of the present disclosure, for example, a sum of the historical physical address and an offset between the predicted virtual address and the historical virtual address may be taken as the first predicted physical address. That is, the first predicted physical address can be calculated according to the following formula.

PPA＝HPA+(PVA－HVA)

Where PPA represents the first predicted physical address, HPA represents the historical physical address, PVA represents the predicted virtual address, and HVA represents the historical virtual address.

The first predicted physical address of the predicted virtual address can be calculated very simply using the above formula, thereby at least partially omitting the address translation process.

In some embodiments of the present disclosure, a processor may include a multi-level cache including at least a first level cache and a second level cache. The first level cache may be a cache that is electrically connected to the CPU core and may transmit data directly to the CPU core. The second-level cache is for example a cache electrically connected with the first-level cache and transmitting data with the processor core through the first-level cache. For example, the processor includes a first level cache, a second level cache, … …, and a last level cache, and the storage capacities of the first level cache, the second level cache, … …, and the last level cache may sequentially increase, the reading speed sequentially decreases, and the distance to the CPU core also sequentially increases. For example, the first level cache may be located closest to the CPU core, have minimal storage capacity, and have the fastest read speed.

In some embodiments of the present disclosure, the information processing method may further include determining a target cache of the second storage information based on the foregoing embodiments, where the target cache includes a first-level cache or a second-level cache, and then step S330 may be to determine whether the predicted virtual address and the historical virtual address are in the same virtual address page in response to the target cache being the second-level cache. That is, if the target cache is the second level cache, it is determined whether the predicted virtual address is in the same virtual address page as the historical virtual address, and the first predicted physical address storing the second storage information is calculated according to the method provided in step S340.

In still other embodiments of the present disclosure, if the target cache is a first level cache, a third predicted physical address to store the second storage information may be obtained by the address translation pipeline, and the second storage information may be retrieved from the third predicted physical address and cached in the first level cache. Fig. 6 below shows an implementation manner of the embodiment, and please refer to fig. 6 and corresponding description parts, which are not described herein again.

For example, if the prefetcher is an L1/L2 synthesized prefetcher, then the L1/L2 synthesized prefetcher may be a prefetch for which the target cache is a second level cache, where the first predicted physical address for storing the second storage information is calculated according to the method provided in step S340, and for which the target cache is a first level cache, where the third predicted physical address for storing the second storage information may be obtained through the address translation pipeline.

In other embodiments of the present disclosure, the first predicted physical address for storing the second storage information may be calculated according to the method provided in step S340, regardless of whether the target cache is a first level cache or a second level cache.

For example, in an embodiment where the target cache is a first-level cache and the first predicted physical address storing the second storage information is calculated according to the method provided in step S340, the information processing method described above with reference to fig. 3 may further include: the prefetcher may generate a prefetch request based on the first predicted physical address and send the prefetch request such that the prefetch request reaches the MAB, the MAB sending the prefetch request to the second level cache, the second level cache determining whether second storage information corresponding to the first predicted physical address has been cached in the first level cache in response to the prefetch request. In response to the first level cache having cached second storage information corresponding to the first predicted physical address, the second level cache notifies the address cache to discard the first prefetch request. In response to the first-level cache not caching the second storage information corresponding to the first predicted physical address, the second-level cache extracts the second storage information corresponding to the first predicted physical address and sends the extracted second storage information to the MAB, so that the MAB sends the extracted second storage information to the first-level cache to cause the second storage information to be cached in the first-level cache.

In the above embodiment, the second-level cache may be, for example, an Inclusive cache (Inclusive cache), so that whether the second storage information corresponding to the first predicted physical address is already cached in the first-level cache may be determined according to the state information in the second-level cache. The second-level cache is a cache, that is, the second-level storage information stored in the second-level cache at least includes the first-level storage information stored in the first-level cache, and the second-level cache further includes state information. For example, the first-level storage information included in the first-level cache is storage information a and storage information B, and if the second-level cache is an inclusive cache, the second-level storage information at least includes storage information a and storage information B. The second-level storage information may further include, for example, storage information C, storage information D, and the like, on the basis of storage information a and storage information B.

The state information indicates whether the second-level storage information is located in the first-level cache or not, and the second storage information is located in the multi-level cache or the memory. For example, if the second-level storage information includes storage information a, storage information B, and storage information C, the second-level cache includes respective status information of storage information a, storage information B, and storage information C, which may indicate whether storage information a, storage information B, and storage information C are cached in the first-level cache.

In some embodiments of the present disclosure, the second level cache may include, for example, logic circuitry that may retrieve state information in the second level cache and determine whether the state information of the second stored information or the state information of the first predicted physical address is equal to a reference value. The reference value may be set by a person skilled in the art according to actual requirements, and may be, for example, 0 or 1. Step S355 is illustrated by taking the example that the reference value is 1 indicating that the second-level storage information is located in the first-level cache. For example, the logic may determine the status information of the second storage information from the second-level cache, and then the logic may compare the status information with a reference value of 1, determine that the second storage information is already cached in the first-level cache if the status information is equal to 1, and determine that the second storage information is not cached in the first-level cache if the status information is not equal to 1.

In some embodiments of the present disclosure, the second storage information may be data or instructions. The second stored information may be stored in any one of the plurality of levels of cache memory of the processor, and the second stored information may also be stored in the memory. For example, if the second storage information is stored in the second-level cache, the second storage information is extracted from the second-level cache and cached in the first-level cache. And if the second storage information is stored in the third-level cache, the second-level cache extracts the second storage information from the third-level cache and caches the second storage information to the first-level cache.

In some embodiments of the present disclosure, if the target cache is a second-level cache and the processor further includes a prefetcher, the information processing method may further include the steps described below with reference to fig. 4A based on the foregoing embodiments.

Fig. 4A illustrates a flowchart of another information processing method provided in at least one embodiment of the present disclosure.

As shown in fig. 4A, the information processing method may further include steps S350 to S370 on the basis of the foregoing embodiment.

Step S350: the prefetcher generates a first prefetch request based on the first predicted physical address. The first prefetch request requests storage of second storage information stored in the first predicted physical address to the second-level cache.

The prefetcher, which may be, for example, an L2 cache prefetcher or an L1/L2 composite prefetcher, is used for caching prefetched data information into an L2 cache.

Step S360: the prefetcher sends a first prefetch request to a second level cache.

Step S370: the second-level cache caches second storage information corresponding to the first predicted physical address to the second-level cache in response to the first prefetch request.

For example, the second level cache determines whether second storage information corresponding to the first predicted physical address has been cached in the second level cache in response to the first prefetch request. The first prefetch request is discarded in response to the second level cache having cached second storage information corresponding to the first predicted physical address. And in response to that the second-level cache does not cache the second storage information corresponding to the first predicted physical address, the second-level cache extracts the second storage information corresponding to the first predicted physical address from a next-level cache or a memory and stores the second storage information in the second-level cache.

In some embodiments of the present disclosure, the sending, by the prefetcher, the first prefetch request to the second level cache in step S360 may include: the prefetcher sends a first prefetch request to a prefetch queue to store the first prefetch request through the prefetch queue, and the prefetch queue sends the first prefetch request to a second level cache in response to the second level cache having free space.

The information processing method adds a prefetch queue between the prefetcher and the second-level cache. The prefetch queue may cache prefetches that do not require address translation and may send those prefetches past when the second level cache may receive them, thereby at least partially avoiding prefetch loss due to the second level cache being full of storage space.

In some embodiments of the present disclosure, the size of the prefetch queue may be set by one skilled in the art based on the actual circumstances.

In some embodiments of the present disclosure, the prefetcher sending a first prefetch request to a second level cache further comprises: in response to the memory space of the prefetch queue being full, the first prefetch request is discarded or other prefetch requests in the prefetch queue are replaced with the first prefetch request.

For example, at least one other prefetch request queued at the end of the prefetch queue may be replaced with the first prefetch request.

In other embodiments of the present disclosure, the prefetcher may also send the first prefetch request directly to the second level cache instead of sending the first prefetch request through the prefetch queue to the second level cache.

Fig. 4B shows a schematic flowchart of an information processing method provided by at least one embodiment of the present disclosure. The information processing method described above with reference to fig. 3 and 4A is explained below with reference to fig. 4B.

As shown in fig. 4B, the information processing method may include the following operations.

Step S410: the CPU core gives a virtual address of the instruction or data that needs to be read. The virtual address is, for example, the historical virtual address.

Step S420: the virtual address is translated to a physical address using an address translation pipeline, and a read request including the physical address is sent to a prefetcher, such that the prefetcher trains the virtual address as a historical virtual address and uses the historical virtual address to obtain a predicted virtual address. This physical address may be used as the historical physical address described previously.

Steps S410 and S420 may be a process of acquiring read information of a history read request for the prefetcher. For example, the method may be performed according to step S310 described in fig. 3 above, and will not be described herein again.

Step S430: the prefetcher trains all or a portion of historical physical addresses to predict a predicted virtual address of an instruction or data that the CPU core will fetch at a future time. For example, the method may be performed according to step S320 described in fig. 3 above, and will not be described herein again.

Step S440: and judging whether the predicted virtual address and the historical virtual address are in the same virtual address page. For example, the method can be performed according to step S330 described in fig. 3 above, and will not be described herein again.

Step S450: and in response to the predicted virtual address being in the same virtual address page as the historical virtual address, determining a first predicted physical address from the historical virtual address, the historical physical address, and the predicted virtual address. For example, the method can be performed according to step S340 described in fig. 3 above, and will not be described herein again.

Step S460: the prefetcher generates a first prefetch request based on the first predicted physical address and sends the first prefetch request to a prefetch queue. For example, step S350 described above in fig. 4A may be performed, and will not be described herein again.

Step S470: the prefetch queue sends a first prefetch request to the second level cache. For example, step S360 described in fig. 4A above may be performed, and will not be described herein again.

Step S480: the second-level cache responds to the first prefetching request, and caches second storage information corresponding to the first predicted physical address in the second-level cache in response to the first prefetching request. Step S370 described above with respect to fig. 4A may be performed, for example. The second-level cache caches second storage information corresponding to the first predicted physical address to the second-level cache in response to the first prefetch request, which may include, for example, determining whether second storage information corresponding to the first predicted physical address is already cached in the second-level cache, and discarding the first prefetch request by the second-level cache if the second-level cache determines that the second storage information is already cached by the second-level cache. Alternatively, if the second-level cache determines that the second storage information is not cached by itself, the second-level cache may retrieve the second storage information from the next-level cache or the memory to store the second storage information in itself. For example, the second level cache may extract the second storage information from the last level cache.

Fig. 5 shows a flowchart of another information processing method provided in at least one embodiment of the present disclosure.

As shown in fig. 5, the information processing method may further include step S510 on the basis of the method described in the foregoing fig. 3.

Step S510: and in response to the predicted virtual address not being in the same virtual address page as the historical virtual address, performing address translation on the predicted virtual address through an address translation pipeline to obtain a second predicted physical address.

As shown in fig. 4B, for example, in the case where the prefetcher determines that the predicted virtual address is not in the same virtual address page as the historical virtual address, the prefetcher may perform step S401. Step S401 may include, for example, sending the predicted virtual address to an address translation pipeline such that the address translation pipeline translates the predicted virtual address.

In some embodiments of the present disclosure, sending the predicted virtual address to the address translation pipeline may be, for example, the prefetcher generating a prefetch request containing the predicted virtual address from the predicted virtual address and sending the prefetch request containing the predicted virtual address to the address translation pipeline for address translation of the predicted virtual address by the address translation pipeline.

In other embodiments of the present disclosure, as shown in fig. 5, the information processing method may further include steps S520 to S550.

Step S520: the address translation pipeline generates a second prefetch request based on the second predicted physical address and sends the second prefetch request to the prefetch queue.

For example, the address translation pipeline is translating the predicted virtual address to a second predicted physical address, generating a second prefetch request based on the second predicted physical address, and sending the second prefetch request to the prefetch queue.

Step S530: the prefetch queue sends a second prefetch request to the second level cache in response to the second prefetch request.

The second level cache determines whether second storage information corresponding to the second predicted physical address has been cached in the second level cache in response to the second prefetch request.

Step S540: the second prefetch request is discarded in response to second storage information corresponding to the second predicted physical address having been cached in the second level cache.

Step S550: and in response to that the second storage information corresponding to the second predicted physical address is not cached in the second-level cache, the second-level cache extracts the second storage information corresponding to the second predicted physical address from a next-level cache or a memory and stores the second storage information in the second-level cache.

The following describes the above with reference to steps S520 to S550 in fig. 5 with reference to fig. 4B.

As shown in fig. 4B, for example, in the case where the prefetcher determines that the predicted virtual address is not in the same virtual address page as the historical virtual address, the prefetcher performs step S401 of sending a prefetch request containing the predicted virtual address to the address translation pipeline so that the address translation pipeline translates the predicted virtual address.

The address translation pipeline, in response to receiving a prefetch request from the prefetcher containing a predicted virtual address, may perform step S402 of translating the predicted virtual address to a second predicted physical address, generating a second prefetch request based on the second predicted physical address, and sending the second prefetch request to the prefetch queue.

Next, the prefetch queue performs step S470 in response to the second prefetch request. Step S470 may be the prefetch queue sending a second prefetch request to the second level cache.

The second level cache determines whether second storage information corresponding to the second predicted physical address has been cached in the second level cache in response to the second prefetch request. The second prefetch request is discarded in response to second storage information corresponding to the second predicted physical address having been cached in the second level cache. And in response to that the second storage information corresponding to the second predicted physical address is not cached in the second-level cache, the second-level cache extracts the second storage information corresponding to the second predicted physical address from a next-level cache or a memory and stores the second storage information in the second-level cache. For example, step S540 or step S550 described above with reference to fig. 5 may be performed, which is not described herein again.

In some embodiments of the present disclosure, in a case where the predicted virtual address is a plurality and the plurality of predicted virtual addresses are within the same virtual address page, in response to the predicted virtual address not being in the same virtual address page as the historical virtual address, address translating the predicted virtual address to obtain the second predicted physical address, includes: responding to the fact that the plurality of predicted virtual addresses are not in the same virtual address page with the historical virtual address, conducting address translation on the selected predicted virtual address in the plurality of predicted virtual addresses to obtain a second predicted physical address, and determining second predicted physical addresses corresponding to other predicted virtual addresses except the selected predicted virtual address in the plurality of predicted virtual addresses according to the second predicted physical address corresponding to the selected predicted virtual address.

If the predicted virtual addresses corresponding to multiple consecutive prefetches are all in the same virtual address page but are not in the same page as any historical virtual address, then address translation may be performed for only the first prefetch in the multiple consecutive prefetches and the requested predicted physical address may be sent to the prefetcher so that a subsequent prefetch accessing the virtual address page need not perform address translation again.

For example, the prefetcher predicts that the predicted virtual addresses to be read by the CPU core in the future include 0X 00000008, 0X 0000000B and 0X 0000000D, and may determine that 0X 00000008, 0X 0000000B and 0X 0000000D are in the same virtual address page, then one of the predicted virtual addresses may be selected from 0X 00000008, 0X 0000000B and 0X 0000000D for address translation to obtain a second predicted physical address of the selected predicted virtual address. For example, the selected predicted virtual address is 0X 00000008, and 0X 00000008 is address-translated by the address translation pipeline to obtain a physical address corresponding to 0X 00000008. Then, the physical addresses corresponding to 0X 0000000B and 0X 0000000D are calculated according to the physical address corresponding to 0X 00000008. For example, an offset between the target predicted virtual address and the selected predicted virtual address may be calculated, and the sum of the offset and the selected predicted physical address may be used as the physical address corresponding to the target predicted virtual address. The above calculation method will be described by taking an example in which the target predicted virtual address is 0X 0000000B and the selected predicted virtual address is 0X 00000008. The physical address of 0X 0000000B is equal to the offset between 0X 0000000B and 0X 00000008 plus the corresponding physical address of 0X 00000008.

In some embodiments of the present disclosure, the selected predicted virtual address may be any one of the plurality of predicted virtual addresses. In other embodiments of the present disclosure, the selected predicted virtual address is the predicted virtual address that is first accessed by the processor core from among the plurality of predicted virtual addresses predicted by the prefetcher, or the predicted virtual address that is first predicted by the prefetcher from among the plurality of predicted virtual addresses.

Fig. 6 shows a flowchart of another information processing method provided in at least one embodiment of the present disclosure.

As shown in fig. 6, the information processing method may further include steps S610 to S660 based on the foregoing embodiment.

Step S610: in response to the target cache being the first level cache, a third prefetch request is sent to the address translation pipeline such that the third prefetch request reaches the address translation pipeline, the third prefetch request including the predicted virtual address.

For example, the prefetcher determines that the target cache is a first level cache and may send a third prefetch request to the address translation pipeline. The third prefetch request includes a predicted virtual address.

Step S620: the address translation pipeline translates the predicted virtual address to a third predicted physical address in response to the third prefetch request and generates a fourth prefetch request based on the third predicted physical address.

The fourth prefetch request is a prefetch request that includes the third predicted physical address.

Step S630: and determining whether second storage information corresponding to the third predicted physical address is cached in the first-level cache.

For example, the address translation pipeline may determine whether second store information corresponding to the third predicted physical address is already cached in the first level cache.

Step S640: and discarding the fourth prefetch request in response to the second storage information corresponding to the third predicted physical address having been cached in the first level cache.

The address translation pipeline may directly discard the fourth prefetch request if the second store information corresponding to the third predicted physical address has been cached in the first level cache.

Step S650: and in response to that the second storage information corresponding to the third predicted physical address is not cached in the first-level cache, sending a fourth prefetch request to the address cache, so that the address cache sends the fourth prefetch request to the second-level cache.

For example, if the second store information corresponding to the third predicted physical address is not cached in the first level cache, the address translation pipeline may send a fourth prefetch request to the MAB, such that the MAB sends the fourth prefetch request to the second cache.

Step S660: the second level cache fetches second storage information corresponding to the third predicted physical address in response to a fourth prefetch request from the address cache and sends the fetched second storage information to the address cache, such that the address cache sends the fetched second storage information to the first level cache.

For example, the second level cache receives a fourth prefetch request from the MAB, extracts the second storage information corresponding to the predicted physical address from the next level cache or from itself, and returns the second storage information to the MAB, such that the MAB sends the extracted second storage information to the first level cache.

The information processing method described in fig. 6 is further explained below with reference to fig. 4B. As shown in fig. 4B, the embodiment may further include steps S401 to S406 in addition to the foregoing steps.

As shown in FIG. 4B, if the target cache is a first level cache, the prefetcher may perform step S401. Step S401: a third prefetch request is sent to the address translation pipeline that includes the predicted virtual address. For example, operation S610 described above with reference to fig. 6 may be performed.

Step S403: the address translation pipeline translates the predicted virtual address to a third predicted physical address in response to the third prefetch request and generates a fourth prefetch request based on the third predicted physical address.

The address translation pipeline also judges whether second storage information corresponding to the third predicted physical address is cached in the first-level cache. And discarding the fourth prefetch request in response to the second storage information corresponding to the third predicted physical address having been cached in the first level cache. And in response to that the second storage information corresponding to the third predicted physical address is not cached in the first-level cache, sending a fourth prefetch request to the MAB, so that the MAB sends the fourth prefetch request to the second-level cache. For example, operations S620-S650 described above with reference to FIG. 6 may be performed.

Step S404: the MAB sends a fourth prefetch request to the second level cache.

Step S405: the second level cache fetches second storage information corresponding to the third predicted physical address in response to a fourth prefetch request from the MAB, and sends the fetched second storage information to the MAB. For example, operation S660 described above with reference to fig. 6 may be performed.

Step S406: and the MAB sends the extracted second storage information to the first-level cache.

In some embodiments of the present disclosure, the prefetch queue and the address translation pipeline share the same interface of the address cache, so that interface resources can be saved. Alternatively, in other embodiments of the present disclosure, the prefetch queue and the address translation pipeline each occupy a different interface in the address cache. For example, an MAB interface exclusive of a prefetch queue can be added to a processor to reduce prefetch latency.

Fig. 7 shows a schematic block diagram of an information processing apparatus 700 according to at least one embodiment of the present disclosure.

For example, as shown in fig. 7, the information processing apparatus 700 includes an acquisition unit 710, a prediction unit 720, a judgment unit 730, and an address determination unit 740.

The acquisition unit 710 is configured to acquire read information of a history read request. The history read request is sent by a processor core of the processor. The history read request indicates that the processor core requests to read the first stored information at the history time. The read information includes a historical virtual address and a historical physical address of the first stored information, the historical physical address corresponding to the historical virtual address. The obtaining unit 710 may, for example, perform step S310 described in fig. 3, which is not described herein again.

The prediction unit 720 is configured to predict a predicted virtual address at which the processor core requests the read second storage information at a future time, based on the historical virtual address. The second determining unit 720 may, for example, perform step S320 described in fig. 3, which is not described herein again.

The determining unit 730 is configured to determine whether the predicted virtual address and the historical virtual address are in the same virtual address page. The determination unit 730 may perform, for example, step S330 described in fig. 3.

The address determination unit 740 is configured to determine a first predicted physical address from the historical virtual address, the historical physical address, and the predicted virtual address in response to the predicted virtual address being in the same virtual address page as the historical virtual address. The first predicted physical address corresponds to the predicted virtual address. The address determining unit 740 may, for example, perform step S340 described in fig. 3, which is not described herein again.

For example, the obtaining unit 710, the predicting unit 720, the judging unit 730, and the address determining unit 740 may be hardware, software, firmware, or any feasible combination thereof. For example, the obtaining unit 710, the predicting unit 720, the judging unit 730, and the address determining unit 740 may be dedicated or general circuits, chips, or devices, and may also be a combination of a processor and a memory. The embodiments of the present disclosure are not limited in this regard to the specific implementation forms of the above units.

It should be noted that, in the embodiment of the present disclosure, each unit of the information processing apparatus 700 corresponds to each step of the foregoing information processing method, and for a specific function of the information processing apparatus 700, reference may be made to the related description about the information processing method, which is not described herein again. The components and configuration of information processing apparatus 700 shown in fig. 7 are exemplary only, and not limiting, and information processing apparatus 700 may also include other components and configurations as desired.

At least one embodiment of the present disclosure also provides an electronic device including a processor for implementing the information processing method described above. The electronic equipment can at least partially avoid time delay brought by address translation, and improves the effectiveness of prefetching. In addition, because the address translation pipeline is frequently required to be shared with the prefetching for normal instruction and data reading, the information processing method reduces address translation for prefetching, reduces address reading time delay for normal reading, and reduces power consumption required for address translation prefetching.

Fig. 8 is a schematic block diagram of an electronic device provided in some embodiments of the present disclosure. As shown in fig. 8, the electronic device 800 includes a processor 810. Processor 810, when running, may perform one or more of the steps of the information processing methods described above.

For example, processor 810 may be a Central Processing Unit (CPU) or other form of processing unit having data processing capabilities and/or program execution capabilities. For example, the Central Processing Unit (CPU) may be an X86 or ARM architecture or the like. The processor 810 may be a general-purpose processor or a special-purpose processor that may control other components in the electronic device 800 to perform desired functions.

It should be noted that, in the embodiment of the present disclosure, reference may be made to the above description on the information processing method for specific functions and technical effects of the electronic device 800, and details are not described here again.

Fig. 9 is a schematic block diagram of another electronic device provided by some embodiments of the present disclosure. The electronic device 900 is, for example, suitable for implementing the information processing method provided by the embodiment of the present disclosure. The electronic device 900 may be a terminal device or the like. It should be noted that the electronic device 900 shown in fig. 9 is only one example and does not bring any limitations to the function and the scope of the use of the embodiments of the present disclosure.

As shown in fig. 9, electronic device 900 may include a processing means (e.g., central processing unit) 910 that may perform various appropriate actions and processes in accordance with a program stored in a Read Only Memory (ROM)920 or a program loaded from a storage means 980 into a Random Access Memory (RAM) 930. In the RAM 930, various programs and data necessary for the operation of the electronic apparatus 900 are also stored. The processing device 910, the ROM 920, and the RAM 930 are connected to each other by a bus 940. An input/output (I/O) interface 950 is also connected to bus 940.

Generally, the following devices may be connected to the I/O interface 950: input devices 960 including, for example, a touch screen, touch pad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; output devices 970 including, for example, a Liquid Crystal Display (LCD), speaker, vibrator, or the like; storage 980 including, for example, magnetic tape, hard disk, etc.; and a communication device 990. The communication means 990 may allow the electronic device 900 to communicate wirelessly or by wire with other electronic devices to exchange data. While fig. 9 illustrates an electronic device 900 having various means, it is to be understood that not all illustrated means are required to be implemented or provided, and that the electronic device 900 may alternatively be implemented or provided with more or less means.

For example, according to an embodiment of the present disclosure, the processing device 910 may execute the information processing method described above, and may implement the functions defined in the information processing method provided by the embodiment of the present disclosure.

The following points need to be explained:

(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to common designs.

(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above description is only a specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be subject to the scope of the claims.

Claims

1. An information processing method comprising:

obtaining reading information of a history reading request, wherein the history reading request is sent by a processor core of a processor, the history reading request indicates that the processor core requests to read first storage information at a history moment, the reading information comprises a history virtual address and a history physical address of the first storage information, and the history physical address corresponds to the history virtual address;

predicting a predicted virtual address where second storage information requested to be read by the processor core at a future moment is located according to the historical virtual address;

judging whether the predicted virtual address and the historical virtual address are in the same virtual address page or not;

and in response to the predicted virtual address and the historical virtual address being in the same virtual address page, determining a first predicted physical address according to the historical virtual address, the historical physical address and the predicted virtual address, wherein the first predicted physical address corresponds to the predicted virtual address.

2. The method of claim 1, wherein determining the first predicted physical address from the historical virtual address, the historical physical address, and the predicted virtual address in response to the predicted virtual address being in a same virtual address page as the historical virtual address comprises:

in response to the predicted virtual address and the historical virtual address being in the same virtual address page, taking a sum of an offset between the predicted virtual address and the historical physical address as the first predicted physical address.

3. The method of claim 1, wherein the processor comprises a multi-level cache comprising at least a first level cache and a second level cache, the first level cache being one of the multi-level cache that is electrically connected to the processor core and that transfers data directly with the processor core, the second level cache being one of the multi-level cache that is electrically connected to the first level cache and that transfers data with the processor core through the first level cache,

the method further comprises the following steps:

determining a target cache of the second storage information, wherein the target cache comprises the first-level cache or the second-level cache;

the determining whether the predicted virtual address and the historical virtual address are in the same virtual address page includes:

and responding to the target cache being the second-level cache, and judging whether the predicted virtual address and the historical virtual address are in the same virtual address page.

4. The method of claim 3, wherein the processor further comprises a prefetcher, the method further comprising:

the prefetcher generates a first prefetching request according to the first predicted physical address, wherein the first prefetching request is used for requesting to store second storage information stored in the first predicted physical address into the second-level cache;

the prefetcher sending the first prefetch request to the second level cache; and

and the second-level cache responds to the first pre-fetching request and caches the second storage information corresponding to the first predicted physical address into the second-level cache.

5. The method of claim 4, wherein the second-level cache, in response to the first prefetch request, caches the second storage information corresponding to the first predicted physical address to the second-level cache, comprising:

the second-level cache responds to the first pre-fetching request and determines whether second storage information corresponding to the first predicted physical address is cached in the second-level cache or not;

discarding the first prefetch request in response to the second level cache having cached second storage information corresponding to the first predicted physical address; and

in response to the second-level cache not caching the second storage information corresponding to the first predicted physical address, the second-level cache extracts the second storage information corresponding to the first predicted physical address from a next-level cache or a memory and stores the second storage information in the second-level cache.

6. The method of claim 4, wherein the prefetcher sending the first prefetch request to the second level cache comprises:

the prefetcher sending the first prefetch request to a prefetch queue to store the first prefetch request through the prefetch queue; and

in response to the second level cache having free space, the prefetch queue sends the first prefetch request to the second level cache.

7. The method of claim 6, wherein the prefetcher sends the first prefetch request to the second level cache, further comprising:

responsive to the memory space of the prefetch queue being full, discarding the first prefetch request or replacing other prefetch requests in the prefetch queue with the first prefetch request.

8. The method of claim 7, wherein the processor further comprises an address translation pipeline, the method further comprising:

in response to the predicted virtual address not being in the same virtual address page as the historical virtual address, address translating the predicted virtual address through the address translation pipeline to obtain a second predicted physical address.

9. The method of claim 8, further comprising:

the address translation pipeline generates a second prefetch request according to the second predicted physical address and sends the second prefetch request to the prefetch queue;

the prefetch queue sends the second prefetch request to the second level cache in response to the second prefetch request;

the second-level cache responds to the second prefetching request and determines whether second storage information corresponding to the second predicted physical address is cached in the second-level cache;

discarding the second prefetch request in response to second storage information corresponding to the second predicted physical address having been cached in the second level cache;

in response to that the second storage information corresponding to the second predicted physical address is not cached in the second-level cache, the second-level cache extracts the second storage information corresponding to the second predicted physical address from a next-level cache or a memory, and stores the second storage information in the second-level cache.

10. The method of claim 8, wherein, in a case where the predicted virtual address is multiple and multiple predicted virtual addresses are within a same virtual address page, in response to the predicted virtual address not being in the same virtual address page as the historical virtual address, address translating the predicted virtual address through the address translation pipeline to obtain the second predicted physical address, comprises:

responding to the fact that the plurality of predicted virtual addresses are not in the same virtual address page with the historical virtual address, and performing address translation on the selected predicted virtual address in the plurality of predicted virtual addresses through the address translation pipeline to obtain a second predicted physical address; and

and determining second predicted physical addresses corresponding to other predicted virtual addresses except the selected predicted virtual address in the plurality of predicted virtual addresses according to the second predicted physical address corresponding to the selected predicted virtual address.

11. The method of claim 10, wherein the selected predicted virtual address is a predicted virtual address of the plurality of predicted virtual addresses predicted by the prefetcher that is accessed by the processor core first.

12. The method of claim 8, wherein the prefetch queue and the address translation pipeline share the same interface of the address cache, or the prefetch queue and the address translation pipeline each occupy a different interface in the address cache.

13. The method of claim 8, further comprising:

in response to the target cache being the first level cache, sending a third prefetch request to the address translation pipeline such that the third prefetch request reaches the address translation pipeline, wherein the third prefetch request includes the predicted virtual address;

the address translation pipeline translating, in response to the third prefetch request, the predicted virtual address to a third predicted physical address and generating a fourth prefetch request from the third predicted physical address;

determining whether second storage information corresponding to the third predicted physical address is cached in the first-level cache;

discarding the fourth prefetch request in response to second storage information corresponding to the third predicted physical address having been cached in the first level cache;

in response to that second storage information corresponding to the third predicted physical address is not cached in the first-level cache, sending the fourth prefetch request to the address cache, so that the address cache sends the fourth prefetch request to the second-level cache; and

the second level cache fetches second storage information corresponding to the third predicted physical address in response to the fourth prefetch request from the address cache and sends the fetched second storage information to the address cache, such that the address cache sends the fetched second storage information to the first level cache.

14. The method of any of claims 1-13, wherein determining whether the predicted virtual address and the historical virtual address are in a same virtual address page comprises:

determining the size of a page of a virtual address page where the historical virtual address is located; and

and judging whether the predicted virtual address and the historical virtual address are in the same virtual address page or not based on the size of the page of the virtual address page.

15. An information processing apparatus comprising:

an obtaining unit configured to obtain read information of a history read request, wherein the history read request is sent by a processor core of a processor, the history read request indicates that the processor core requests to read first storage information at a history time, the read information includes a history virtual address and a history physical address of the first storage information, and the history physical address corresponds to the history virtual address;

the prediction unit is configured to predict a predicted virtual address where the second storage information requested to be read by the processor core at a future moment is located according to the historical virtual address;

a judging unit configured to judge whether the predicted virtual address and the historical virtual address are in the same virtual address page; and

an address determination unit configured to determine a first predicted physical address from the historical virtual address, the historical physical address, and the predicted virtual address in response to the predicted virtual address being in a same virtual address page as the historical virtual address, wherein the first predicted physical address corresponds to the predicted virtual address.

16. An electronic device comprising a processor, wherein the processor is configured to implement the information processing method of any one of claims 1-14.