CN112415367A - Drive chip abnormality detection method and device, electronic equipment and readable storage medium - Google Patents
Drive chip abnormality detection method and device, electronic equipment and readable storage medium Download PDFInfo
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- G—PHYSICS
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
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Abstract
The invention provides a method and a device for detecting the abnormality of a drive chip, an electronic device and a readable storage medium, wherein the method comprises the following steps: inputting a link training signal to a first driving chip in the N driving chips connected in series through a first pin of the time schedule controller; when the first pin is detected to be at a first level and the duration time exceeds a first preset time, judging to enter a detection mode; respectively and sequentially inputting a link training signal to each target drive chip in the N drive chips in the detection mode, and acquiring the level of the first pin when a link control signal is input to the target drive chip again; and when the level of the first pin is a first level, judging that the target driving chip is abnormal. According to the invention, each driving chip is detected through the time schedule controller, the abnormal information of the driving chip is obtained, and the abnormal information is displayed in the display screen at the corresponding position of the normal driving chip, so that the abnormal reason is rapidly and correctly determined.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a method and an apparatus for detecting an abnormality of a driver chip, an electronic device, and a readable storage medium.
Background
In the existing large-sized Liquid Crystal Display (LCD), there are mutually independent unit modules such as a timing controller, a driving chip, and a power chip, and when an electronic device is lit, the individual driving chip is burnt out, but the failed driving chip cannot be known, and a defective product needs to be returned to a factory for analysis, so that the failed driving chip can be confirmed.
Disclosure of Invention
The invention provides a method and a device for detecting the abnormality of a drive chip, an electronic device and a readable storage medium, which are used for solving the problem that the drive chip with a fault cannot be known when the electronic device is in a bad state.
According to a first aspect of the present invention, the present invention provides a method for detecting abnormality of a driver chip, the method comprising: inputting a link training signal to a first driving chip in the N driving chips connected in series through a first pin of the time schedule controller; when the first pin is detected to be at a first level and the duration time exceeds a first preset time, judging to enter a detection mode; respectively and sequentially inputting a link training signal to each target drive chip in the N drive chips in the detection mode, and acquiring the level of the first pin when a link control signal is input to the target drive chip again; and when the level of the first pin is a first level, judging that the target driving chip is abnormal.
In some embodiments, the timing controller further includes a second pin electrically connected to the first pin, and when the first pin is at a first level and exceeds the first predetermined time, determining to enter the detection mode includes: and controlling the second pin to automatically switch from a first level to a second level so as to indicate to enter the detection mode.
In some embodiments, the method further comprises: when the second pin is at a first level, indicating to enter a normal mode, and inputting a link training signal to a first driving chip in the N driving chips connected in series in the normal mode; and when the second pin is at a second level, indicating to enter the detection mode, and respectively and sequentially inputting a link training signal to each target drive chip in the N drive chips in the detection mode.
In some embodiments, the method further comprises: and when the level of the first pin is a second level, judging that the target driving chip is normal.
In some embodiments, the determining that the target driver chip is abnormal includes: and recording abnormal information of the target drive chip, wherein the abnormal information at least comprises the position information of the target drive chip.
In some embodiments, the method further comprises: when the detection of all the driving chips is completed, automatically converting the first pin from a first level to a second level; and inputting a display signal to a normal driving chip to control a display panel electrically connected with the driving chip to display prompt characters, wherein the prompt characters are used for indicating the abnormal driving chip.
In some embodiments, the method further comprises: and if the display signal is input to the normal driving chip for a second preset time, inputting the link training signal to a first driving chip of the N driving chips connected in series again through the first pin.
According to a second aspect of the present invention, there is provided a driver chip abnormality detection apparatus, comprising: the input module is used for inputting a link training signal to a first driving chip in the N driving chips connected in series through a first pin of the time schedule controller; the first judgment module is used for judging to enter a detection mode when the first pin is detected to be at a first level and the duration time exceeds a first preset time; the acquisition module is used for respectively and sequentially inputting a link training signal to each target drive chip in the N drive chips in the detection mode and acquiring the level of the first pin when the link control signal is input to the target drive chip; and the second judging module is used for judging that the target driving chip is abnormal when the level of the first pin is the first level.
According to a third aspect of the present invention, an electronic device is provided, which includes a processor, a memory, and a program or an instruction stored in the memory and executable on the processor, wherein the program or the instruction, when executed by the processor, implements the steps of the driver chip abnormality detection method as described above.
According to a fourth aspect of the present invention, the present invention provides a readable storage medium, on which a program or an instruction is stored, and when the program or the instruction is executed by a processor, the method for detecting the abnormality of the driver chip as described above is implemented.
Compared with the prior art, the invention has the beneficial effects that: according to the invention, each driving chip is detected through the time schedule controller, the abnormal information of the driving chip is obtained, and the abnormal information is displayed in the display screen at the corresponding position of the normal driving chip, so that the abnormal reason is rapidly and correctly determined.
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Fig. 1 is a schematic flowchart illustrating a method for detecting an abnormality of a driver chip according to an embodiment of the present invention.
Fig. 2 is a circuit diagram of a normal mode according to the present invention.
FIG. 3 is a circuit diagram of a detection mode according to the present invention.
Fig. 4 is a schematic structural diagram of a device for detecting abnormality of a driver chip according to an embodiment of the present invention.
Fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, an embodiment of the invention provides a method for detecting an abnormality of a driver chip, which is applied to an electronic device and includes steps S11 to S14.
In step S11, a link training signal is input to a first driver chip of the N driver chips connected in series through a first pin of the timing controller.
In the embodiment of the present invention, the driving chip is a source driving chip, but is not limited thereto. In some other embodiments, the driving chip may be a gate driving chip or the like. The interface between the timing controller and the driving chip is preferably, but not limited to, a Clock Embedded Data Signaling (CEDS) interface in which a clock signal has been embedded in a data signal.
In step S12, when the first pin is detected to be at the first level and the duration time exceeds the first preset time, it is determined to enter the detection mode.
In the embodiment of the invention, the timing controller inputs the link training signal to the N driving chips connected in series, when an abnormality occurs to a certain driving chip, the communication of the timing controller is also abnormal, which is specifically shown in that the level of the first pin (RX _ LOCK _ N pin) of the timing controller is the first level (low level), so that the timing controller cannot always transmit the link training signal to cause the display panel to display a black screen.
In some embodiments, the first predetermined time may be set to 5s to avoid the problem that the level detection result is inaccurate due to too short time or the overall detection time is too long due to too long time.
In some embodiments, the timing controller further includes a second pin (Fail _ Detect pin), the second pin is electrically connected to the first pin, and step 12 specifically includes: and controlling the second pin to automatically switch from the first level to the second level so as to indicate that the detection mode is entered.
Step S13, sequentially inputting a link training signal to each target driver chip of the N driver chips in the detection mode, and retrieving the level of the first pin when a link control signal is input to the target driver chip.
In an embodiment of the invention, the electronic device includes a normal mode and a detection mode. When the second pin is at a first level, indicating to enter a normal mode, and inputting a link training signal to a first driving chip in the N driving chips connected in series in the normal mode; and when the second pin is at a second level, indicating to enter a detection mode, and respectively and sequentially inputting a link training signal to each target drive chip in the N drive chips in the detection mode.
Referring to fig. 2, the present invention provides a circuit diagram under a normal mode. In the normal mode, the driving chip is connected to the first pin after being connected in series.
Referring to fig. 3, the present invention provides a circuit diagram under a detection mode. In the detection mode, the driving chip can be connected to the first pin alone, or a plurality of driving chips can be connected to the first pin after being connected in parallel.
In step S14, when the level of the first pin is the first level, it is determined that the target driver chip is abnormal.
In this embodiment of the present invention, step S14 further includes: and recording the abnormal information of the target drive chip, wherein the abnormal information at least comprises the position information of the target drive chip.
In some embodiments, when the level of the first pin is the second level, the target driver chip is determined to be normal.
In some embodiments, the method for detecting a driver chip further includes steps S15 to S17.
In step S15, when the detection of all the driver chips is completed, the first pin is automatically converted from the first level to the second level.
And step S16, inputting a display signal to the normal driving chip to control a display panel electrically connected with the driving chip to display a prompt character, wherein the prompt character is used for indicating the abnormal driving chip.
Step S17, if the display signal is input to the normal driver chip for the second preset time, re-input the link training signal to the first driver chip of the N driver chips connected in series through the first pin.
After the detection is finished, the normal driving chips are connected in parallel and then connected to the time sequence controller, and the display panel at the corresponding position of the time sequence controller space-time driving chips displays prompt characters. And after the display time lasts for a period of time, the electronic equipment is controlled to be switched to a normal mode, namely, the link training signals are input to the N drive chips connected in series again through the first pins.
As shown in fig. 2, an embodiment of the invention provides a device for detecting abnormality of a driver chip, which is applied to an electronic device, and the device includes an input module 21, a first determining module 22, an obtaining module 23, and a second determining module 24.
The input module 21 is configured to input a link training signal to a first driver chip of the N driver chips connected in series through a first pin of the timing controller.
In the embodiment of the present invention, the driving chip is a source driving chip, but is not limited thereto. In some other embodiments, the driving chip may be a gate driving chip or the like. The interface between the timing controller and the driving chip is preferably, but not limited to, a Clock Embedded Data Signaling (CEDS) interface in which a clock signal has been embedded in a data signal.
The first determining module 22 is configured to determine to enter the detecting mode when the first pin is detected to be at the first level and the duration time exceeds a first preset time.
In the embodiment of the invention, the timing controller inputs the link training signal to the N driving chips connected in series, when an abnormality occurs to a certain driving chip, the communication of the timing controller is also abnormal, which is specifically shown in that the level of the first pin (RX _ LOCK _ N pin) of the timing controller is the first level (low level), so that the timing controller cannot always transmit the link training signal to cause the display panel to display a black screen.
In some embodiments, the first predetermined time may be set to 5s to avoid the problem that the level detection result is inaccurate due to too short time or the overall detection time is too long due to too long time.
In some embodiments, the timing controller further includes a second pin (Fail _ Detect pin) electrically connected to the first pin, and when the first pin is detected to be at the first level and the duration exceeds a first preset time, the second pin is controlled to automatically switch from the first level to the second level to indicate that the detection mode is entered.
The obtaining module 23 is configured to respectively sequentially input a link training signal to each target driver chip of the N driver chips in the detection mode, and to obtain the level of the first pin when a link control signal is input to the target driver chip again.
In an embodiment of the invention, the electronic device includes a normal mode and a detection mode. When the second pin is at a first level, judging to enter a normal mode, and inputting a link training signal to a first driving chip in the N driving chips connected in series in the normal mode; and when the second pin is at a second level, judging to enter a detection mode, and respectively and sequentially inputting a link training signal to each target driving chip in the N driving chips in the detection mode.
In the normal mode, the driving chip is connected to the first pin after being connected in series; in the detection mode, the driving chip may be connected to the first pin alone or in parallel.
The second determination module 24 is configured to determine that the target driver chip is abnormal when the level of the first pin is the first level.
In the embodiment of the invention, after the target driving chip is judged to be abnormal, the abnormal information of the target driving chip is recorded, and the abnormal information at least comprises the position information of the target driving chip.
In some embodiments, when the level of the first pin is the second level, the target driver chip is determined to be normal.
In some embodiments, when all the driver chips are detected, the first pin is automatically switched from a first level to a second level; inputting a display signal to a normal driving chip to control a display panel electrically connected with the driving chip to display prompt characters, wherein the prompt characters are used for indicating an abnormal driving chip; and when the prompt characters are displayed for a second preset time, inputting link training signals to the N drive chips connected in series again through the first pins.
After the detection is finished, the normal driving chips are connected in parallel and then connected to the time sequence controller, and the display panel at the corresponding position of the time sequence controller space-time driving chips displays prompt characters. And if the display signal is input to the normal driving chip for a second preset time, controlling the electronic equipment to be switched to the normal mode, namely inputting the link training signal to the first driving chip of the N driving chips connected in series again through the first pin.
Referring to fig. 5, an embodiment of the invention further provides an electronic device 500, where the electronic device 500 may be a mobile phone, a tablet, a computer, or the like. As shown in fig. 5, the electronic device 500 includes a processor 501, a memory 502. The processor 501 is electrically connected to the memory 502.
The processor 501 is a control center of the electronic device 500, connects various parts of the whole electronic device by using various interfaces and lines, executes various functions of the electronic device and processes data by running or loading an application program stored in the memory 502 and calling the data stored in the memory 502, thereby performing overall monitoring of the electronic device.
In this embodiment, the electronic device 500 is provided with a plurality of memory partitions, where the plurality of memory partitions includes a system partition and a target partition, and the processor 501 in the electronic device 500 loads instructions corresponding to processes of one or more application programs into the memory 502 according to the following steps, and the processor 501 runs the application programs stored in the memory 502, so as to implement various functions:
inputting a link training signal to a first driving chip in the N driving chips connected in series through a first pin of the time schedule controller;
when the first pin is detected to be at a first level and the duration time exceeds a first preset time, judging to enter a detection mode;
respectively and sequentially inputting a link training signal to each target drive chip in the N drive chips in the detection mode, and acquiring the level of the first pin when a link control signal is input to the target drive chip again; and
and when the level of the first pin is a first level, judging that the target driving chip is abnormal.
Referring to fig. 6, fig. 6 shows a specific structural block diagram of an electronic device 600 provided in an embodiment of the present invention, where the electronic device 600 may be used to implement the driving chip detection method provided in the above embodiment. The electronic device 600 may be a mobile phone or a tablet. The electronic device 600 also includes the following components.
The RF circuit 610 is used for receiving and transmitting electromagnetic waves, and performs interconversion between the electromagnetic waves and electrical signals, thereby communicating with a communication network or other devices. RF circuit 610 may include various existing circuit elements for performing these functions, such as an antenna, a radio frequency transceiver, a digital signal processor, an encryption/decryption chip, a Subscriber Identity Module (SIM) card, memory, and so forth. The RF circuit 610 may communicate with various networks such as the internet, an intranet, a wireless network, or with other devices over a wireless network. The wireless network may comprise a cellular telephone network, a wireless local area network, or a metropolitan area network. The Wireless network may use various Communication standards, protocols, and technologies, including, but not limited to, Global System for Mobile Communication (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (WCDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Wireless Fidelity (Wi-Fi) (e.g., IEEE802.11a, IEEE802.11 b, IEEE 802.2.access, and/or IEEE802.11 n), Voice over Internet Protocol (VoIP), world wide Internet Microwave Access (Microwave for Wireless Communication), other suitable protocols for short message service (Max), and any other suitable protocols, and may even include those protocols that have not yet been developed.
The memory 620 may be used to store software programs and modules, such as program instructions/modules corresponding to the driver chip detection method in the foregoing embodiment, and the processor 680 executes various functional applications and data processing by running the software programs and modules stored in the memory 620, so as to implement the functions of the driver chip detection method. The memory 620 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 620 can further include memory located remotely from the processor 680, which can be connected to the electronic device 600 via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The input unit 630 may be used to receive input numeric or character information and generate keyboard, mouse, joystick, optical or trackball signal inputs related to user settings and function control. In particular, the input unit 630 may include a touch sensitive surface 631 as well as other input devices 632. The touch sensitive surface 631, also referred to as a touch display screen or a touch pad, may collect touch operations by a user (e.g., operations by a user on the touch sensitive surface 631 or near the touch sensitive surface 631 using any suitable object or attachment such as a finger, a stylus, etc.) on or near the touch sensitive surface 631 and drive the corresponding connection device according to a predetermined program. Alternatively, the touch sensitive surface 631 may comprise two parts, a touch detection means and a touch controller. The touch detection device detects the touch direction of a user, detects a signal brought by touch operation and transmits the signal to the touch controller; the touch controller receives touch information from the touch sensing device, converts the touch information into touch point coordinates, sends the touch point coordinates to the processor 680, and can receive and execute commands sent by the processor 680. In addition, the touch sensitive surface 631 may be implemented using various types of resistive, capacitive, infrared, and surface acoustic waves. The input unit 630 may include other input devices 632 in addition to the touch-sensitive surface 631. In particular, other input devices 632 may include, but are not limited to, one or more of a physical keyboard, function keys (such as volume control keys, switch keys, etc.), a trackball, a mouse, a joystick, and the like.
The display unit 640 may be used to display information input by or provided to a user and various graphical user interfaces of the electronic device 600, which may be made up of graphics, text, icons, video, and any combination thereof. The Display unit 640 may include a Display panel 641, and optionally, the Display panel 641 may be configured in the form of an LCD (Liquid Crystal Display), an OLED (Organic Light-Emitting Diode), or the like. Further, the touch-sensitive surface 631 may overlay the display panel 641, and when the touch-sensitive surface 631 detects a touch operation thereon or nearby, the touch operation is transmitted to the processor 680 to determine the type of the touch event, and then the processor 680 provides a corresponding visual output on the display panel 641 according to the type of the touch event. Although in FIG. 6, the touch-sensitive surface 631 and the display panel 641 are implemented as two separate components to implement input and output functions, in some embodiments, the touch-sensitive surface 631 and the display panel 641 may be integrated to implement input and output functions.
The electronic device 600 may also include at least one sensor 650, such as light sensors, motion sensors, and other sensors. Specifically, the light sensor may include an ambient light sensor that may adjust the brightness of the display panel 641 according to the brightness of ambient light, and a proximity sensor that may turn off the display panel 641 and/or the backlight when the electronic device 600 is moved to the ear. As one of the motion sensors, the gravity acceleration sensor can detect the magnitude of acceleration in each direction (generally, three axes), can detect the magnitude and direction of gravity when the mobile phone is stationary, and can be used for applications of recognizing the posture of the mobile phone (such as horizontal and vertical screen switching, related games, magnetometer posture calibration), vibration recognition related functions (such as pedometer and tapping), and the like; as for other sensors such as a gyroscope, a barometer, a hygrometer, a thermometer, and an infrared sensor, which can be configured in the electronic device 600, further description is omitted here.
The electronic device 600, via the transport module 670 (e.g., a Wi-Fi module), may assist a user in emailing, browsing web pages, accessing streaming media, etc., which provides wireless broadband internet access to the user. Although fig. 6 shows the transmission module 670, it is understood that it does not belong to the essential constitution of the electronic device 600 and may be omitted entirely as needed within the scope not changing the essence of the invention.
The processor 680 is a control center of the electronic device 600, connects various parts of the entire mobile phone using various interfaces and lines, and performs various functions of the electronic device 600 and processes data by operating or executing software programs and/or modules stored in the memory 620 and calling data stored in the memory 620, thereby monitoring the mobile phone as a whole. Optionally, processor 680 may include one or more processing cores; in some embodiments, processor 680 may integrate an application processor, which handles primarily the operating system, user interface, applications, etc., and a modem processor, which handles primarily wireless communications. It will be appreciated that the modem processor described above may not be integrated into processor 680.
Electronic device 600 also includes a power supply 690 (e.g., a battery) that provides power to the various components, and in some embodiments may be logically coupled to processor 680 via a power management system that may perform functions such as managing charging, discharging, and power consumption. The power supply 690 may also include any component including one or more dc or ac power sources, recharging systems, power failure detection circuitry, power converters or inverters, power status indicators, and the like.
Although not shown, the electronic device 600 may further include a camera (e.g., a front camera, a rear camera), a bluetooth module, and the like, which are not described in detail herein. Specifically, in this embodiment, the display unit of the electronic device is a touch screen display, the electronic device further includes a memory, and one or more programs, where the one or more programs are stored in the memory and configured to be executed by the one or more processors, and the one or more programs include instructions for:
inputting a link training signal to a first driving chip in the N driving chips connected in series through a first pin of the time schedule controller;
when the first pin is detected to be at a first level and the duration time exceeds a first preset time, judging to enter a detection mode;
respectively and sequentially inputting a link training signal to each target drive chip in the N drive chips in the detection mode, and acquiring the level of the first pin when a link control signal is input to the target drive chip again; and
and when the level of the first pin is a first level, judging that the target driving chip is abnormal.
In specific implementation, the above modules may be implemented as independent entities, or may be combined arbitrarily to be implemented as the same or several entities, and specific implementation of the above modules may refer to the foregoing method embodiments, which are not described herein again.
It will be understood by those skilled in the art that all or part of the steps of the methods of the above embodiments may be performed by instructions or by instructions controlling associated hardware, and the instructions may be stored in a computer readable storage medium and loaded and executed by a processor. To this end, the present invention provides a readable storage medium, in which a plurality of instructions are stored, and the instructions can be loaded by a processor to execute the steps in any one of the driver chip detection methods provided in the embodiments of the present invention.
Wherein the readable storage medium may include: read Only Memory (ROM), Random Access Memory (RAM), magnetic or optical disks, and the like.
Since the instructions stored in the readable storage medium can execute the steps in any one of the driving chip detection methods provided in the embodiments of the present invention, the beneficial effects that can be achieved by any one of the driving chip detection methods provided in the embodiments of the present invention can be achieved, which are detailed in the foregoing embodiments and will not be described again here. The above operations can be implemented in the foregoing embodiments, and are not described in detail herein.
The invention has the beneficial effects that: according to the invention, each driving chip is detected through the time schedule controller, the abnormal information of the driving chip is obtained, and the abnormal information is displayed in the display screen at the corresponding position of the normal driving chip, so that the abnormal reason is rapidly and correctly determined.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The method, the system, the readable storage medium and the electronic device for detecting the abnormality of the driver chip provided by the embodiment of the present invention are described in detail, and a specific example is applied to illustrate the principle and the implementation manner of the present invention, and the description of the embodiment is only used to help understanding the technical scheme and the core idea of the present invention; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A method for detecting abnormality of a driver chip includes:
inputting a link training signal to a first driving chip in the N driving chips connected in series through a first pin of the time schedule controller;
when the first pin is detected to be at a first level and the duration time exceeds a first preset time, judging to enter a detection mode;
respectively and sequentially inputting a link training signal to each target drive chip in the N drive chips in the detection mode, and acquiring the level of the first pin when a link control signal is input to the target drive chip again; and
and when the level of the first pin is a first level, judging that the target driving chip is abnormal.
2. The method as claimed in claim 1, wherein the timing controller further comprises a second pin electrically connected to the first pin, and the determining to enter the detection mode when the first pin is at the first level and exceeds the first predetermined time comprises:
and controlling the second pin to automatically switch from a first level to a second level so as to indicate to enter the detection mode.
3. The method of detecting abnormality in a driver chip according to claim 2, further comprising:
when the second pin is at a first level, indicating to enter a normal mode, and inputting a link training signal to a first driving chip in the N driving chips connected in series in the normal mode;
and when the second pin is at a second level, indicating to enter the detection mode, and respectively and sequentially inputting a link training signal to each target drive chip in the N drive chips in the detection mode.
4. The method of detecting abnormality in a driver chip according to claim 1, further comprising:
and when the level of the first pin is a second level, judging that the target driving chip is normal.
5. The method as claimed in claim 1, wherein the step of determining the target driver chip is abnormal comprises:
and recording abnormal information of the target drive chip, wherein the abnormal information at least comprises the position information of the target drive chip.
6. The method of detecting abnormality in a driver chip according to claim 1, further comprising:
when the detection of all the driving chips is completed, automatically converting the first pin from a first level to a second level;
and inputting a display signal to a normal driving chip to control a display panel electrically connected with the driving chip to display prompt characters, wherein the prompt characters are used for indicating the abnormal driving chip.
7. The method of detecting abnormality in a driver chip according to claim 6, further comprising:
and if the display signal is input to the normal driving chip for a second preset time, inputting the link training signal to a first driving chip of the N driving chips connected in series again through the first pin.
8. An abnormality detection device for a driver chip, comprising:
the input module is used for inputting a link training signal to a first driving chip in the N driving chips connected in series through a first pin of the time schedule controller;
the first judgment module is used for judging to enter a detection mode when the first pin is detected to be at a first level and the duration time exceeds a first preset time;
the acquisition module is used for respectively and sequentially inputting a link training signal to each target drive chip in the N drive chips in the detection mode and acquiring the level of the first pin when the link control signal is input to the target drive chip; and
and the second determination module is used for determining that the target driving chip is abnormal when the level of the first pin is the first level.
9. An electronic device comprising a processor, a memory, and a program or instructions stored on the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the driver chip abnormality detection method according to any one of claims 1 to 7.
10. A readable storage medium storing a program or instructions thereon, wherein the program or instructions when executed by a processor implement the driver chip abnormality detection method according to any one of claims 1 to 7.
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