CN112415296B - Test equipment and test system - Google Patents
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- CN112415296B CN112415296B CN201910786191.1A CN201910786191A CN112415296B CN 112415296 B CN112415296 B CN 112415296B CN 201910786191 A CN201910786191 A CN 201910786191A CN 112415296 B CN112415296 B CN 112415296B
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- 238000012360 testing method Methods 0.000 title claims abstract description 208
- 230000015654 memory Effects 0.000 claims description 24
- 238000001514 detection method Methods 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 11
- 238000004891 communication Methods 0.000 description 8
- 230000004044 response Effects 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000008878 coupling Effects 0.000 description 3
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- 238000005859 coupling reaction Methods 0.000 description 3
- 238000000638 solvent extraction Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
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- 238000000034 method Methods 0.000 description 2
- 238000011002 quantification Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 238000012545 processing Methods 0.000 description 1
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Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
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Abstract
The embodiment of the invention provides test equipment and a test system. The test apparatus includes: an embedded processor; a transmitting card circuit electrically connected to the embedded processor; and a receiving card test interface electrically connected with the transmitting card circuit. The embodiment of the invention adopts the embedded processor to connect the transmitting card circuit and the receiving card test interface, so that the test equipment can be directly connected with the receiving card, and the signal source is transmitted to the receiving card through the test equipment for being displayed by the LED display screen, thereby realizing the detection of the receiving card.
Description
Technical Field
The invention relates to the technical field of display control, in particular to test equipment and a test system.
Background
When a large LED display screen is built, a plurality of boxes are spliced one by one, the LED display screen is detected after the building is finished, whether the splicing of the LED display screen is normal or not is tested, and whether the receiving card and the boxes work normally or not is judged. In the prior art, the signal source output equipment is connected with the receiving card and the LED display screen through the transmitting card, and can output a simple signal source to the transmitting card, so that the LED display screen displays a test picture. However, the signal source output device can only output the signal source to the transmitting card, and cannot detect the receiving card alone, and meanwhile, the signal source is output to the transmitting card and then transmitted to the receiving card, and the problem that whether the transmitting card or the receiving card is the transmitting card or the receiving card cannot be accurately positioned can also be solved.
Disclosure of Invention
Therefore, in order to overcome the defects and shortcomings in the prior art, the embodiment of the invention provides a testing device and a testing system for detecting a receiving card.
In one aspect, an embodiment of the present invention provides a test apparatus, including: an embedded processor; a transmitting card circuit electrically connected to the embedded processor; and a receiving card test interface electrically connected with the transmitting card circuit.
The embedded processor is connected with the transmitting card circuit and the receiving card test interface, so that the test equipment can be directly connected with the receiving card, and the test equipment transmits a signal source to the receiving card for display by the LED display screen, thereby realizing detection of the receiving card.
In one embodiment of the present invention, the transmitting card circuit includes: the microprocessor is electrically connected with the embedded processor; the programmable logic device is electrically connected with the microprocessor and the embedded processor, and the receiving card test interface is connected with the programmable logic device; and the first nonvolatile memory is electrically connected with the microprocessor and the programmable logic device.
In one embodiment of the invention, the test device further comprises a second non-volatile memory and/or an input source interface, the second non-volatile memory and/or the input source interface being connected to the embedded processor.
In one embodiment of the present invention, the test device further includes a touch screen electrically connected to the embedded processor.
In one embodiment of the present invention, the card test interface includes a first card test interface and a second card test interface, and the first card test interface and the second card test interface are respectively electrically connected to the programmable logic device.
In one embodiment of the invention, the test apparatus further comprises: an output selection circuit electrically connected between the embedded processor and the programmable logic device; and the transmitting card test interface is electrically connected with the output selection circuit.
In another aspect, a test system provided in an embodiment of the present invention includes: a test apparatus as hereinbefore described; and the receiving card is electrically connected with the receiving card test interface of the test equipment.
The test system in this embodiment adopts the test equipment to connect with the receiving card, and determines whether to respond after the test equipment sends the data packet and the receiving card receives the data packet, thereby realizing the access test and locating the receiving card with problems in the access.
In a specific embodiment of the present invention, the test system further comprises: and the LED display screen is electrically connected with the receiving card.
In still another aspect, a test system provided in an embodiment of the present invention includes: a test device as described above; a transmitting card electrically connected with the transmitting card test interface; a receiving card electrically connected with the transmitting card; and the LED display screen is electrically connected with the receiving card.
The test system in the embodiment adopts the test equipment to connect with the transmitting card, the transmitting card is connected with the receiving card, the receiving card is connected with the LED display screen, and the signal source is transmitted to the transmitting card through the test equipment to enable the LED display screen to display, so that the test of the transmitting card is realized.
In yet another aspect, a test system provided by an embodiment of the present invention includes: a test apparatus as hereinbefore described; the receiving card comprises a first data interface and a second data interface, wherein the first data interface is connected with the first receiving card test interface, and the second data interface is connected with the second receiving card test interface.
The test system in this embodiment is that the test device connects the receiving card through the first receiving card test interface and the second receiving card test interface to form a channel, the test device sends a data packet through the first receiving card test interface, the second receiving card test interface receives the data packet, and the error rate can be calculated by comparing the difference between the sent data packet and the received data packet, thereby realizing quantification of communication quality.
In summary, the above technical solution may have the following advantages or beneficial effects: the embedded processor is connected with the transmitting card circuit and the receiving card test interface, so that the test equipment can be directly connected with the receiving card, and the test equipment transmits a signal source to the receiving card to enable the LED display screen to display, thereby realizing the detection of the receiving card and simplifying a receiving card test system. And secondly, the test equipment is connected with the receiving card, the test equipment sends the data packet, and the receiving card judges whether the receiving card responds after receiving the data packet, so that the test of the receiving card in the passage is realized, and the receiving card with a problem in the passage is further positioned. In addition, connect the sending card through test equipment, send the card and connect the receiving card, the receiving card is connected the LED display screen, makes the LED display screen show through test equipment transmission signal source to sending card to realize sending the test of card. Furthermore, the test equipment is connected with the receiving card through the first receiving card test interface and the second receiving card test interface to form a passage, the test equipment sends a data packet through the first receiving card test interface, the second receiving card test interface receives the data packet, and the error rate can be calculated by comparing the difference between the sent data packet and the received data packet, so that the quantification of the communication quality is realized.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a test system according to a first embodiment of the present invention.
Fig. 2 is a schematic diagram of a structure of the test apparatus shown in fig. 1.
Fig. 3 is another schematic structural diagram of a test apparatus according to a first embodiment of the present invention.
Fig. 4 is a schematic structural diagram of another test system according to the first embodiment of the present invention.
Fig. 5 is another schematic structural diagram of a test apparatus according to the first embodiment of the present invention.
Fig. 6 is a schematic diagram of another structure of a testing apparatus according to the first embodiment of the present invention.
Fig. 7 is a schematic structural diagram of a test apparatus according to a first embodiment of the present invention.
Fig. 8 is a schematic structural diagram of a test system according to a second embodiment of the present invention.
Fig. 9 is a schematic diagram of a structure of the test apparatus shown in fig. 8.
Fig. 10 is a schematic structural diagram of a test system according to a third embodiment of the present invention.
FIG. 11 is a schematic diagram of a configuration of the test apparatus shown in FIG. 10.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
[ First embodiment ]
Referring to fig. 1, a test system according to a first embodiment of the present invention includes: test apparatus 100 and a plurality of receiver cards 200, the plurality of receiver cards 200 being serially connected (or cascaded) with test apparatus 100.
As shown in fig. 2, test apparatus 100 includes, for example, an embedded processor 110, a transmit card circuit 120, and a receive card test interface 130. The transmit card circuit 120 is coupled to the embedded processor 110, and the receive card test interface 130 is coupled to the transmit card circuit 120. The embedded processor 110 is, for example, ARM (Advanced RISC Machines), which has the characteristics of small volume, low power consumption, low cost, high performance, etc., and can control the test equipment to work; the receiving card test interface 130 is, for example, an ethernet interface, a fiber optic interface, or a coaxial cable interface, but the embodiment of the invention is not limited thereto.
Specifically, referring to fig. 3, the transmission card circuit 120 includes, for example: the programmable logic device 122 and the first nonvolatile memory 123, the first nonvolatile memory 123 connects the embedded processor 110, the programmable logic device 122 connects the first nonvolatile memory 123 and the embedded processor 110, and the receiving card test interface 130 connects the programmable logic device 122. The Programmable logic device 122 is, for example, a Field-Programmable gate array (Field-Programmable GATE ARRAY, FPGA); the first nonvolatile memory 123 is, for example, flash (Flash EEPROM), but the embodiment of the invention is not limited thereto.
In this way, when the channel test is performed on the receiver card 200 in the above-described test system, the receiver card 200 is connected to the test apparatus 100, and a plurality of receiver cards 200 are connected in series (or referred to as a cascade), for example. The operator controls the test device 100 to send a data packet to the receiving card 200, and after the receiving card 200 receives the data packet, returns a response to the test device 100, and after the data packet is transmitted to a Zhang Jieshou card 200, the test device 100 does not receive the response, so that the communication of locating the receiving card 200 is problematic, and the operator checks the receiving card 200. By the system, the path test is realized, and the receiving card with the problem in the path can be positioned.
Referring to fig. 4, another test system provided in an embodiment of the present invention includes: test device 100, receiving card 200 and LED display 300, test device 100 connects receiving card 200, and receiving card 200 connects LED display 300. The test apparatus 100 is the test apparatus 100 described above. The LED display 300 herein includes, for example, at least one LED light panel. Specifically, in the test system, the receiving card 200 is detected, a test instruction is sent by the embedded processor 110 in the test device 100, the standard test image of the receiving card 200 is called to be displayed on the LED display screen 300, and whether the receiving card 200 can work normally is detected by judging whether the test image on the LED display screen 300 is displayed normally. When the test image on the LED display 300 is displayed normally, it indicates that the receiving card 200 can work normally; when the test image on the LED display 300 is displayed abnormally, it indicates that the receiving card 200 cannot function properly. The standard test image of the receiving card 200 is, for example, a pure color image and a line image of red, green, blue, etc., but the embodiment of the invention is not limited thereto. In addition, the self-defined image or video can be called by the embedded processor 110 in the test device 100, processed by the programmable logic device 122, and then sent to the LED display screen 300 for display through the receiving card 200, and whether the receiving card 200 can work normally is detected by judging whether the test image on the LED display screen 300 is displayed normally or not.
Specifically, referring to fig. 5, the test apparatus 100 provided in the embodiment of the present invention further includes a microprocessor 121, where the microprocessor 121 is connected to the embedded processor 110, the programmable logic device 122 is connected to the microprocessor 110 and the embedded processor 110, the receiving card test interface 130 is connected to the programmable logic device 122, and the first nonvolatile memory 123 is connected to the microprocessor 121 and the programmable logic device 122. The microprocessor 121 is for example an MCU (Micro Control Unit ); the Programmable logic device 122 is, for example, a Field-Programmable gate array (Field-Programmable GATE ARRAY, FPGA); the first nonvolatile memory 123 is, for example, flash (Flash EEPROM), but the embodiment of the invention is not limited thereto. Here, two nonvolatile memories may be provided, and the microprocessor 121 and the programmable logic device 122 may be connected to each other.
Referring to fig. 6, the test apparatus 100 provided in the embodiment of the present invention further includes a second nonvolatile memory 150 and/or an input source interface 140, where the second nonvolatile memory 150 and the input source interface 140 are connected to the embedded processor 110, the input source interface 140 is, for example, a USB (Universal Serial Bus ) interface, specifically, for example, a USB2.0 interface, and a USB3.0 interface, and the second nonvolatile memory 150 is, for example, a ROM (Read-only memory) for storing data. Specifically, the test apparatus 100 may input a data source such as an image, a video, etc. through the input source interface 140, and the test apparatus 100 may also store the input data source in the second nonvolatile memory 150. Multiple ways of video source input are provided through the input source interface 140 and the second non-volatile memory 150, making use more convenient for the user.
It should be noted that, the test apparatus 100 may further generate and output a test screen with a corresponding size according to the resolution size input by the user, where the test screen includes, for example: the gray level display device comprises a pure-color picture, a gradual change picture and a grid line picture, wherein the pure-color picture supports to select 256 gray levels of 0-255, the gradual change supports gray level gradual change of 0-32, 0-64, 0-128 and 0-255, the grid lines are white lines, the gray level of 0-255 can be set, and the interval between the two grid lines can be set according to the actual needs of a user.
Referring to fig. 7, the test apparatus 100 provided in the embodiment of the present invention further includes a touch screen 160, where the touch screen 160 is connected to the embedded processor 110, and an operator may perform control operations on the test apparatus 100 through the touch screen 160 and visualize the operations. The touch screen 160 is, for example, an LCD touch screen, which provides a simple, convenient, natural way of human-machine interaction.
[ Second embodiment ]
Referring to fig. 8, a test system according to a second embodiment of the present invention includes: test apparatus 100, receiving card 200, wherein receiving card 200 includes a first data interface 202 and a second data interface 204. The first data interface 202 and the second data interface 204 are, for example, ethernet interfaces, fiber optic interfaces, coaxial cable interfaces, etc.
As shown in fig. 9, the test apparatus 100 shown in fig. 8 includes: the device comprises an embedded processor 110, a microprocessor 121, a programmable logic device 122, a first nonvolatile memory 122, a first receiving card test interface 132 and a second receiving card test interface 134, wherein the microprocessor 121 is connected with the embedded processor 110, the programmable logic device 122 is connected with the microprocessor 110 and the embedded processor 110, the first nonvolatile memory 123 is connected with the microprocessor 121 and the programmable logic device 122, and the first receiving card test interface 132 and the second receiving card test interface 134 are respectively connected with the programmable logic device 122. The embedded processor 110 is, for example, ARM (Advanced RISC Machines), which has the characteristics of small volume, low power consumption, low cost, high performance, etc., and can control the test equipment to work; the microprocessor 121 is for example an MCU (Micro Control Unit ); the Programmable logic device 122 is, for example, a Field-Programmable gate array (Field-Programmable GATE ARRAY, FPGA); the first nonvolatile memory 123 is, for example, flash (Flash EEPROM), but the embodiment of the invention is not limited thereto.
In the above test system, the bit error rate detection is performed, specifically, the first data interface 202 of the receiving card 200 is connected to the first receiving card test interface 132 of the test device 100, the second data interface 204 of the receiving card 200 is connected to the second receiving card test interface 134 of the test device 100, the test device 100 and the receiving card 200 form a path connection, and the receiving card 200 may be multiple. In a specific application scenario, after an operator builds an LED display screen, all receiving cards 200 connected by a network port are cascaded and connected with test equipment 100 to form a channel, the operator controls the test equipment to send a plurality of data packets through a first receiving card test interface 132, the data packets are returned to the test equipment 100 after being transmitted by the receiving cards 200, the test equipment 100 receives the data packets through a second receiving card test interface 134, and the error rate is obtained by calculating the number of the sent data packets and the received data packets, and the specific calculation formula is as follows: bit error rate= (number of transmitted packets-number of received packets)/number of transmitted packets. By the test system and the test mode, the communication quality of the receiving card channel can be detected, and the communication quality can be quantified.
In addition, the test system may further test the path of the receiving card 200, and when there are a plurality of receiving cards 200, specifically, the operator controls the test device 100 to send data packets to the receiving card 200 through the first receiving card test interface 132 and the second receiving card test interface 134, and after the receiving card 200 receives the data packets, returns a response to the test device 100, and after the data packets are transmitted to a Zhang Jieshou card 200, the test device 100 does not receive the response, so that there is a problem in locating the communication of the receiving card 200, and the operator checks the receiving card 200. By detecting the receiving cards 200 in the receiving card path in this way, two receiving cards 200 can be detected at the same time, and the detection efficiency of the receiving cards 200 in the receiving card path is greatly improved. Further, the test apparatus 100 may further be provided with a plurality of receiving card test interfaces for simultaneously testing a plurality of receiving cards, thereby further improving the detection efficiency.
[ Third embodiment ]
Referring to fig. 10, a test system according to a third embodiment of the present invention includes: the test device 100, the transmitting card 400, the receiving card 200 and the LED display screen 300, wherein the transmitting card 400 is connected with the test device 100, the receiving card 200 is connected with the transmitting card 400, and the LED display screen 300 is connected with the receiving card 200.
As shown in fig. 11, the test apparatus 100 includes: the device comprises an embedded processor 110, a microprocessor 121, a programmable logic device 122, a first nonvolatile memory 122, a receiving card test interface 130, an output selection circuit 170 and a transmitting card test interface 180, wherein the microprocessor 121 is connected with the embedded processor 110, the programmable logic device 122 is connected with the microprocessor 110 and the embedded processor 110, the first nonvolatile memory 123 is connected with the microprocessor 121 and the programmable logic device 122, the receiving card test interface 130 is connected with the programmable logic device 122, the output selection circuit 170 is connected between the embedded processor 110 and the programmable logic device 122, and the transmitting card test interface 180 is connected with the output selection circuit 170. The output selection circuit 170 is HDMI SWITCH (High Definition Multimedia INTERFACE SWITCH, high-definition multimedia interface switch), for example, to realize single-output selection when a single-input multi-output interface is used; or the output selection circuit 170 is, for example, an HDMI (High Definition Multimedia Interface, high-definition multimedia interface) one-to-two output circuit, realizing single input and multiple output, and copying the signal source of the single input to realize multiple output. The embedded processor 110 is, for example, ARM (Advanced RISC Machines), which has the characteristics of small volume, low power consumption, low cost, high performance, etc., and can control the test equipment to work; the microprocessor 121 is for example an MCU (Micro Control Unit ); the Programmable logic device 122 is, for example, a Field-Programmable gate array (Field-Programmable GATE ARRAY, FPGA); the first nonvolatile memory 123 is, for example, flash (Flash EEPROM), but the embodiment of the invention is not limited thereto.
In the above test system, the test device 100 is controlled by the operator to send the test image to the sending card 400 through the embedded processor 110, the sending card 400 transmits the test image to the receiving card 200 to display the LED display screen, and whether the sending card 400 can work normally is detected by judging whether the test image on the LED display screen 300 is displayed normally. When the test image on the LED display 300 is displayed normally, it means that the transmitting card 400 can work normally; when the test image on the LED display 300 is displayed abnormally, it means that the transmitting card 400 cannot operate normally. Of course, in this test system, the receiving card 200 needs to be guaranteed to work properly. Through the test system and the test mode, the test equipment can replace a PC, and off-line detection of the sending card is realized.
In addition, it should be understood that the foregoing embodiments are merely exemplary illustrations of the present invention, and the technical solutions of the embodiments may be arbitrarily combined and matched without conflict in technical features, contradiction in structure, and departure from the purpose of the present invention.
In the several embodiments provided in the present invention, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the partitioning of elements is merely a logical functional partitioning, and there may be additional partitioning in actual implementation, e.g., multiple elements or components may be combined or integrated into another system, or some features may be omitted, or not implemented. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit/module in the embodiments of the present invention may be integrated in one processing unit/module, or each unit/module may exist alone physically, or two or more units/modules may be integrated in one unit/module. The integrated units/modules may be implemented in hardware or in hardware plus software functional units/modules.
The integrated units/modules implemented in the form of software functional units/modules described above may be stored in a computer readable storage medium. The software functional units described above are stored in a storage medium and include instructions for causing one or more processors of a computer device (which may be a personal computer, a server, or a network device, etc.) to perform some steps of the methods described in the embodiments of the present application.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A test apparatus, comprising:
An embedded processor;
a transmitting card circuit electrically connected to the embedded processor; and
A receiving card test interface electrically connected with the transmitting card circuit;
the test equipment can generate and output a test picture with a corresponding size according to the resolution input by a user;
The test equipment is used for receiving a plurality of receiving data packets through the receiving card test interface, and calculating the error rate according to the number of the sending data packets and the receiving data packets.
2. The test apparatus of claim 1, wherein the transmit card circuit comprises:
The microprocessor is electrically connected with the embedded processor;
The programmable logic device is electrically connected with the microprocessor and the embedded processor, and the receiving card test interface is connected with the programmable logic device;
and the first nonvolatile memory is electrically connected with the microprocessor and the programmable logic device.
3. The test apparatus of claim 2, further comprising: the second nonvolatile memory and/or the input source interface are connected with the embedded processor.
4. The test apparatus of claim 2, further comprising:
And the touch screen is electrically connected with the embedded processor.
5. The test apparatus of claim 2, wherein the receiver card test interface comprises a first receiver card test interface and a second receiver card test interface, the first receiver card test interface and the second receiver card test interface electrically connected to the programmable logic device, respectively.
6. The test apparatus of claim 2, further comprising:
An output selection circuit electrically connected between the embedded processor and the programmable logic device;
and the transmitting card test interface is electrically connected with the output selection circuit.
7. A test system, comprising:
the test device of any one of claims 1 to 6;
and the receiving card is electrically connected with the receiving card test interface of the test equipment.
8. The test system of claim 7, further comprising: and the LED display screen is electrically connected with the receiving card.
9. A test system, comprising:
The test apparatus of claim 6;
a transmitting card electrically connected with the transmitting card test interface;
A receiving card electrically connected with the transmitting card;
And the LED display screen is electrically connected with the receiving card.
10. A test system, comprising:
The test apparatus of claim 5;
The receiving card comprises a first data interface and a second data interface, wherein the first data interface is connected with the first receiving card test interface, and the second data interface is connected with the second receiving card test interface.
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| CN201910786191.1A CN112415296B (en) | 2019-08-23 | 2019-08-23 | Test equipment and test system |
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