CN1124030C - 在数字信号接收器中选择性地转换时钟频率的装置 - Google Patents

在数字信号接收器中选择性地转换时钟频率的装置 Download PDF

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CN1124030C
CN1124030C CN99127055A CN99127055A CN1124030C CN 1124030 C CN1124030 C CN 1124030C CN 99127055 A CN99127055 A CN 99127055A CN 99127055 A CN99127055 A CN 99127055A CN 1124030 C CN1124030 C CN 1124030C
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clock frequency
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locked loop
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孙泰龙
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Samsung Electronics Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/015—High-definition television systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/46—Receiver circuitry for the reception of television signals according to analogue transmission standards for receiving on more than one standard at will
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
    • H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/41—Structure of client; Structure of client peripherals
    • H04N21/426—Internal components of the client ; Characteristics thereof
    • H04N21/42607—Internal components of the client ; Characteristics thereof for processing the incoming bitstream
    • H04N21/4263—Internal components of the client ; Characteristics thereof for processing the incoming bitstream involving specific tuning arrangements, e.g. two tuners
    • H04N21/42638—Internal components of the client ; Characteristics thereof for processing the incoming bitstream involving specific tuning arrangements, e.g. two tuners involving a hybrid front-end, e.g. analog and digital tuners
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/4302—Content synchronisation processes, e.g. decoder synchronisation
    • H04N21/4305—Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
    • H04N21/4402—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display
    • H04N21/440218—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display by transcoding between formats or standards, e.g. from MPEG-2 to MPEG-4
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • H04N7/0117—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving conversion of the spatial resolution of the incoming video signal
    • H04N7/0122—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving conversion of the spatial resolution of the incoming video signal the input and the output signals having different aspect ratios

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Synchronizing For Television (AREA)

Abstract

一种在数字信号接收器中选择性地转换时钟频率的装置，包括：第一锁相环(PLL)；第二锁相环；切换部分，按照预定控制信号从一个所述锁相环中选择时钟频率；控制器，控制切换部分，以选择和输出对应于输入数字信号的帧速率的时钟频率。所述帧速率被检测，并且对应于检测后的帧速率的时钟频率仅被提供到用于相应信号处理的块。此外，当输入模拟NTSC信号时，相应时钟频率仅被提供到与相应信号处理有关的块。因此可防止视频信号处理中的遗漏和冗余。

Description

在数字信号接收器中选择 性地转换时钟频率的装置
技术领域
本发明涉及一种数字信号接收器，尤其涉及一种在数字信号接收器中选择性地转换时钟频率的装置，用于检测输入信号的帧速率并且提供对应于帧速率的时钟频率。
背景技术
在数字电视(TV)广播中，从广播电台发射到TV接收器的信号是数字信号，并且在TV中的信号也是数字信号，因此与使用模拟信号时的情况相比，会取得清楚的图象和清晰的声音。数字TV可利用18种视频广播标准中的一种来提供图象，这18种视频广播标准的范围为从具有与传统模拟NTSC(National Television System Committee，国家电视***委员会)制式相同的640×480的分辨率的标准TV(SDTV)制式，到具有七倍于SDTV制式的1920×1080的分辩率的高清晰度电视(HDTV)制式。并且数字TV采用DOLBYAC-3制式来产生清晰的立体声。
数字TV还利用了高效的数据压缩技术，其压缩率高于50∶1，因此广播电台可以提供更多的信道。而且，因为数字TV也支持双向传输，所以数字TV可提供与模拟TV完全不同的服务。
图1是数字TV接收器的方框图。图1中的数字TV接收器包括天线100、调谐器102、中频(IF)模块104、信道解码器106、传输流(transport stream，TS)解码器108、音频解码器110、音频信号处理器112、扬声器114、视频解码器116、在屏图形混合器(on-screen graphic mixer，OSGM)118、视频信号处理器120、阴极射线管(cathode ray tube，CRT)122和微处理器124。
调谐器102在微处理器124的控制下，从通过天线接收的广播信号中选择一个射频(radio frequency，RF)信道。IF模块104从调谐器102接收IF频率并将该IF信号转换成基带信号。信道解码器106对来自IF模块104的基带信号进行信道解码以便生成数据位流。TS解码器108从信道解码器106的数据位流中分离音频数据、视频数据和附加数据。音频解码器110按照MPEG标准或Dolby AC-3标准接收音频数据并解码该音频数据，音频信号处理器112将解码的音频信号输出到扬声器114中。
视频解码器116按照MPEG标准接收来自TS解码器108的视频数据并且解码该视频数据，而OSGM118在微处理器124的控制下将OSG数据和解码的视频数据进行混合。视频信号处理器120接收来自OSGM118的信号、处理该信号并且将处理后的信号输出到CRT 122。
具有以上结构的数字TV接收器可以有用于模拟信号的额外的调谐器。美国电视***委员会(American Television System Committee，ATSC)标准是一种数字广播制式，它采用用于数字信号的各种帧速率，包括60Hz、59.94Hz、30Hz、29.97Hz、24Hz和23.97Hz。因此，有必要按照帧速率选择性地转换时钟频率，从而防止信号处理中的遗漏或冗余(omission or redundancy)。
发明内容
本发明的一个目的是提供一种在数字信号接收器中选择性地转换时钟频率的装置，它能提供基于帧速率的时钟频率。
为达到本发明的以上目的，提供了一种在数字信号接收器中选择性地转换时钟频率的装置，包括：第一锁相环(PLL)，用于产生第一时钟频率，和第二锁相环，用于产生第二时钟频率，其特征在于：所述第一锁相环和所述第二锁相环并联；切换部分，用于按照预定控制信号从所述第一和第二锁相环中的一个锁相环中选择一时钟频率；及控制器，用于控制所述切换部分，以便选择和输出对应于输入数字信号的帧速率的时钟频率。
最好，第一锁相环产生74.25MHz的时钟频率而第二锁相环产生74.175MHz的时钟频率。最好，当输入数字信号的帧速率60Hz、30Hz或24Hz时，控制器控制切换部分从第一锁相环中选择时钟频率，而当输入数字信号的帧速率是59.94Hz、29.97Hz或23.97Hz时，控制器控制切换部分从第二锁相环中选择时钟频率。
附图说明
通过参照附图详细描述本发明的优选实施例，本发明的以上目的将会更明白，附图中：
图1是数字电视(TV)接收器的方框图；
图2是按照本发明的具有时钟频率转换装置的数字TV接收器的方框图；及
图3是图2的锁相环(PLL)的详细电路图。
具体实施方式
在图2中，显示了按照本发明的具有时钟频率转换装置的数字信号接收器，标号200代表转输流(TS)解码器、标号202代表视频解码器、标号204代表模数转换器(analog-to-digital converter，ADC)、标号206代表格式转换器、标号208代表锁相环(PLL)、标号210代表缓冲器、标号212代表控制器、标号214代表在屏图形混合器(OSGM)，以及标号216代表振荡器(OSC)。
ADC 204将NTSC信号转换成数字信号。格式转换器206将来自视频解码器202的视频数据VIDEO(视频)和来自ADC 204的视频数据VIDEO转换成预定显示格式。PLL 208包括产生不同时钟频率的第一和第二PLL，并且输出在控制器212的控制下选择的时钟频率。
控制器212检测来自格式转换器206的帧速率并且控制PLL 208，以使对应于检测帧速率的时钟频率从PLL 208输出。另外，当模拟NTSC信号输入时，控制器212控制连接到PLL 208的缓冲器210，以使时钟频率仅被施加到与模拟NTSC信号的处理有关的块上。也就是说，当视频数据通过ADC 204被接收时，没有必要将时钟频率CLOCK(时钟)提供到视频解码器202。因此，控制器212控制缓冲器210，以使时钟频率仅被施加给格式转换器206和OSGM214。
图3是图2的PLL 208的详细电路图。如图3所示，PLL 208包括第一PLL 208a、第二PLL 208b和切换部分208c。第一PLL 208a包括相位比较器302、低通滤波器(LPF)304、电压控制振荡器(voltage controlled oscillator，VCO)306和1/N的分频器308。第二PLL 208b包括相位比较器402、低通滤波器(LPF)404、VCO 406和1/N分频器408。在这个实施例中，第一PLL 208a产生74.25MHz的时钟频率以及第二PLL 208b产生74.175MHz的时钟频率。切换部分208c根据控制器212输出的选择信号选择性地输出74.25MHz或74.175MHz的时钟频率。
根据ATSC标准，包括60Hz、59.94Hz、30Hz、29.94Hz、24Hz和23.97Hz的数字信号的各种帧速率被分成两组中的一组：第一组包括60Hz、30Hz和24Hz，而第二组包括59.94Hz、29.94Hz和23.97Hz。
当输入数字信号具有包括在第一组中的帧速率时，控制器212控制切换部分208c，以便从第一PLL 208a选择性地输出74.25MHz的时钟频率。其中，当输入数字信号具有包括在第二组中的帧速率时，控制器212控制切换部分208c，以便从第二PLL 208b选择性地输出74.175MHz的时钟频率。
而且，当具有包括在第二组中的59.94Hz的NTSC信号通过ADC 204被输入时，控制器212控制切换部分208c，以便从第二PLL 208b选择74.175MHz的时钟频率。在这种情况下，视频解码器202没有运作。因此，控制器212控制缓冲器210，以便阻止(block)将时钟频率CLOCK提供到视频解码器202，从而使时钟频率CLOCK仅被提供到格式转换器206和OSGM 214。
正如以上的描述，输入数字信号的帧速率被检测，并且对应于检测后的帧速率的时钟频率仅被提供到用于相应信号处理的块。此外在输入模拟NTSC信号的情况下，相应的时钟频率仅被提供到用于相应信号处理的块。因此，可防止在视频信号处理中的遗漏或冗余。
虽然上面已参照本发明的优选实施例对本发明进行了特定的图示和描述，但应当理解，在不偏离由附属权利要求书所确定的本发明的精神和范围的情况下，可由本领域普通技术人员对本发明的形式和细节进行各种修改。

Claims (3)

1.一种在数字信号接收器中选择性地转换时钟频率的装置，包括：第一锁相环(PLL)，用于产生第一时钟频率，和第二锁相环，用于产生第二时钟频率，其特征在于：
所述第一锁相环和所述第二锁相环并联；
切换部分，用于按照预定控制信号从所述第一和第二锁相环中的一个锁相环中选择一时钟频率；及
控制器，用于控制所述切换部分，以便选择和输出对应于输入数字信号的帧速率的时钟频率。
2.如权利要求1所述的装置，其中所述第一锁相环产生74.25MHz的时钟频率，而所述第二锁相环产生74.175MHz的时钟频率。
3.如权利要求1所述的装置，其中当所述输入数字信号的帧速率是60Hz、30Hz或24Hz时，所述控制器控制所述切换部分，以便从所述第一锁相环选择时钟频率，而当所述输入数字信号的帧速率是59.94Hz、29.97Hz或23.97Hz时，所述控制器控制所述切换部分，以便从所述第二锁相环选择时钟频率。
CN99127055A 1998-12-28 1999-12-24 在数字信号接收器中选择性地转换时钟频率的装置 Expired - Fee Related CN1124030C (zh)

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