CN112397476A - 半导体器件 - Google Patents

半导体器件 Download PDF

Info

Publication number
CN112397476A
CN112397476A CN202010451123.2A CN202010451123A CN112397476A CN 112397476 A CN112397476 A CN 112397476A CN 202010451123 A CN202010451123 A CN 202010451123A CN 112397476 A CN112397476 A CN 112397476A
Authority
CN
China
Prior art keywords
lead
segment
bump
leads
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010451123.2A
Other languages
English (en)
Inventor
高浚泳
金世年
卢永勋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN112397476A publication Critical patent/CN112397476A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H01L21/4875—Connection or disconnection of other leads to or from bases or plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145—Organic substrates, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49531—Additional leads the additional leads being a wiring board
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/1316—Iron [Fe] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1415—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/14153—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry with a staggered arrangement, e.g. depopulated array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1415—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/14154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H01L2224/14155—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1605—Shape
    • H01L2224/16057—Shape in side view
    • H01L2224/16058—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81439—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81444—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/8146—Iron [Fe] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)

Abstract

一种半导体器件包括基板、位于所述基板上的半导体芯片以及位于所述基板和所述半导体芯片之间的第一引线和第二引线。所述第一引线和所述第二引线沿平行于所述基板的顶表面的第一方向从基板的边缘朝向所述半导体芯片下方延伸。所述第一引线包括第一凸块连接件和第一段。所述第二引线包括第二凸块连接件。所述第一凸块连接件在所述第一方向上与所述第二凸块连接件间隔开。所述第一引线的所述第一段在第二方向上与所述第二凸块连接件间隔开。所述第二方向平行于所述基板的所述顶表面并且垂直于所述第一方向。所述第一引线的所述第一段的厚度小于所述第二凸块连接件的厚度。

Description

半导体器件
相关申请的交叉引用
本申请要求于2019年8月14日在韩国知识产权局提交的韩国专利申请No.10-2019-0099316的优先权，其全部内容通过引用合并于此。
技术领域
本发明构思涉及半导体器件，更具体地，涉及包括精细节距引线的半导体器件。
背景技术
由于电子技术的发展，近年来，半导体器件的规模迅速缩小。对电子设备的功能的需求增加了电子设备中集成电路(IC)的引线的数量。为了在有限的区域内制造更多的引线，已经进行了研究以缩窄相邻引线之间的间隔。
发明内容
本发明构思的一些示例实施例提供了防止和/或减少相邻引线之间的电流泄漏的精细引线结构。
本发明构思的目的不限于上述实施例，并且根据以下描述，本领域技术人员将清楚地理解以上未提及的其他目的。
根据本发明构思的一些示例实施例，一种半导体器件可以包括：基板；半导体芯片，所述半导体芯片位于所述基板上；以及第一引线和第二引线，所述第一引线和所述第二引线位于所述基板和所述半导体芯片之间。所述第一引线和所述第二引线可以沿平行于所述基板的顶表面的第一方向在所述基板上延伸到所述半导体芯片下方。所述第一引线可以包括第一凸块连接件和连接到所述第一凸块连接件的第一段。所述第二引线可以包括第二凸块连接件。所述第一凸块连接件可以在所述第一方向上与所述第二凸块连接件间隔开。所述第一引线的所述第一段可以在第二方向上与所述第二凸块连接件间隔开。所述第二方向平行于所述基板的所述顶表面并且垂直于所述第一方向。所述第一引线的所述第一段的厚度小于所述第二凸块连接件的厚度。
根据本发明构思的一些示例实施例，一种半导体器件可以包括：基板；半导体芯片，所述半导体芯片位于所述基板上；多根第一引线，所述多根第一引线位于所述半导体芯片与所述基板之间；以及多根第二引线，所述多根第二引线分别位于所述多根第一引线中的相邻的第一引线之间。所述第一引线和所述第二引线可以沿平行于所述基板的顶表面的第一方向在所述基板上延伸到所述半导体芯片下方。所述第一引线可以比所述第二引线在所述第一方向上延伸得更远。每个所述第一引线可以包括第一凸块连接件，并且每个所述第二引线可以包括第二凸块连接件。所述第一凸块连接件和所述第二凸块连接件可以沿平行于所述基板的所述顶表面且垂直于所述第一方向的第二方向以之字形方式布置。每个所述第一引线可以包括位于相邻的第二凸块连接件之间的第一段。每个所述第一引线的所述第一段的顶表面的水平高度可以低于每个所述第二凸块连接件的顶表面的水平高度。
根据本发明构思的一些示例实施例，一种半导体器件可以包括：基板；半导体芯片，所述半导体芯片位于所述基板上；第一引线和第二引线，所述第一引线和所述第二引线位于所述基板和所述半导体芯片之间；阻焊层，所述阻焊层位于所述第一引线的一部分和所述第二引线的一部分上；以及底部填充层，所述底部填充层位于所述基板的一部分、所述第一引线的一部分、所述第二引线的一部分和所述阻焊层的一部分上。所述第一引线和所述第二引线可以沿平行于所述基板的顶表面的第一方向在所述基板上延伸到所述半导体芯片下方。所述第一引线可以比所述第二引线在所述第一方向上延伸得更远。所述第一引线和所述第二引线可以在平行于所述基板的所述顶表面且垂直于所述第一方向的第二方向上彼此间隔开。所述第一引线可以包括第一凸块连接件、第一段和第二段，所述第一段位于所述第二段和所述第一凸块连接件之间。所述第二引线可以包括第二凸块连接件。介电图案可以位于所述第一引线的所述第一段上。所述第一凸块连接件可以在所述第一方向上与所述第二凸块连接件间隔开。所述第一引线的所述第一段可以在所述第二方向上与所述第二凸块连接件间隔开。所述第一引线的所述第一段的第一端部可以与所述半导体芯片垂直交叠，并且所述第一引线的所述第一段的第二端部可以与所述阻焊层垂直交叠。所述第一引线的所述第一段的厚度可以小于所述第二凸块连接件的厚度、所述第一凸块连接件的厚度以及所述第一引线的所述第二段的厚度。
附图说明
图1A示出了根据本发明构思的一些示例实施例的半导体器件的俯视图。
图1B示出了沿图1A的线I-I'截取的截面图。
图1C示出了沿图1A的线II-II'截取的截面图。
图1D示出了示出图1C的部分“aa”的放大图。
图2A示出了根据本发明构思的一些示例实施例的半导体器件的俯视图。
图2B示出了沿图2A的线I-I'截取的截面图。
图2C示出了沿图2A的线II-II'截取的截面图。
图2D示出了示出图2C的部分“bb”的放大图。
图3A和图3B示出了根据本发明构思的一些示例实施例的半导体器件的分别沿图2A的线I-I'和线II-II'截取的截面图。
图4A至图4D示出了根据本发明构思的一些示例实施例的制造半导体器件的方法的截面图。
图5A至图5D示出了根据本发明构思的一些示例实施例的制造半导体器件的方法的截面图。
具体实施方式
现在下面将参照附图描述根据本发明构思的半导体器件。
图1A示出了根据本发明构思的一些示例实施例的半导体器件的俯视图。图1B示出了沿图1A的线I-I'截取的截面图。图1C示出了沿图1A的线II-II'截取的截面图。图1D示出了示出图1C的部分“aa”的放大图。
参照图1A至图1D，根据本发明构思的一些实施例的半导体器件1000可以包括基板10、多根第一引线20、多根第二引线21、多个阻焊层(solder mask)40、底部填充层50和半导体芯片60。
基板10可以包括例如印刷电路板(PCB)或柔性膜，然而本发明构思不限于此。柔性膜可以包括例如聚酰亚胺。
多个阻焊层40可以覆盖第一引线20的一部分和第二引线21的一部分。多个阻焊层40可以防止和/或减少在将半导体芯片60安装在基板10上时的热处理期间在第一引线20和第二引线21中发生氧化和/或短路。
多个凸块30和31可以设置在布置在半导体芯片60的下部的焊盘(未示出)上。多个凸块30和31可以包括例如金(Au)。多个凸块30和31可以包括第一凸块30和第二凸块31。当在俯视图中观察时，第一凸块30和第二凸块31可以以之字形方式布置。在一些实施例中，第一凸块30可以布置为沿着第一轴线基本共线延伸，并且第二凸块31可以布置为沿着偏离第一轴线的第二轴线基本共线延伸。第一凸块30和第二凸块31可以分别接触第一引线20和第二引线21。第一凸块30和第二凸块31可以用作将半导体芯片60连接到第一引线20和第二引线21的连接端子。
底部填充层50可以位于基板10、第一引线20、第二引线21和阻焊层40上，和/或部分地覆盖基板10、第一引线20、第二引线21和阻焊层40。底部填充层50可以位于第一凸块30和第二凸块31之间的空间内，和/或填充第一凸块30和第二凸块31之间的空间。底部填充层50可以保护第一引线20、第二引线21、第一凸块30、第二凸块31和/或半导体芯片60免受外部环境的影响。
半导体芯片60可以包括集成电路(IC)。例如，半导体芯片60可以是显示驱动IC(DDI)。
第一引线20和第二引线21可以在基板10的顶表面上设置在相对边缘上。第一引线20和第二引线21均可以具有沿平行于基板10的顶表面的第一方向D1延伸的线性形状。每根第一引线20可以在第一方向D1上比每根第二引线21延伸得更远。例如，第一引线20可以具有在第一方向D1上与第二引线21的端部21E间隔开的端部20E。
第一引线20和第二引线21可以沿平行于基板10的顶表面并且垂直于第一方向D1的第二方向D2彼此间隔开并且彼此交替地设置。第一引线20的端部20E和第二引线21的端部21E可以沿第二方向D2以之字形方式布置。在一些实施例中，第一引线20的端部20E可以布置为沿在第二方向D2上的第一轴线基本共线延伸，并且第二引线21的端部21E可以布置为沿在第二方向D2上的第二轴线基本共线延伸，第二轴线在第一方向D1上偏离第一轴线。
第一引线20和第二引线21可以包括例如诸如铜(Cu)、金(Au)、银(Ag)和/或铁(Fe)的导电材料。
在本说明书中，术语“水平高度”可以表示从基板10的顶表面沿着垂直于基板10的顶表面的第三方向D3的高度。第一引线20的底表面可以位于与第二引线21的底表面的水平高度基本相同的水平高度。第一引线20的底表面和第二引线21的底表面可以位于与基板10的顶表面的水平高度相同或者比基板10的顶表面的水平高度高的水平高度。第一引线20在第二方向D2上的宽度202可以与第二引线21在第二方向D2上的宽度212基本相同。
第一引线20可以包括第一凸块连接件20a、第一段20b和第二段20c。第一凸块连接件20a可以对应于第一引线20的端部20E。第一引线20的第二段20c可以通过第一引线20的第一段20b与第一凸块连接件20a间隔开。当在俯视图中观察时，第一凸块连接件20a可以与半导体芯片60交叠(例如，在第三方向D3上)。第一引线20的第一段20b的一端可以与半导体芯片60交叠(例如，在第三方向D3上)，并且另一端可以与阻焊层40交叠(例如，在第三方向D3上)。第一引线20的第二段20c的一端可以与阻焊层40交叠(例如，在第三方向D3上)，并且第一引线20的第二段20c的另一端的顶表面被阻焊层40暴露和/或不与阻焊层40交叠(例如，在第三方向D3上)。
第一引线20的第一凸块连接件20a可以具有与第一凸块30接触的顶表面20at。第一凸块30在第一方向D1上的宽度可以小于第一凸块连接件20a在第一方向D1上的宽度。第一凸块30在第二方向D2上的宽度可以大于第一凸块连接件20a在第二方向D2上的宽度。第一凸块连接件20a的顶表面20at的至少一部分可以在第一凸块30的相对侧暴露。例如，在一些实施例中，第一凸块连接件20a的顶表面20at可以延伸到第一凸块30的相对侧之外，使得第一凸块连接件20a的顶表面20at的一部分在第三方向D3上不与第一凸块30交叠。
第一引线20的第一段20b的厚度t2可以小于第一凸块连接件20a的厚度t1，并且小于第一引线20的第二段20c的厚度t3。第一凸块连接件20a的厚度t1可以与第一引线20的第二段20c的厚度t3基本相同。
第一引线20的第一段20b的顶表面20bt的水平高度可以低于第一凸块连接件20a的顶表面20at的水平高度，并且低于第一引线20的第二段20c的顶表面20ct的水平高度。第一凸块连接件20a的顶表面20at的水平高度可以与第一引线20的第二段20c的顶表面20ct的水平高度基本相同。
第二引线21可以包括第二凸块连接件21a和第一段21b。第二凸块连接件21a可以对应于第二引线21的端部21E。第二引线21的第一段21b可以连接到第二凸块连接件21a。当在俯视图中观察时，第二凸块连接件21a可以与半导体芯片60交叠(例如，在第三方向D3上)。第二引线21的第一段21b的一端可以与半导体芯片60交叠(例如，在第三方向D3上)，并且第二引线21的第一段21b的另一端的顶表面被阻焊层40暴露和/或不与阻焊层40交叠(例如，在第三方向D3上)。
第二凸块连接件21a可以接触第二凸块31。第二凸块31在第一方向D1上的宽度和在第二方向D2上的宽度可以分别与第一凸块30在第一方向D1上的宽度和在第二方向D2上的宽度基本相同。第二凸块连接件21a在第一方向D1上的宽度可以与第一凸块连接件20a在第一方向D1上的宽度基本相同。第二凸块连接件21a的顶表面可以在第二凸块31的相对侧暴露。例如，在一些实施例中，第二凸块连接件21a的顶表面可以延伸到第二凸块31的相对侧之外，使得第二凸块连接件21a的顶表面的一部分在第三方向D3上不与第二凸块31交叠。
当在俯视图中观察时，第二凸块31与第一引线20的第一段20b之间的在第二方向D2上的距离ΔH1可以小于(例如，短于)第二凸块连接件21a与第一引线20的第一段20b之间的在第二方向D2上的距离ΔH2。第二凸块31在第一方向D1上的宽度ΔW1可以小于第一引线20的第一段20b在第一方向D1上的宽度ΔW2。
第二引线21可以具有沿第一方向D1一致的厚度ta。第二引线21的厚度ta可以与第一凸块连接件20a的厚度t1和第一引线20的第二段20c的厚度t3基本相同。
第一引线20的第一段20b的厚度t2可以小于第二凸块连接件21a的厚度ta。第一引线20的第一段20b的厚度t2可以在例如2μm到小于8μm的范围内。第二凸块连接件21a的厚度ta可以在例如8μm到10μm的范围内。
在一些实施例中，第二引线21的第二凸块连接件21a的顶表面21at与第一引线20的第一段20b的顶表面20bt之间的水平高度差可以为2μm或更大。
介电图案70可以设置在第一引线20的第一段20b上。介电图案70可以位于第一引线20的第一段20b的顶表面20bt上和/或覆盖第一引线20的第一段20b的顶表面20bt，并且还位于第一引线20的第一段20b的在第二方向D2上的相对侧表面上和/或覆盖第一引线20的第一段20b的在第二方向D2上的相对侧表面。介电图案70可以包括有机可焊性保护剂(OSP)。
介电图案70的顶表面70t的水平高度可以低于第二凸块连接件21a的顶表面21at的水平高度。
图2A示出了根据本发明构思的一些示例实施例的半导体器件的俯视图。图2B示出了沿图2A的线I-I'截取的截面图。图2C示出了沿图2A的线II-II'截取的截面图。图2D示出了示出图2C的部分“bb”的放大图。除了下面讨论的以外，已经参照图1A至图1D详细描述了本发明构思，因此，将省略进一步的说明。
参照图2A至图2D，半导体器件2000的第一引线20可以包括第一凸块连接件20a和第一段20b。第一凸块连接件20a可以对应于第一引线20的端部20E。第一引线20的第一段20b可以对应于除第一凸块连接件20a之外的其余部分。当在俯视图中观察时，第一引线20的第一段20b的一端可以与半导体芯片60交叠(例如，在第三方向D3上)，并且第一引线20的第一段20b的另一端的顶表面可以被阻焊层40暴露(例如，在第三方向D3上不与阻焊层40交叠)。
第一引线20的第一段20b的厚度t2可以小于第一凸块连接件20a的厚度t1。第一引线20的第一段20b的顶表面20bt的水平高度可以低于第一凸块连接件20a的顶表面20at的水平高度。
第二引线21可以包括第二凸块连接件21a和第一段21b。第二凸块连接件21a可以对应于第二引线21的端部21E。第二引线21的第一段21b可以对应于第二引线21的除第二凸块连接件21a之外的其余部分。第二引线21的第一段21b的一端可以与半导体芯片60交叠(例如，在第三方向D3上)，并且第二引线21的第一段21b的另一端的顶表面可以被阻焊层40暴露(例如，在第三方向D3上不与阻焊层40交叠)。
第二引线21的第一段21b的厚度tb可以小于第二凸块连接件21a的厚度ta。第二引线21的第一段21b的顶表面21bt的水平高度可以低于第二凸块连接件21a的顶表面21at的水平高度。
第二引线21的第一段21b的顶表面21bt可以位于与第一引线20的第一段20b的顶表面20bt的水平高度基本相同的水平高度处。
第一引线20的第一段20b的厚度t2可以小于第二凸块连接件21a的厚度ta。第一引线20的第一段20b的厚度t2可以在例如2μm到10μm的范围内。例如，第一引线20的第一段20b的厚度t2可以在8μm到10μm的范围内。
第二凸块连接件21a的厚度ta可以在例如10μm到16μm的范围内。在一些实施例中，第一引线20的第一段20b的厚度t2与第二引线21的第二凸块连接件21a的厚度ta之间可以存在2μm到8μm的差。
在一些实施例中，第一凸块连接件20a的顶表面20at(或者第二凸块连接件21a的顶表面21at)与第一引线20的第一段20b的顶表面20bt(或者第二引线21的第一段21b的顶表面21bt)之间的水平高度差可以为2μm或更大(例如，从2μm到8μm、从2μm到10μm)。
图3A和图3B示出了根据本发明构思的一些示例实施例的半导体器件的分别沿图2A的线I-I'和线II-II'截取的截面图。
参照图3A和图3B，半导体器件2001可以包括设置在第一引线20的第一段20b上以及也设置在第二引线21的第一段21b上的介电图案70。介电图案70可以位于第一引线20的第一段20b的顶表面上和/或覆盖第一引线20的第一段20b的顶表面，并且还位于第一引线20的第一段20b的在第二方向D2上的相对侧表面上和/或覆盖第一引线20的第一段20b的在第二方向D2上的相对侧表面。介电图案70可以位于第二引线21的第一段21b的顶表面上和/或覆盖第二引线21的第一段21b的顶表面，并且也可以位于第二引线21的第一段21b的在第二方向D2上的相对侧表面上和/或覆盖第二引线21的第一段21b的在第二方向D2上的相对侧表面。介电图案70的顶表面70t的水平高度可以低于第二凸块连接件21a的顶表面21at的水平高度。
图4A至图4D示出了沿图1A的线I-I'截取的截面图，以示出根据本发明构思的一些示例实施例的制造半导体器件的方法。
参照图4A，可以在基板10上形成金属层200。可以通过粘附层(未示出)将金属层200附着到基板10。可以在金属层200上形成具有多个开口(图4A中示出了多个开口中的一个开口)的第一掩模图案MSK1。可以通过使用第一掩模图案MSK1的第一蚀刻工艺P200图案化金属层200。
参照图4B，可以图案化金属层200，以形成多根第一引线20和多根第二引线21。之后，可以去除第一掩模图案MSK1。
参照图4C，可以形成暴露第一引线20的顶表面的第二掩模图案MSK2。第二掩模图案MSK2可以保护(例如，不暴露)第二引线21。可以执行第二蚀刻工艺P201以部分地蚀刻第一引线20。
参照图4D，可以部分地蚀刻第一引线20以形成第一引线20的第一段20b。第一引线20的第一段20b的厚度t2可以小于与其相邻的第二引线21的厚度ta。可以执行涂覆工艺以在第一引线20的第一段20b上形成介电图案70。可以去除第二掩模图案MSK2。
返回参照图1B和图1C，可以在第一引线20的一部分和第二引线21的一部分上形成多个阻焊层40。可以在基板10上安装半导体芯片60。在基板10上安装半导体芯片60的同时，第一凸块30可以与第一引线20的第一凸块连接件20a对准并且热压缩在第一引线20的第一凸块连接件20a上，并且第二凸块31可以与第二引线21的第二凸块连接件21a对准并且热压缩在第二引线21的第二凸块连接件21a上。可以形成底部填充层50以填充第一凸块30和第二凸块31之间的空间。
图5A至图5D示出了示出根据本发明构思的一些示例实施例的制造半导体器件的方法的截面图。
参照图5A，可以在基板10上形成金属晶种层201。金属晶种层201可以包括例如铜。可以在金属晶种层201上形成第一掩模图案MSK1。
参照图5B，可以在由第一掩模图案MSK1暴露的金属晶种层201上形成第一引线20和第二引线21。例如，可以采用电镀工艺来沉积第一引线20和第二引线21。
参照图5C，可以在第一掩模图案MSK1上形成第二掩模图案MSK2。第二掩模图案MSK2可以具有选择性地暴露第二引线21的端部21E和第一引线20的端部20E的开口。
参照图5D，可以在第一引线20的端部20E和第二引线21的端部21E上局部地沉积导电材料(例如，铜)，从而形成第一凸块连接件20a和第二凸块连接件21a。可以去除第二掩模图案MSK2，然后可以从基板10去除未形成为第一引线20和第二引线21的金属晶种层201(例如，金属晶种层201的在基板10上的第一引线20与第二引线21之间的部分)。
返回参照图2B，可以形成多个阻焊层40，可以在基板10上安装半导体芯片60，然后可以形成底部填充层50。
在以倒装芯片方式安装并且具有交错的凸块及其对应的引线的半导体器件中，即使当在凸块和引线之间建立了轻微的未对准时，漏泄电流也可能流过相邻的引线。根据本发明构思，可以控制凸块与其相邻引线之间的阶梯差，以防止和/或减少电流泄漏并提供精细节距结构。
此外，相邻的引线之间可以设置有防止和/或减少电流泄漏的结构，因此，可以在有限的区域中形成更多数量的引线。
尽管已经结合附图中示出的本发明构思的一些示例实施例描述了本发明，但是本领域普通技术人员将理解的是，在不脱离本发明构思的范围的情况下，可以在其中进行形式和细节上的变化。因此，以上公开的实施例应被认为是说明性的，而不是限制性的。

Claims (20)

1.一种半导体器件，所述半导体器件包括：
基板；
半导体芯片，所述半导体芯片位于所述基板上；以及
第一引线和第二引线，所述第一引线和所述第二引线位于所述基板和所述半导体芯片之间，
其中，所述第一引线和所述第二引线沿平行于所述基板的顶表面的第一方向在所述基板上延伸到所述半导体芯片下方，
其中，所述第一引线包括第一凸块连接件和连接到所述第一凸块连接件的第一段，
其中，所述第二引线包括第二凸块连接件，
其中，所述第一凸块连接件在所述第一方向上与所述第二凸块连接件间隔开，
其中，所述第一引线的所述第一段在第二方向上与所述第二凸块连接件间隔开，所述第二方向平行于所述基板的所述顶表面并且垂直于所述第一方向，并且
其中，所述第一引线的所述第一段的厚度小于所述第二凸块连接件的厚度。
2.根据权利要求1所述的半导体器件，其中，所述第一引线的所述第一段的厚度小于所述第一凸块连接件的厚度。
3.根据权利要求1所述的半导体器件，其中，所述第一引线的底表面与所述第二引线的底表面位于相同的水平高度处，并且
其中，所述第一引线的所述第一段的顶表面的水平高度低于所述第二引线的所述第二凸块连接件的顶表面的水平高度。
4.根据权利要求1所述的半导体器件，其中，所述第一引线和所述第二引线中的每一者的底表面位于与所述基板的所述顶表面的水平高度相同或者比所述基板的所述顶表面的水平高度高的水平高度处。
5.根据权利要求1所述的半导体器件，其中，所述第一引线还包括第二段，
其中，所述第一引线的所述第一段位于所述第一引线的所述第二段和所述第一凸块连接件之间，并且
其中，所述第一凸块连接件的顶表面和所述第一引线的所述第二段的顶表面的水平高度高于所述第一引线的所述第一段的顶表面的水平高度。
6.根据权利要求5所述的半导体器件，所述半导体器件还包括凸块，所述凸块位于所述第二凸块连接件上，
其中，所述凸块的在所述第一方向上的宽度小于所述第一引线的所述第一段的在所述第一方向上的宽度。
7.根据权利要求5所述的半导体器件，所述半导体器件还包括介电图案，所述介电图案位于所述第一引线的所述第一段的所述顶表面上并且位于所述第一引线的所述第一段的在所述第二方向上的相对侧表面上。
8.根据权利要求7所述的半导体器件，其中，所述介电图案包括有机可焊性保护剂。
9.根据权利要求1所述的半导体器件，其中，所述基板包括：印刷电路板或包括聚酰亚胺的柔性膜。
10.根据权利要求1所述的半导体器件，其中，所述第二引线的厚度沿所述第一方向是一致的。
11.根据权利要求1所述的半导体器件，其中，所述第一引线的所述第一段从所述基板的边缘延伸到所述半导体芯片下方，并且
其中，所述第一引线的所述第一段的所述厚度沿所述第一方向是一致的。
12.根据权利要求11所述的半导体器件，其中，所述第二引线还包括连接到所述第二凸块连接件的第一段，
其中，所述第二凸块连接件位于所述第二引线的端部处，并且
其中，所述第二引线的所述第一段的厚度小于所述第二凸块连接件的厚度。
13.根据权利要求11所述的半导体器件，所述半导体器件还包括介电图案，所述介电图案位于所述第一引线的所述第一段上并且位于所述第二引线的所述第一段上。
14.一种半导体器件，所述半导体器件包括：
基板；
半导体芯片，所述半导体芯片位于所述基板上；
多根第一引线，所述多根第一引线位于所述半导体芯片与所述基板之间；以及
多根第二引线，所述多根第二引线分别位于所述多根第一引线中的相邻的第一引线之间，
其中，所述第一引线和所述第二引线沿平行于所述基板的顶表面的第一方向在所述基板上延伸到所述半导体芯片下方，
其中，所述第一引线比所述第二引线在所述第一方向上延伸得更远，
其中，每根所述第一引线包括第一凸块连接件，并且每根所述第二引线包括第二凸块连接件，
其中，所述第一凸块连接件和所述第二凸块连接件沿平行于所述基板的所述顶表面且垂直于所述第一方向的第二方向以之字形方式布置，
其中，每根所述第一引线包括位于相邻的第二凸块连接件之间的第一段，并且
其中，每根所述第一引线的所述第一段的顶表面的水平高度低于每根所述第二凸块连接件的顶表面的水平高度。
15.根据权利要求14所述的半导体器件，其中，每根所述第一引线还包括第二段，所述第二段通过所述第一段与所述第一凸块连接件间隔开，
其中，所述第一凸块连接件的厚度和每根所述第一引线的所述第二段的厚度大于每根所述第一引线的所述第一段的厚度，
其中，每根所述第二引线沿所述第一方向包括一致的厚度，
其中，每根所述第二引线的所述第二凸块连接件与每根所述第一引线的所述第一段之间的厚度差在2μm到8μm的范围内，并且
其中，每根所述第一引线的所述第一段的厚度在2μm到8μm的范围内。
16.根据权利要求14所述的半导体器件，其中，每根所述第二引线还包括连接到所述第二凸块连接件的第一段，
其中，每根所述第二引线的所述第二凸块连接件的厚度大于每根所述第二引线的所述第一段的厚度，
其中，每根所述第二引线的所述第二凸块连接件与每根所述第一引线的所述第一段之间的厚度差在2μm到8μm的范围内，并且
其中，每根所述第一引线的所述第一段的厚度在8μm到10μm的范围内。
17.根据权利要求14所述的半导体器件，所述半导体器件还包括：
位于每根所述第一引线的所述第一凸块连接件上的第一凸块；以及
位于每根所述第二引线的所述第二凸块连接件上的第二凸块，
其中，所述第一凸块连接件的顶表面延伸到所述第一凸块的相对侧之外，并且
其中，所述第二凸块连接件的所述顶表面延伸到所述第二凸块的相对侧之外。
18.根据权利要求14所述的半导体器件，所述半导体器件还包括介电图案，所述介电图案位于每根所述第一引线的所述第一段上，
其中，所述介电图案的顶表面的水平高度低于每根所述第二引线的所述第二凸块连接件的所述顶表面的水平高度。
19.一种半导体器件，所述半导体器件包括：
基板；
半导体芯片，所述半导体芯片位于所述基板上；
第一引线和第二引线，所述第一引线和所述第二引线位于所述基板和所述半导体芯片之间；
阻焊层，所述阻焊层位于所述第一引线的一部分和所述第二引线的一部分上；以及
底部填充层，所述底部填充层位于所述基板的一部分、所述第一引线的一部分、所述第二引线的一部分和所述阻焊层的一部分上，
其中，所述第一引线和所述第二引线沿平行于所述基板的顶表面的第一方向在所述基板上延伸到所述半导体芯片下方，
其中，所述第一引线比所述第二引线在所述第一方向上延伸得更远，
其中，所述第一引线和所述第二引线在平行于所述基板的所述顶表面且垂直于所述第一方向的第二方向上彼此间隔开，
其中，所述第一引线包括第一凸块连接件、第一段和第二段，所述第一段位于所述第二段和所述第一凸块连接件之间，
其中，所述第二引线包括第二凸块连接件，
其中，介电图案位于所述第一引线的所述第一段上，
其中，所述第一凸块连接件在所述第一方向上与所述第二凸块连接件间隔开，
其中，所述第一引线的所述第一段与所述第二凸块连接件在所述第二方向上间隔开，
其中，所述第一引线的所述第一段的第一端部与所述半导体芯片垂直交叠，并且所述第一引线的所述第一段的第二端部与所述阻焊层垂直交叠，并且
其中，所述第一引线的所述第一段的厚度小于所述第二凸块连接件的厚度、所述第一凸块连接件的厚度以及所述第一引线的所述第二段的厚度。
20.根据权利要求19所述的半导体器件，其中，所述第二凸块连接件与所述第一引线的所述第一段之间的厚度差在2μm到8μm的范围内，
其中，所述基板包括聚酰亚胺，
其中，所述第一引线和所述第二引线包括铜，并且
其中，所述介电图案包括有机可焊性保护剂。
CN202010451123.2A 2019-08-14 2020-05-25 半导体器件 Pending CN112397476A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2019-0099316 2019-08-14
KR1020190099316A KR20210020274A (ko) 2019-08-14 2019-08-14 반도체 장치

Publications (1)

Publication Number Publication Date
CN112397476A true CN112397476A (zh) 2021-02-23

Family

ID=74566788

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010451123.2A Pending CN112397476A (zh) 2019-08-14 2020-05-25 半导体器件

Country Status (3)

Country Link
US (1) US11373942B2 (zh)
KR (1) KR20210020274A (zh)
CN (1) CN112397476A (zh)

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI226111B (en) 2003-11-06 2005-01-01 Himax Tech Inc Semiconductor packaging structure
TWI233714B (en) 2003-12-23 2005-06-01 Himax Tech Inc Electrical connection structure
KR100568496B1 (ko) 2004-10-21 2006-04-07 삼성전자주식회사 주석-인듐 합금층을 갖는 필름 회로 기판
JP2006229018A (ja) 2005-02-18 2006-08-31 Matsushita Electric Ind Co Ltd テープキャリア基板およびその製造方法および半導体装置
KR100788415B1 (ko) 2006-03-31 2007-12-24 삼성전자주식회사 이엠아이 노이즈 특성을 개선한 테이프 배선기판 및 그를이용한 테이프 패키지
US20090020316A1 (en) 2007-07-19 2009-01-22 Chia-Hui Wu Method of manufacturing chip on film and structure thereof
KR20090026891A (ko) 2007-09-11 2009-03-16 삼성전자주식회사 배선기판, 이를 갖는 테이프 패키지 및 표시장치, 이의제조방법 및 이를 갖는 테이프 패키지 및 표시장치의제조방법
US8349721B2 (en) 2008-03-19 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming insulating layer on conductive traces for electrical isolation in fine pitch bonding
KR101627574B1 (ko) * 2008-09-22 2016-06-21 쿄세라 코포레이션 배선 기판 및 그 제조 방법
US9418928B2 (en) 2014-01-06 2016-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Protrusion bump pads for bond-on-trace processing
US9305890B2 (en) 2014-01-15 2016-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. Package having substrate with embedded metal trace overlapped by landing pad
KR102214512B1 (ko) 2014-07-04 2021-02-09 삼성전자 주식회사 인쇄회로기판 및 이를 이용한 반도체 패키지

Also Published As

Publication number Publication date
KR20210020274A (ko) 2021-02-24
US11373942B2 (en) 2022-06-28
US20210050291A1 (en) 2021-02-18

Similar Documents

Publication Publication Date Title
US7851928B2 (en) Semiconductor device having substrate with differentially plated copper and selective solder
TWI395274B (zh) 製造電路基材的方法及製造電子部件封裝結構的方法
TWI426586B (zh) 具有用於將焊墊鍍於晶片下方之導線的球柵陣列封裝
CN100424866C (zh) 带式电路基板及使用该带式电路基板的半导体芯片封装
US8105934B2 (en) Bump structure for a semiconductor device and method of manufacture
WO2008112318A2 (en) Fine pitch microcontacts and method for forming thereof
KR101046117B1 (ko) 반도체 장치 및 그 제조 방법
CN108538802B (zh) 半导体装置封装及制造半导体装置封装的方法
KR100654338B1 (ko) 테이프 배선 기판과 그를 이용한 반도체 칩 패키지
JP3927783B2 (ja) 半導体部品
US20060097400A1 (en) Substrate via pad structure providing reliable connectivity in array package devices
US20190139907A1 (en) Package structure and manufacturing method thereof
KR101259844B1 (ko) 리드 크랙이 강화된 전자소자용 탭 테이프 및 그의 제조 방법
KR101336275B1 (ko) 솔더 마스크 패드를 구비한 집적 회로 실장 시스템 및 그 제조 방법
JP5627097B2 (ja) 配線基板
US11688674B2 (en) Printed circuit board and electronic component package
CN112397476A (zh) 半导体器件
CN100527398C (zh) 半导体器件的凸点结构和制造方法
TWI550745B (zh) 封裝基板及其製作方法
JP2006253253A (ja) フレキシブル回路基板の製造方法
KR100986294B1 (ko) 인쇄회로기판의 제조방법
KR101097292B1 (ko) 패키지 기판 및 그 제조 방법
KR100936782B1 (ko) 2단계 니켈 무전해도금으로 형성된 금속범프를 갖는반도체장치 및 그 금속 범프를 제조하는 방법
CN104378933B (zh) 布线基板的制造方法及半导体装置的制造方法
CN116130444A (zh) 半导体封装装置及其制造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination