CN112397374A - Low threading dislocation density silicon-based gallium arsenide layer growth method based on nano-cavities - Google Patents
Low threading dislocation density silicon-based gallium arsenide layer growth method based on nano-cavities Download PDFInfo
- Publication number
- CN112397374A CN112397374A CN202011286959.8A CN202011286959A CN112397374A CN 112397374 A CN112397374 A CN 112397374A CN 202011286959 A CN202011286959 A CN 202011286959A CN 112397374 A CN112397374 A CN 112397374A
- Authority
- CN
- China
- Prior art keywords
- nano
- growing
- gallium arsenide
- silicon
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 73
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 73
- 239000010703 silicon Substances 0.000 title claims abstract description 73
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 title claims abstract description 50
- 229910001218 Gallium arsenide Inorganic materials 0.000 title claims abstract description 50
- 238000000034 method Methods 0.000 title claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 238000000137 annealing Methods 0.000 claims abstract description 23
- 229910000673 Indium arsenide Inorganic materials 0.000 claims abstract description 22
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 claims abstract description 22
- 239000002096 quantum dot Substances 0.000 claims abstract description 4
- 239000000463 material Substances 0.000 claims description 13
- 238000005566 electron beam evaporation Methods 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 claims description 3
- 239000011800 void material Substances 0.000 claims 4
- 230000035515 penetration Effects 0.000 abstract description 4
- 238000001451 molecular beam epitaxy Methods 0.000 description 31
- 150000001875 compounds Chemical class 0.000 description 4
- 238000004891 communication Methods 0.000 description 3
- 238000001534 heteroepitaxy Methods 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000013473 artificial intelligence Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 230000001902 propagating effect Effects 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/02546—Arsenides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02601—Nanoparticles
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02658—Pretreatments
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02694—Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Nanotechnology (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
Abstract
The invention specifically discloses a method for growing a low threading dislocation density silicon-based gallium arsenide layer based on a nano-cavity, which comprises the following steps: s1, conveying the silicon substrate into an MBE cavity to remove the surface oxide layer; s2, growing a first epitaxial layer on the silicon substrate with the surface oxide layer removed and annealing; s3, carrying out indium arsenide nano-dot growth after annealing in the step S2; s4, growing a second epitaxial layer after the indium arsenide nano dots in the step S3 grow, and annealing again; s5, re-annealing in the step S4, and growing a gallium arsenide buffer layer, thereby obtaining the low threading dislocation density silicon-based gallium arsenide substrate based on nano-holes. The invention greatly reduces the penetration dislocation density on the silicon substrate by adopting the nanometer-sized cavity, can effectively avoid the problem of micro-cracks of the silicon substrate caused by using excessive layers of superlattice dislocation filter layers in the subsequent gallium arsenide growth, and thus improves the performance of devices on the silicon-based gallium arsenide substrate.
Description
Technical Field
The invention relates to the technical field of semiconductor substrates, in particular to a method for growing a low threading dislocation density silicon-based gallium arsenide layer based on nano holes.
Background
With the rapid development of the fields of big data, cloud computing, internet of things, 5G communication, artificial intelligence and the like, the data traffic is expected to increase by more than 25% and more than one hundred terabytes in 2021 year after the global annual data traffic increases. This explosively increasing traffic demand has made existing data communications areas challenging. Under the large background, the realization of high-speed low-power optical interconnection in a data center by utilizing a silicon-based photonic integrated circuit becomes a breakthrough in the field of new-generation communication. Since the silicon material is an indirect band gap semiconductor material, the light emitting efficiency is low, and how to realize a high-efficiency silicon-based light source becomes the most important bottleneck of a silicon-based photonic integrated circuit. The most mature method in the prior art is to integrate mature III-V compound photoelectric devices on a silicon substrate by adopting a heteroepitaxy and heterointegration method, thereby realizing a high-efficiency silicon-based light source. Heteroepitaxy is considered a more efficient integration method with higher throughput and lower production cost relative to heterointegration.
A technical difficulty with heteroepitaxy is that the III-V material does not match the crystalline properties of the silicon material. Due to lattice mismatch between the III-V group compound material and the silicon substrate, high-density penetration dislocations can be generated when the III-V group compound material is epitaxially grown on the silicon material, and the penetration dislocations can form non-radiative recombination centers of a large number of carriers and spread to an active layer of a silicon-based light source, so that the luminous efficiency of the device is greatly reduced, and the service life of the device is greatly prolonged. Threading dislocations only end up propagating throughout the entire crystal structure or when two threading dislocations having opposite berms vector directions meet. Molecular Beam Epitaxy (MBE) based on silicon substrates for achieving low threading dislocation density III-V compound materials relies primarily on superlattice dislocation filtering layers at this stage. This method requires a high thickness III-V buffer layer to accommodate enough superlattice dislocation filter layers to effectively reduce the penetration dislocation density to<106cm-2. Due to the different thermal expansion coefficients of III-V and IV, a large amount of microcracks are generated in the excessively thick epitaxial layer during cooling thermal annealing, and the productivity of the laser is greatly reduced.
In view of this, how to achieve a low thickness and low threading dislocation density III-V buffer layer will directly determine the key to success of high-yield and low-cost Si-based photonic integrated circuits.
Disclosure of Invention
The invention aims to provide a method for growing a low threading dislocation density silicon-based gallium arsenide layer based on nano-cavities, which utilizes MBE equipment to prepare a silicon epitaxial layer on a silicon substrate and combines a gallium arsenide buffer layer to reduce threading dislocation.
In order to solve the technical problem, the invention provides a method for growing a low threading dislocation density silicon-based gallium arsenide layer based on nano-cavities, which comprises the following steps:
s1, conveying the silicon substrate into the MBE cavity, and removing the surface oxide layer of the silicon substrate by utilizing the high temperature in the MBE cavity;
s2, growing a first epitaxial layer on the silicon substrate with the surface oxide layer removed, and carrying out first annealing in the MBE cavity;
s3, carrying out indium arsenide nano-dot growth after the first annealing in the step S2;
s4, growing a second epitaxial layer after the indium arsenide nano dots in the step S3 grow, and then carrying out second annealing in the MBE cavity to form nano holes in the second epitaxial layer;
s5, after the second annealing of the step S4, growing a gallium arsenide material to form a gallium arsenide buffer layer, thereby obtaining the silicon-based gallium arsenide substrate with low threading dislocation density based on the nano-holes.
Preferably, the step S1 is specifically implemented as follows: and (3) conveying the silicon substrate into an MBE (moving bed) cavity with the temperature of 950-1200 ℃ and keeping the temperature for 10-40min, thereby removing the surface oxide layer of the silicon substrate.
Preferably, the step S2 is specifically implemented as follows: and (3) growing a first epitaxial layer with the thickness of 50-100nm on the silicon substrate with the surface oxide layer removed by using an MBE cavity and a silicon electron beam evaporation technology, and then maintaining the temperature in the MBE cavity between 900 and 1200 ℃ for 10-20min to finish the first annealing in the MBE cavity.
Preferably, the first epitaxial layer is a silicon epitaxial layer.
Preferably, the step S3 is specifically implemented as follows: and reducing the temperature in the MBE cavity to between 300 and 500 ℃ and keeping the temperature, and then growing the indium arsenide nano-dots to obtain the indium arsenide nano-dots.
Preferably, the growth rate of the indium arsenide nanodots is 0.1 to 0.3 atomic layers per second.
Preferably, the step S4 is specifically implemented as follows: and keeping the temperature in the MBE cavity between 300 and 500 ℃, growing a second epitaxial layer with the thickness of 10-20nm, and then raising the temperature in the MBE cavity to between 700 and 750 ℃ to perform second annealing in the MBE cavity so as to generate high-density nano holes in the second epitaxial layer.
Preferably, the material used for growing the second epitaxial layer is silicon.
Preferably, the step S5 is specifically implemented as follows: and reducing the temperature in the MBE cavity to between 550 and 610 ℃, and then growing a gallium arsenide material to grow a gallium arsenide buffer layer with the thickness of 200 and 500nm, thereby obtaining the low threading dislocation density silicon-based gallium arsenide substrate based on the nano-cavities.
Preferably, the growth rate of the gallium arsenide buffer layer is 0.1 to 1.0 atomic layers per second.
Compared with the prior art, the method has the advantages that firstly, a first epitaxial layer is prepared on the silicon substrate by using MBE equipment and then annealed, then high-quality indium arsenide nano-dots are grown on the first epitaxial layer, a second epitaxial layer barrier is formed at the periphery of the indium arsenide nano-dots and then annealed again to generate high-density nano holes in the second epitaxial layer, and finally the gallium arsenide buffer layer is combined to reduce the threading dislocation density of the silicon substrate.
Drawings
FIG. 1 is a flow chart of the method for growing a low threading dislocation density Si-based GaAs layer based on nano-voids according to the present invention,
fig. 2 is a structural view of a low threading dislocation density gaas silicon substrate in accordance with the present invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the present invention is further described in detail below with reference to the accompanying drawings.
FIG. 1 is a flow chart showing the method for growing a low threading dislocation density silicon-based GaAs layer based on nano-voids according to the present invention.
Fig. 2 shows a structural diagram of a gaas substrate with a low threading dislocation density according to the present invention. As shown in fig. 2, the epitaxial wafer comprises a silicon substrate 1, a first epitaxial layer 2, a second epitaxial layer 3 and a gallium arsenide buffer layer 4.
As shown in fig. 1-2, a method for growing a low threading dislocation density silicon-based gallium arsenide layer based on nano-voids comprises the following steps:
s1, conveying the silicon substrate 1 into an MBE (Molecular Beam Epitaxy) cavity, and removing a surface oxidation layer of the silicon substrate 1 by utilizing high temperature in the MBE cavity;
s2, growing a first epitaxial layer 2 on the silicon substrate 1 with the surface oxide layer removed, and carrying out first annealing in the MBE cavity;
s3, carrying out indium arsenide nano-dot growth after the first annealing in the step S2 to obtain indium arsenide nano-dots;
s4, growing a second epitaxial layer 3 after the indium arsenide nano dots in the step S3 grow, and then performing second annealing in the MBE cavity to form nano holes in the second epitaxial layer 3;
s5, after the second annealing of the step S4, growing a gallium arsenide material to form a gallium arsenide buffer layer 4, thereby obtaining the silicon-based gallium arsenide substrate with low threading dislocation density based on nano-holes.
In the embodiment, firstly, a first epitaxial layer 2 is prepared on a silicon substrate 1 by using MBE equipment, indium arsenide nano-dots are grown on the first epitaxial layer 2, then a second epitaxial layer 3 barrier is formed at the periphery of the indium arsenide nano-dots to generate high-density nano holes in the second epitaxial layer 3, and finally the threading dislocation density of the silicon substrate is reduced by combining the second epitaxial layer 3 with a gallium arsenide buffer layer 4, so that the problem of micro-cracks caused by using too many layers of superlattice dislocation filter layers in the subsequent gallium arsenide growth process can be effectively avoided, and the performance of devices on the silicon-based gallium arsenide substrate is improved.
The specific implementation manner of step S1 is as follows: and (2) conveying the silicon substrate 1 into an MBE (moving bed) cavity with the temperature of 950-1200 ℃ and keeping the temperature for 10-40min, thereby removing the surface oxide layer of the silicon substrate 1.
The specific implementation manner of step S2 is as follows: and (3) growing a first epitaxial layer 2 with the thickness of 50-100nm on the silicon substrate 1 with the surface oxide layer removed by using an MBE cavity and a silicon electron beam evaporation technology, and then maintaining the temperature in the MBE cavity between 900 and 1200 ℃ for 10-20min to finish the first annealing in the MBE cavity. In this embodiment, the first epitaxial layer 2 is a silicon epitaxial layer.
The specific implementation manner of step S3 is as follows: and reducing the temperature in the MBE cavity to between 300 and 500 ℃ and keeping the temperature, and then growing the indium arsenide nano-dots to obtain the indium arsenide nano-dots.
Wherein the growth rate of the indium arsenide nanodots is 0.1 to 0.3 atomic layers per second.
The specific implementation manner of step S4 is as follows: keeping the temperature in the MBE cavity between 300 and 500 ℃, growing a second epitaxial layer 3 with the thickness of 10-20nm, and then raising the temperature in the MBE cavity to between 700 and 750 ℃ to carry out second annealing in the MBE cavity so as to generate high-density nano-voids in the second epitaxial layer 3. In this embodiment, the material used for the second epitaxial layer 3 is silicon. Due to the high density of nano-voids created in the second epitaxial layer 3, threading dislocations formed on the surface of the second epitaxial layer 3 can propagate into the high density nano-voids and be terminated.
The specific implementation manner of step S5 is as follows: the temperature in the MBE cavity is reduced to 550-610 ℃, and then gallium arsenide material growth is carried out to grow a gallium arsenide buffer layer 4 with the thickness of 200-500nm, so as to obtain the silicon-based gallium arsenide substrate with low threading dislocation density based on the nano-cavities. In this embodiment, the thickness of the gallium arsenide buffer layer 4 may be adjusted according to the control precision of polishing.
Wherein the growth rate of the gallium arsenide buffer layer 4 is 0.1-1.0 atomic layer per second.
The method for growing the low threading dislocation density silicon-based gallium arsenide layer based on the nano-cavity is described in detail above. The principles and embodiments of the present invention are explained herein using specific examples, which are presented only to assist in understanding the core concepts of the present invention. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.
Claims (10)
1. The method for growing the low threading dislocation density silicon-based gallium arsenide layer based on the nano-cavity is characterized by comprising the following steps:
s1, conveying the silicon substrate into the MBE cavity, and removing the surface oxide layer of the silicon substrate by utilizing the high temperature in the MBE cavity;
s2, growing a first epitaxial layer on the silicon substrate with the surface oxide layer removed, and carrying out first annealing in the MBE cavity;
s3, carrying out indium arsenide nano-dot growth after the first annealing in the step S2;
s4, growing a second epitaxial layer after the indium arsenide nano dots in the step S3 grow, and then carrying out second annealing in the MBE cavity to form nano holes in the second epitaxial layer;
s5, after the second annealing of the step S4, growing a gallium arsenide material to form a gallium arsenide buffer layer, thereby obtaining the silicon-based gallium arsenide substrate with low threading dislocation density based on the nano-holes.
2. The method for growing a low threading dislocation density silicon-based gallium arsenide layer based on nano-voids as claimed in claim 1, wherein the step S1 is implemented as follows: and (3) conveying the silicon substrate into an MBE (moving bed) cavity with the temperature of 950-1200 ℃ and keeping the temperature for 10-40min, thereby removing the surface oxide layer of the silicon substrate.
3. The method for growing a low threading dislocation density silicon-based gallium arsenide layer based on nano-voids as claimed in claim 2, wherein the step S2 is implemented as follows: and (3) growing a first epitaxial layer with the thickness of 50-100nm on the silicon substrate with the surface oxide layer removed by using an MBE cavity and a silicon electron beam evaporation technology, and then maintaining the temperature in the MBE cavity between 900 and 1200 ℃ for 10-20min to finish the first annealing in the MBE cavity.
4. The method of growing a nano-void based low threading dislocation density gaas layer according to claim 3, wherein the first epitaxial layer is a silicon epitaxial layer.
5. The method for growing a low threading dislocation density silicon-based gallium arsenide layer based on nano-voids as claimed in claim 4, wherein the step S3 is implemented as follows: and reducing the temperature in the MBE cavity to between 300 and 500 ℃ and keeping the temperature, and then growing the indium arsenide nano-dots to obtain the indium arsenide nano-dots.
6. The method of growing a nano-void based low threading dislocation density silicon based gallium arsenide layer as claimed in claim 5 wherein the indium arsenide nano dots are grown at a rate of 0.1 to 0.3 atomic layers per second.
7. The method for growing a low threading dislocation density silicon-based gallium arsenide layer based on nanovoids of claim 6, wherein the step S4 is specifically implemented as follows: and keeping the temperature in the MBE cavity between 300 and 500 ℃, growing a second epitaxial layer with the thickness of 10-20nm, and then raising the temperature in the MBE cavity to between 700 and 750 ℃ to perform second annealing in the MBE cavity so as to generate high-density nano holes in the second epitaxial layer.
8. The method of growing a nano-void based low threading dislocation density gaas layer according to claim 7, wherein the second epitaxial layer is grown from silicon.
9. The method for growing a low threading dislocation density silicon-based gallium arsenide layer based on nano-voids as claimed in claim 8, wherein the step S5 is implemented as follows: and reducing the temperature in the MBE cavity to between 550 and 610 ℃, and then growing a gallium arsenide material to grow a gallium arsenide buffer layer with the thickness of 200 and 500nm, thereby obtaining the low threading dislocation density silicon-based gallium arsenide substrate based on the nano-cavities.
10. The method of growing a nano-void based low threading dislocation density silicon based gallium arsenide layer as claimed in claim 9 wherein the gallium arsenide buffer layer is grown at a rate of 0.1 to 1.0 atomic layers per second.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011286959.8A CN112397374B (en) | 2020-11-17 | 2020-11-17 | Growth method of low threading dislocation density silicon-based gallium arsenide layer based on nano-cavity |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011286959.8A CN112397374B (en) | 2020-11-17 | 2020-11-17 | Growth method of low threading dislocation density silicon-based gallium arsenide layer based on nano-cavity |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112397374A true CN112397374A (en) | 2021-02-23 |
| CN112397374B CN112397374B (en) | 2024-01-16 |
Family
ID=74605845
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011286959.8A Active CN112397374B (en) | 2020-11-17 | 2020-11-17 | Growth method of low threading dislocation density silicon-based gallium arsenide layer based on nano-cavity |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112397374B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112951942A (en) * | 2021-04-23 | 2021-06-11 | 湖南汇思光电科技有限公司 | Method for manufacturing germanium avalanche photodetector based on gallium arsenide substrate |
| CN115360272A (en) * | 2022-10-21 | 2022-11-18 | 至善时代智能科技(北京)有限公司 | Preparation method of AlN thin film |
| JP7416171B1 (en) | 2022-10-24 | 2024-01-17 | 信越半導体株式会社 | Epitaxial wafer manufacturing method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001102668A (en) * | 1999-09-28 | 2001-04-13 | Kyocera Corp | Manufacturing method of semiconductor substrate |
| CN103311106A (en) * | 2013-05-14 | 2013-09-18 | 中国科学院半导体研究所 | Preparation method for silica-based gallium arsenide material with high quality and low surface roughness |
| US9496347B1 (en) * | 2015-12-18 | 2016-11-15 | International Business Machines Corporation | Graded buffer epitaxy in aspect ratio trapping |
| CN106480498A (en) * | 2016-10-12 | 2017-03-08 | 北京邮电大学 | A kind of nano graph substrate side epitaxial silicon based quantum dot laser equipment material and preparation method thereof |
| CN111540671A (en) * | 2020-05-15 | 2020-08-14 | 湖南汇思光电科技有限公司 | III-V group compound material growth method based on CMOS technology compatible with silicon substrate |
-
2020
- 2020-11-17 CN CN202011286959.8A patent/CN112397374B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001102668A (en) * | 1999-09-28 | 2001-04-13 | Kyocera Corp | Manufacturing method of semiconductor substrate |
| CN103311106A (en) * | 2013-05-14 | 2013-09-18 | 中国科学院半导体研究所 | Preparation method for silica-based gallium arsenide material with high quality and low surface roughness |
| US9496347B1 (en) * | 2015-12-18 | 2016-11-15 | International Business Machines Corporation | Graded buffer epitaxy in aspect ratio trapping |
| CN106480498A (en) * | 2016-10-12 | 2017-03-08 | 北京邮电大学 | A kind of nano graph substrate side epitaxial silicon based quantum dot laser equipment material and preparation method thereof |
| CN111540671A (en) * | 2020-05-15 | 2020-08-14 | 湖南汇思光电科技有限公司 | III-V group compound material growth method based on CMOS technology compatible with silicon substrate |
Non-Patent Citations (1)
| Title |
|---|
| 林兰英等: "掺铟低位错密度的半绝缘砷化镓", 《半导体学报》, vol. 8, no. 2, pages 204 - 207 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112951942A (en) * | 2021-04-23 | 2021-06-11 | 湖南汇思光电科技有限公司 | Method for manufacturing germanium avalanche photodetector based on gallium arsenide substrate |
| CN115360272A (en) * | 2022-10-21 | 2022-11-18 | 至善时代智能科技(北京)有限公司 | Preparation method of AlN thin film |
| CN115360272B (en) * | 2022-10-21 | 2023-01-31 | 至善时代智能科技(北京)有限公司 | Preparation method of AlN thin film |
| JP7416171B1 (en) | 2022-10-24 | 2024-01-17 | 信越半導体株式会社 | Epitaxial wafer manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112397374B (en) | 2024-01-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112397374B (en) | Growth method of low threading dislocation density silicon-based gallium arsenide layer based on nano-cavity | |
| JP6484076B2 (en) | Optical device | |
| CN107275187B (en) | Self-supporting gallium nitride layer and preparation method and annealing method thereof | |
| US6441403B1 (en) | Semiconductor device with roughened surface increasing external quantum efficiency | |
| JP4371202B2 (en) | Nitride semiconductor manufacturing method, semiconductor wafer, and semiconductor device | |
| JP2828002B2 (en) | Semiconductor light emitting device and method of manufacturing the same | |
| JP2000340511A (en) | Method for growing gallium nitride compound semiconductor crystal and semiconductor substrate | |
| CN111540671B (en) | III-V group compound material growth method based on CMOS technology compatible with silicon substrate | |
| JPH11243253A (en) | Growth of nitride-based iii-v compound semiconductor, manufacture of semiconductor device, substrate for growth of nitride-based iii-v compound semiconductor, manufacture of the substrate for growth of nitride-based iii-v compound semiconductor | |
| WO2013078807A1 (en) | Monolithical integrated lattice mismatched crystal template and fabrication method therefor | |
| JP4303379B2 (en) | Manufacturing method of semiconductor substrate | |
| US10892159B2 (en) | Semipolar or nonpolar group III-nitride substrates | |
| CN114242854B (en) | Homoepitaxy structure, preparation method and stripping method thereof | |
| KR101288064B1 (en) | Method for manufacturing light emitting element, compound semiconductor wafer, and light emitting element | |
| CN111262127B (en) | Preparation method of silicon-based InGaAs laser substrate, substrate and laser | |
| US20210175077A1 (en) | Semipolar or nonpolar group iii-nitride substrates | |
| JP5071484B2 (en) | Compound semiconductor epitaxial wafer and manufacturing method thereof | |
| CN111834206B (en) | Method for extending GeSi quantum dots | |
| JP2000150388A (en) | Iii nitride semiconductor thin film and manufacture thereof | |
| JP2002299261A (en) | Semiconductor wafer and manufacturing method therefor | |
| JP2000332293A (en) | Iii-v nitride semiconductor light emitting element and its manufacture | |
| CN111435694A (en) | GaN epitaxial wafer and preparation method thereof | |
| CN115360272B (en) | Preparation method of AlN thin film | |
| CN115084308B (en) | Germanium substrate-gallium arsenide/germanium heterojunction film composite structure and preparation method and application thereof | |
| CN115966458A (en) | Preparation method of epitaxial structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |