CN112385040A - Array and contact architecture for four stacked layer three-dimensional cross-point memory - Google Patents
Array and contact architecture for four stacked layer three-dimensional cross-point memory Download PDFInfo
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- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
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- G—PHYSICS
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- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
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- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
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- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0023—Address circuits or decoders
- G11C13/0026—Bit-line or column circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0023—Address circuits or decoders
- G11C13/0028—Word-line or row circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/003—Cell access
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/71—Three dimensional array
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/77—Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
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Abstract
An architecture for a three-dimensional cross-point memory cell includes a plurality of planar and mutually parallel layers of bit cell regions, each of which includes a bit line extending in a bit line direction. The architecture also includes a decoder to which the bit field is electrically connected through the contacts. Each bit slice layer has a per-decoder slice ratio defined as a ratio of a bit slice in the layer to a number of decoders to which at least one slice in the layer is electrically connected. At least one bit pad region layer has a bit pad area ratio greater than 1: 1 different per-decoder slice ratio.
Description
Technical Field
The present disclosure relates generally to three-dimensional electronic memories and, more particularly, to increasing the density of memory cells in three-dimensional cross-point memories.
Background
Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches the lower limit, planar processes and fabrication techniques become challenging and costly. Thus, the storage density of the planar memory cell approaches the upper limit. Three-dimensional (3D) memory architectures can address density limitations in planar memory cells by layering multiple planes of memory cells in a single device.
Disclosure of Invention
According to one aspect, an architecture for a three-dimensional cross-point memory cell includes a plurality of planar and mutually parallel layers of bit regions (bit tiles), each of the bit regions including a bit line extending in a bit line direction. The architecture also includes a decoder to which the bit field is electrically connected through the contacts. Each slice region layer has a slice region ratio per decoder (tile per decoder ratio) defined as a ratio of a bit slice region in a layer to a number of decoders to which at least one slice region in the layer is electrically connected. At least one bit pad region layer has a bit pad area ratio greater than 1: 1 different per-decoder slice ratio.
In some arrangements, at least one bit slice layer has a different slice ratio per decoder than another bit slice layer.
In some arrangements, at least one bit pad zone layer has a 2: 1 per decoder slice ratio.
In some arrangements, there is a 2: at least one bit slice layer of the per decoder slice ratio of 1 includes bit slices electrically connected to the same decoder as another bit slice in the same layer.
In some arrangements, at least one bit pad zone layer has a 4: 1 per decoder slice ratio.
In some arrangements, there is a 4: at least one bit slice layer of the per decoder slice ratio of 1 includes bit slices electrically connected to the same decoder as the other three bit slices in the same layer.
In some arrangements, the plurality of bit slice regions layers comprises: a first layer; an intermediate layer closer to the decoder than the first layer and having a per-decoder slice ratio greater than the first layer; and an outer layer closer to the decoder than the middle layer and having a slice ratio per decoder greater than the middle layer.
In some arrangements, the plurality of bit slice layers further includes a second layer that is further from the decoder than the middle layer and the outer layer and has the same per-decoder slice ratio as the first layer.
In some arrangements, the bit areas in the middle layer are shorter than the bit areas in the first layer in the bit line direction, and the bit areas in the outer layer are shorter than the bit areas in the middle layer in the bit line direction.
According to another aspect, an array and contact architecture for a three-dimensional cross-point memory cell includes a plurality of planar and mutually parallel bit cell layers, each of the bit cells including a bit line extending in a bit line direction. Bit slices in at least one bit slice region layer are shorter than bit slices in another bit slice region layer in the bit line direction.
In some arrangements, the architecture includes a decoder, and the plurality of bit slices includes: a first layer; an intermediate layer closer to the decoder and including a bit slice region shorter in a bit line direction than the bit slice region in the first layer; and an outer layer closer to the decoder than the middle layer and including bit slice regions shorter in a bit line direction than the bit slice regions in the middle layer.
In some arrangements, each bit slice layer has a per-decoder slice ratio defined as a ratio of bit slices in the layer to a number of decoders to which at least one slice in the layer is electrically connected, and the intermediate layer has a per-decoder slice ratio greater than the first layer.
In some arrangements, the outer layer has a slice ratio per decoder that is greater than the middle layer.
In some arrangements, the plurality of bit-slice layers further includes a second layer that is further from the decoder than the middle layer and the outer layer and has bit-slices of the same length in the bit-line direction as the bit-slices in the first layer.
In some arrangements, each bit slice layer has a per-decoder slice ratio defined as a ratio of bit slices in the layer to a number of decoders to which at least one slice in the layer is electrically connected. The second layer has the same per-decoder slice ratio as the first layer, the middle layer has a per-decoder slice ratio greater than the first layer, and the outer layer has a per-decoder slice ratio greater than the middle layer.
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The foregoing aspects, features and advantages of the disclosure will be further understood when considered in conjunction with the following description of exemplary embodiments and the accompanying drawings, in which like reference numerals refer to like elements. In describing the exemplary embodiments of the present disclosure illustrated in the drawings, specific terminology may be employed for the sake of clarity. However, aspects of the present disclosure are not intended to be limited to the specific terminology used.
Fig. 1 is an isometric view of a portion of a prior art three-dimensional cross-point memory.
Fig. 2 is a plan view of a portion of the prior art three-dimensional cross-point memory shown in fig. 1.
Figure 3 is a cross-sectional side view of a portion of the prior art three-dimensional cross-point memory shown in figures 1 and 2.
Figure 4 is a cross-sectional side view of a portion of a three-dimensional cross-point memory according to an embodiment.
Detailed Description
The present technique is applied to the field of three-dimensional cross-point memories. A general example of a three-dimensional (3D) memory is shown in fig. 1. In particular, fig. 1 is an isometric view of a portion of a three-dimensional cross-point memory 10. This portion includes a first bit field 14 and a second bit field 18 that extends below the first bit field 14. The first bit field 14 and the second bit field 18 are each planar and parallel to each other and each include a plurality of bit lines 22 therethrough. The lines 22 are also parallel to each other and extend in the bit line direction.
Interleaved with the bit fields 14, 18 are a first bit field 26 extending between the first bit field 14 and the second bit field 18, and a second bit field 30 extending below the second bit field 18. The illustrated staggering is merely exemplary, and in other examples, the first tile region 26 may extend over the first tile region 14, while the second tile region 30 extends between the first tile region 14 and the second tile region 18. The tablet regions 26, 30 are also planar and parallel to the bit regions 14, 18. The word line regions 26, 30 each include a plurality of word lines 34 extending therethrough in a word direction Z perpendicular to the bit direction X.
The illustrated portion of memory 10 includes three layers of memory cells 40. A memory cell 40 may be present between the bit and word regions 14, 18, 26, 30, while the memory cell 40 is where the bit line 22 and the word line 34 intersect, from a height direction Y perspective. Thus, the storage density per unit area in the XY plane is a function of the number of bit and word partitions that can be alternately interleaved at a given location.
To selectively activate the word lines 34 and bit lines 22, the memory includes a bit line decoder 42 and a word line decoder 46 at the bottom layer of the memory architecture. The bit line decoder 42 and word line decoder 46 are coupled to the bit lines 22 and word lines 34, respectively, through contacts 38 and are used to decode bit line and word line addresses so that a particular bit line 22 or word line 34 is activated when addressed. The bit areas 14, 18 and word areas 26, 30 are each shown in dashed lines to indicate that the contact 38 is located at or near the midpoint of the bit areas 14, 18 in the bit direction X and at or near the midpoint of the word area 34 in the word direction Z. It should also be understood that the number of bit lines 22 per bit tile 14, 18 and word lines 34 per word tile 26, 30 shown is exemplary, and that more or fewer lines may be used per tile. The arrangement of the decoders 42, 46 and the contacts 38 is further discussed in conjunction with fig. 2.
Fig. 2 schematically shows a cross section of the memory 10 from the perspective of the height direction Y, showing only the bit lines 22 and the word lines 34 corresponding to the first and second bit cell regions 14, 18 and the first word cell region 26. Since the contacts 38 extend vertically to the bottom layer of the storage architecture, the contacts 38 associated with each tile define an area, indicated by dashed lines, through which other tiles cannot pass underneath. This is also illustrated in fig. 3, which fig. 3 schematically shows a cross section of the first bit area 14 and the second bit area 18 in the X-Y plane. Such contact areas thus hinder the interleaving of the patches. When present in a repeating pattern, the contact area limits the number of layers of memory cells that can be achieved across the memory device. For example, where bit patches 14, 18 having substantially equal lengths in the bit direction X and a centered contact 38 are used, only two bit patch layers may be used at a given location along the bit direction X in a given X-Y plane.
Fig. 4 schematically shows a cross section of a memory according to an embodiment along the X-Y plane. As shown, the memory includes a third bit area 50 extending below the second bit area 18 and a fourth bit area 54 extending below the third bit area 50. The third bit field 50 is shorter in the bit direction X than the first and second bit fields 14, 18 so that the third bit field 50 can fit between the contacts 38 associated with the first and second bit fields 14, 18. Similarly, the fourth bit land 54 is shorter in the bit direction X than the third bit land 50 such that the fourth bit land 54 can fit between the contacts 38 associated with the first, second, and third bit lands 14, 18, 50. Thus, the architecture of FIG. 4 is capable of using up to four bit slice region layers at a given location along bit direction X on the illustrated X-Y plane. The greater number of bit field layers can correspondingly increase the number of layers of memory cell 40, thereby increasing the possible storage density per unit area in the X-Z plane. Although the third and fourth bit lands 50, 54 are different sizes, in the example shown, contact 38 is connected to the respective third and fourth bit lands 50, 54 along the X direction at the center of the lands.
A layer may be assigned a layer wide group size. In the example of uniform slice placement on a layer, the layer width group size refers to the number of slices in each decoder common group of slices in the layer. In examples where the decoder common group size varies within a layer (e.g., due to differences at the edge of the architecture or manufacturing defects), the layer width group size instead refers to the number of statistical patterns of bit slices in a layer to which any one decoder is electrically connected in a group of all decoders electrically connected to the bit slice region in the layer. In other words, in a layer where the decoder common set size is not uniform, the layer wide set size refers to the statistical mode size of the decoder common set of bit slices in the layer, where each decoder common set of bit slices is one or more bit slices of the common decoder.
In the example shown, the layer comprising the third bit slice 50 has a per-decoder slice ratio greater than the per-decoder slice ratio of the layer comprising the first bit slice 14 and the second bit slice 18, and the layer comprising the fourth bit slice 54 has a per-decoder slice ratio greater than the per-decoder slice ratio of the layer comprising the third bit slice 50, while the layer comprising the first bit slice 14 has a per-decoder slice ratio equal to the per-decoder slice ratio of the layer comprising the second bit slice 18. In particular, the slice ratio per decoder of the layer comprising the third bit slice 50 is twice the slice ratio per decoder of the layer comprising the first bit slice 14 and the second bit slice 18, and the slice ratio per decoder of the layer comprising the fourth bit slice 54 is twice the slice ratio per decoder of the layer comprising the third bit slice 50. Thus, the layer including the first bit field 14 and the layer including the second bit field 18 each have a 1: 1 per decoder slice ratio. The layer comprising the third bit field 50 has 2: 1, and the layer including the fourth bit-slice 54 has a 4: 1 per decoder slice ratio. Similarly, the layers comprising the first bit field 14 and the second bit field 18 each have a layer width group size of 1. The layer comprising the third bit field 50 has a layer width set size of 2 and the layer comprising the fourth bit field 54 has a layer width set size of 4. However, it should be understood that the shown per-decoder slice ratio and layer width group sizes are merely exemplary, and other per-decoder slice ratios are possible according to various applications and embodiments. Further, while some examples are arranged such that for layers closer to the bit slice of the bit line decoder 42, the per-decoder slice ratio of the layer will generally be larger, other per-decoder slice ratio gradients are also possible. Further, it should be understood that the same or similar manner of varying per-decoder tile ratios as described above with respect to bit tiles 14, 18, 50, 54 may be applied to word tile regions 26, 30 and word line decoder 46 to achieve the structure of a memory architecture having more word tile layers.
Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.
Claims (15)
1. An architecture for a three-dimensional memory cell, comprising:
a plurality of planar and mutually parallel layers of bit regions, each of the bit regions comprising a bit line extending in a bit line direction;
a decoder, the bit slice electrically connected to the decoder by a contact; wherein:
each bit slice region layer having a per-decoder slice region ratio defined as a ratio of a total number of bit slice regions in the layer to a total number of decoders electrically connected to the bit slice regions in the layer; and is
At least one bit pad region layer has a bit pad area ratio greater than 1: 1 per decoder slice ratio.
2. The architecture of claim 1, wherein at least one slice layer has a per-decoder slice ratio that is different from another slice layer.
3. The architecture of claim 1, wherein at least one bit slice region layer has a 2: 1 per decoder slice ratio.
4. The architecture of claim 3, wherein there is 2: the at least one bit slice layer of the per decoder slice ratio of 1 comprises bit slices electrically connected to the same decoder as another bit slice in the same layer.
5. The architecture of claim 1, wherein at least one bit slice region layer has a width of 4: 1 per decoder slice ratio.
6. The architecture of claim 1, wherein there is 4: the at least one bit slice layer of the per decoder slice ratio of 1 includes bit slices electrically connected to the same decoder as the other three bit slices in the same layer.
7. The architecture of claim 1, wherein the plurality of bit slice layers comprises:
a first layer;
an intermediate layer closer to the decoder than the first layer and having a per-decoder slice ratio greater than the first layer; and
an outer layer closer to the decoder than the middle layer and having a per-decoder slice ratio greater than the middle layer.
8. The architecture of claim 7, wherein the plurality of slice layers further comprises a second layer that is further from the decoder than the middle layer and the outer layer and has the same per-decoder slice ratio as the first layer.
9. The architecture of claim 7, wherein the bit regions in the middle layer are shorter than the bit regions in the first layer in the bit line direction, and the bit regions in the outer layer are shorter than the bit regions in the middle layer in the bit line direction.
10. An array and contact architecture for a three-dimensional memory cell, comprising:
a plurality of planar and mutually parallel layers of bit regions, each of the bit regions comprising a bit line extending in a bit line direction;
wherein bit regions in at least one bit region layer are shorter than bit regions in another bit region layer in the bit line direction.
11. The architecture of claim 10, comprising a decoder, and wherein the plurality of bit slices comprises:
a first layer;
an intermediate layer closer to the decoder and including bit slices shorter than the bit slices in the first layer in the bit line direction; and
an outer layer closer to the decoder than the middle layer and including bit slice regions shorter than the bit slice regions in the middle layer in the bit line direction.
12. The architecture of claim 11, wherein each bit slice layer has a slice ratio per decoder defined as a ratio of a total number of bit slices in the layer to a total number of decoders electrically connected to bit slices in the layer, and the intermediate layer has a slice ratio per decoder greater than the first layer.
13. The architecture of claim 12, wherein the outer layer has a slice ratio per decoder that is greater than the middle layer.
14. The architecture of claim 11, wherein the plurality of bit slice layers further comprises a second layer that is further from the decoder than the middle layer and the outer layer and has a bit slice in the bit line direction that is the same length as the bit slice in the first layer.
15. The architecture of claim 14, wherein:
each bit slice region layer having a per-decoder slice region ratio defined as a ratio of a total number of bit slice regions in the layer to a total number of decoders electrically connected to the bit slice regions in the layer;
the second layer has the same per-decoder slice ratio as the first layer;
the middle layer has a slice ratio per decoder that is greater than the first layer; and is
The outer layer has a slice ratio per decoder that is greater than the middle layer.
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| CN202111270369.0A CN114005829A (en) | 2020-10-15 | 2020-10-15 | Array and contact architecture for four stacked layer three-dimensional cross-point memory |
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| PCT/CN2020/121071 WO2022077318A1 (en) | 2020-10-15 | 2020-10-15 | Array and contact architecture for four stack three dimensional cross point memory |
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| WO2023245817A1 (en) * | 2022-06-21 | 2023-12-28 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor, memory chip and electronic device |
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| CN108417560A (en) * | 2012-10-05 | 2018-08-17 | 三星电子株式会社 | Semiconductor devices and its manufacturing method |
| CN109219885A (en) * | 2018-07-20 | 2019-01-15 | 长江存储科技有限责任公司 | Three-dimensional storage part |
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| JP5063337B2 (en) * | 2007-12-27 | 2012-10-31 | 株式会社日立製作所 | Semiconductor device |
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| KR102157359B1 (en) * | 2014-12-16 | 2020-09-17 | 삼성전자 주식회사 | Resistive Memory Device including column decoder and Operating Method thereof |
| EP3404697A4 (en) * | 2016-01-13 | 2019-12-25 | Toshiba Memory Corporation | Semiconductor storage device |
| US9792958B1 (en) * | 2017-02-16 | 2017-10-17 | Micron Technology, Inc. | Active boundary quilt architecture memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101047190A (en) * | 2006-03-31 | 2007-10-03 | 株式会社半导体能源研究所 | Nonvolatile semiconductor storage device and method for manufacturing the same |
| CN108417560A (en) * | 2012-10-05 | 2018-08-17 | 三星电子株式会社 | Semiconductor devices and its manufacturing method |
| US20160343440A1 (en) * | 2014-12-08 | 2016-11-24 | Samsung Electronics Co., Ltd. | Nonvolatile memory device including multi-plane |
| US9721663B1 (en) * | 2016-02-18 | 2017-08-01 | Sandisk Technologies Llc | Word line decoder circuitry under a three-dimensional memory array |
| CN109219885A (en) * | 2018-07-20 | 2019-01-15 | 长江存储科技有限责任公司 | Three-dimensional storage part |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2023245817A1 (en) * | 2022-06-21 | 2023-12-28 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor, memory chip and electronic device |
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| WO2022077318A1 (en) | 2022-04-21 |
| CN114005829A (en) | 2022-02-01 |
| CN112385040B (en) | 2022-03-15 |
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