CN112380075B

CN112380075B - Scheduler testing method and device, electronic equipment and computer readable storage medium

Info

Publication number: CN112380075B
Application number: CN202011249076.XA
Authority: CN
Inventors: 于亚轩
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2020-11-10
Filing date: 2020-11-10
Publication date: 2023-03-14
Anticipated expiration: 2040-11-10
Also published as: CN112380075A

Abstract

The application relates to a scheduler testing method, a scheduler testing device, electronic equipment and a computer readable storage medium. The scheduler testing method provided by the embodiment of the application comprises the following steps: sending a first target number of test instructions to a processor to be tested; respectively controlling the operation data corresponding to the first target number of test instructions in the memory to be converted from an invalid state to an effective state according to the second target number scheduling sequence so as to cover all empty and full state combinations of a scheduling queue in a scheduler included in the processor to be tested; acquiring each scheduling sequence in the second target quantity scheduling sequences, wherein the processor to be tested executes the first target quantity test instructions to acquire a group of target execution results so as to acquire a second target quantity group of target execution results; and obtaining a reliability test result aiming at the scheduler according to the second target quantity group target execution result. The scheduler testing method provided by the embodiment of the application can improve the reliability testing efficiency of the scheduler.

Description

Scheduler testing method and device, electronic equipment and computer readable storage medium

Technical Field

The present application relates to the field of computer technologies, and in particular, to a scheduler testing method and apparatus, an electronic device, and a computer-readable storage medium.

Background

With the development of processor pipeline technology and multi-core technology, advanced processors often employ out-of-order execution techniques to increase operating speed by increasing utilization of internal logic elements, and the implementation of out-of-order execution is dependent on the scheduler included in the processor. Based on this, during the design process of the processor, the reliability of the scheduler is usually required to be tested.

In the prior art, the reliability of the scheduler is mainly tested at random, for example, a test instruction is sent to the processor to be tested at random to randomly cover the empty and full states of the scheduling queue in the scheduler, so as to implement the test. However, this test method usually takes a long test time, especially when the number of queue entries in the scheduling queue is large. Taking the number of queue entries of the scheduling queue as N, there are 2^ N all empty-full state combinations of the scheduling queue, so if all the empty-full state combinations of the scheduling queue are covered by a random test method, it usually takes a long test time.

Disclosure of Invention

An object of the present application is to provide a scheduler testing method, apparatus, electronic device and computer-readable storage medium to solve the above problems.

In a first aspect, a scheduler testing method provided by the present application includes:

sending the first target quantity of test instructions to a processor to be tested;

respectively controlling the operation data corresponding to the first target number of test instructions in the memory to be converted from an invalid state to an effective state according to the second target number scheduling sequence so as to cover all empty and full state combinations of a scheduling queue in a scheduler included in the processor to be tested;

acquiring each scheduling sequence in the second target quantity scheduling sequences, wherein the processor to be tested executes the first target quantity test instructions to acquire a group of target execution results so as to acquire a second target quantity group of target execution results;

and obtaining a reliability test result aiming at the scheduler according to the second target quantity group target execution result.

With reference to the first aspect, an embodiment of the present application further provides a first optional implementation manner of the first aspect, where before sending the first target number of test instructions to the processor to be tested, the scheduler testing method further includes:

and if the test starting request is received, responding to the test starting request, and generating a first target number of test instructions, wherein operands corresponding to the first target number of test instructions are located in different storage spaces in the memory, and no correlation exists between any two test instructions in the first target number of test instructions.

With reference to the first aspect, an embodiment of the present application further provides a second optional implementation manner of the first aspect, where the controlling, according to the second target number scheduling order, that the operation data corresponding to the first target number of test instructions in the memory is converted from an invalid state to an valid state includes:

aiming at each scheduling sequence in the second target number scheduling sequences, presetting a conversion duration at intervals according to the scheduling sequence to generate a state conversion instruction;

and sending the state conversion instruction to the memory every time the state conversion instruction is generated, so that the memory requests the next-level storage device of the memory for mapping target data according to the state conversion instruction, wherein the target data is operation data required by executing the test instruction corresponding to the state conversion instruction, and the operation data corresponding to the test instruction is converted from an invalid state to a valid state.

With reference to the first aspect, an embodiment of the present application further provides a third optional implementation manner of the first aspect, where before controlling, according to the second target number of scheduling orders, that the operation data corresponding to the first target number of test instructions in the memory is converted from the invalid state to the valid state, the scheduler testing method further includes:

acquiring the queue item number of a scheduling queue;

and obtaining a second target quantity scheduling sequence according to the queue item number.

With reference to the third optional implementation manner of the first aspect, an embodiment of the present application further provides a fourth optional implementation manner of the first aspect, where the obtaining, according to the number of queue entries, a second target number of scheduling orders includes:

establishing a corresponding relation between the first target quantity test instruction and all queue items in the scheduling queue;

setting a third target quantity stepping value according to the queue item number;

for each queue item in the scheduling queue, traversing the scheduling queue according to a third target quantity stepping value by taking the queue item as an initial position, and obtaining a third target quantity scheduling sequence according to a traversal result;

and taking the third target quantity scheduling sequences corresponding to each queue entry in the scheduling queue as the second target quantity scheduling sequences together.

With reference to the first aspect, an embodiment of the present application further provides a fifth optional implementation manner of the first aspect, where obtaining a reliability test result for a scheduler according to a second target number group target execution result includes:

comparing the target execution result of the second target quantity group with the standard execution result to obtain a comparison result;

and according to the comparison result, obtaining a reliability test result aiming at the scheduler.

With reference to the fifth optional implementation manner of the first aspect, an embodiment of the present application further provides a sixth optional implementation manner of the first aspect, where the reliability test result includes a first test result and a second test result, and the obtaining the reliability test result for the scheduler according to the comparison result includes:

if the comparison result represents that a target execution result different from the standard execution result exists in the target execution results of the second target quantity group, a first test result is obtained, wherein the first test result is used for representing that the reliability of the scheduler does not meet the preset test requirement;

and if the comparison result represents that no target execution result different from the standard execution result exists in the target execution results of the second target quantity group, obtaining a second test result, wherein the second test result is used for representing that the reliability of the scheduler meets the preset test requirement.

With reference to the fifth optional implementation manner of the first aspect, an embodiment of the present application further provides a seventh optional implementation manner of the first aspect, where the second target number group target execution result is compared with the standard execution result, and before obtaining a comparison result, the scheduler testing method further includes:

and under the condition of acquiring any one of the second target quantity scheduling sequences, executing the first target quantity test instructions by the processor model, and taking a group of acquired execution results as standard execution results.

In a second aspect, an embodiment of the present application further provides a scheduler testing apparatus, including:

the driving module is used for sending the first target number of test instructions to the processor to be tested;

the conversion module is used for controlling the operation data corresponding to the first target number of test instructions in the memory to be converted from an invalid state to an effective state according to the second target number scheduling sequence so as to cover all empty and full state combinations of a scheduling queue in a scheduler included in the processor to be tested;

the target execution result acquisition module is used for acquiring each scheduling sequence in the second target quantity scheduling sequences, and the processor to be tested executes the first target quantity test instructions to obtain a group of target execution results so as to obtain a second target quantity group target execution result;

and the test result acquisition module is used for acquiring a reliability test result aiming at the scheduler according to the second target quantity group target execution result.

In a third aspect, an electronic device provided in an embodiment of the present application includes a processor and a storage device, where the storage device stores a computer program, and the processor is configured to execute the computer program to implement the scheduler testing method provided in the first aspect, or any optional implementation manner of the first aspect.

In a fourth aspect, a computer-readable storage medium provided in an embodiment of the present application stores a computer program, and when the computer program is executed, the scheduler testing method provided in the first aspect or any optional implementation manner of the first aspect is implemented.

The scheduler testing method provided by the application can send a first target number of test instructions to a processor to be tested, control operation data corresponding to the first target number of test instructions in a memory to be converted from an invalid state to an effective state according to a second target number of scheduling sequences respectively so as to cover all empty and full state combinations of a scheduling queue in a scheduler included in the processor to be tested, then obtain a group of target execution results of executing the first target number of test instructions by the processor to be tested under each scheduling sequence in the second target number of scheduling sequences so as to obtain a second target number of target execution results, and finally obtain a reliability test result for the scheduler according to the second target number of target execution results. Obviously, the core point of the scheduler testing method provided in the present application is that the operation data corresponding to the first target number of test instructions in the memory is controlled to be converted from the invalid state to the valid state according to the second target number of scheduling sequences, so as to cover all combinations of the empty and full states of the scheduling queue in the scheduler included in the processor to be tested.

The scheduler testing apparatus, the electronic device and the computer readable storage medium provided by the present application have the same advantages as the scheduler testing method, and are not described herein again.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.

Fig. 1 is a schematic structural block diagram of an electronic device according to an embodiment of the present application.

Fig. 2 is a flowchart illustrating steps of a scheduler testing method according to an embodiment of the present application.

Fig. 3 is a schematic structural block diagram of a scheduler testing apparatus according to an embodiment of the present application.

Reference numerals are as follows: 100-an electronic device; 110-a processor; 120-a memory device; 200-scheduler test apparatus; 210-a driver module; 220-a conversion module; 230-target execution result acquisition module; 240-test result acquisition module.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. Furthermore, it should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

Referring to fig. 1, a schematic block diagram of an electronic device 100 according to an embodiment of the present disclosure is shown. In this embodiment of the application, the electronic Device 100 may be a terminal Device, such as a computer, a Personal Digital Assistant (PAD), a Mobile Internet Device (MID), or a server, and the embodiment of the application is not limited thereto.

Structurally, electronic device 100 may include a processor 110 and a memory device 120.

The processor 110 and the memory device 120 are electrically connected, directly or indirectly, to enable data transfer or interaction, e.g., the elements may be electrically connected to each other via one or more communication buses or signal lines. The processor 110 is configured to execute executable modules stored in the storage device 120, for example, software functional modules and computer programs included in the scheduler testing apparatus, so as to implement the scheduler testing method.

The processor 110 may execute the computer program upon receiving the execution instruction. The processor 110 may be an integrated circuit chip having signal processing capabilities. The Processor 110 may also be a general-purpose Processor, for example, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a discrete gate or transistor logic device, a discrete hardware component, which can implement or execute the methods, steps, and logic blocks disclosed in the embodiments of the present Application, and furthermore, the general-purpose Processor may be a microprocessor or any conventional Processor.

The Memory device 120 may be, but is not limited to, a Random Access Memory (RAM), a Read Only Memory (ROM), a Programmable Read-Only Memory (PROM), an Erasable Programmable Read-Only Memory (EPROM), and an electrically Erasable Programmable Read-Only Memory (EEPROM). The memory device 120 is used to store programs, and the processor 110 executes the computer programs after receiving execution instructions.

It should be understood that the structure shown in fig. 1 is merely an illustration, and the electronic device 100 provided in the embodiment of the present application may have fewer or more components than those shown in fig. 1, or may have a different configuration than that shown in fig. 1. Further, the components shown in fig. 1 may be implemented by software, hardware, or a combination thereof.

Please refer to fig. 2, which is a flowchart illustrating a scheduler testing method according to an embodiment of the present application, where the method is applied to the electronic device 100 shown in fig. 1. It should be noted that, the scheduler testing method provided in the embodiment of the present application is not limited by the sequence shown in fig. 2 and the following order, and the specific flow and steps of the scheduler testing method are described below with reference to fig. 2.

Step S100, sending the first target number of test instructions to the processor to be tested.

In the embodiment of the present application, the test instruction may include address information, and the address information is used to characterize a storage space in which operation data corresponding to the test instruction is located in the memory. For example, the address information in test instruction insn addr0 is addr0, and addr0 represents the storage space pointed by addr0 in the memory of the operation data corresponding to test instruction insn addr 0. In the embodiment of the present application, "insn" is used to indicate a certain instruction in one instruction set, and does not refer to a specific instruction, for example, insn addr0 may be Add r0 addr0, insn addr0 may also be Sub r0 addr0, and insn addr0 may also be Xor r r0 addr0, which is not limited in the embodiment of the present application.

In addition, it should be noted that, in the embodiment of the present application, the test instruction may be generated in advance when the test initiation request is received, that is, if the test initiation request is received, a first target number of test instructions are generated in response to the test initiation request, operands corresponding to the first target number of test instructions are located in different storage spaces in the memory, and no correlation exists between any two test instructions in the first target number of test instructions. The absence of correlation between any two test instructions in the first target number of test instructions may be understood as the absence of a dependency relationship between any two test instructions in the first target number of test instructions, where the dependency relationship includes data dependency, control dependency, address dependency, and the like.

It should be further noted that, in this embodiment of the application, a value of the first target number needs to be determined according to the number of queue entries of a scheduling queue in a scheduler included in a processor to be tested, and specifically, in actual implementation, the first target number may be controlled to be greater than or equal to the number of queue entries of the scheduling queue. For example, when the number of queue entries of the scheduling queue is 4, the first target number may be set to 4, or the first target number may be set to 5.

Step S200, respectively according to the second target number scheduling order, controlling the operation data corresponding to the first target number of test instructions in the memory to be converted from the invalid state to the valid state, so as to cover all empty and full state combinations of the scheduling queue in the scheduler included in the processor to be tested.

It should be noted that, in this embodiment of the application, it needs to be ensured that step S200 is executed, and when the operation data corresponding to the first target number of test instructions in the memory is controlled to be converted from the invalid state to the valid state according to the second target number of scheduling sequences, all empty and full state combinations of the scheduling queue in the scheduler included in the processor to be tested can be covered.

Taking the number of queue entries of the scheduling queue as 4, specifically including scheduling queue entry 0, scheduling queue entry 1, scheduling queue entry 2, and scheduling queue entry 3 as an example, 2^4, that is, 16 empty and full state combinations of the scheduling queue are represented by { scheduling queue entry 3, scheduling queue entry 2, scheduling queue entry 1, scheduling queue entry 0}, and then, all empty and full state combinations of the number of scheduling queue entries are as shown in table 1, where 0 represents empty and 1 represents full. For example, 0001 indicates that scheduler queue entry 0 is full, scheduler queue entry 1, scheduler queue entry 2, and scheduler queue entry 3 are empty, 1000 indicates that scheduler queue entry 0, scheduler queue entry 1, and scheduler queue entry 2 are empty, scheduler queue entry 3 is full, and 1111 indicates that scheduler queue entry 0, scheduler queue entry 1, scheduler queue entry 2, and scheduler queue entry 3 are all full.

It can be understood that, in this embodiment of the application, the empty-full state 1111 of the scheduling queue is to perform step S100, after the first target number of test instructions are sent to the processor to be tested, the initial empty-full state combination of the scheduling queue, that is, the initial empty-full state of the scheduling queue is full of the scheduler queue, and in step S200, before the operation data corresponding to the first target number of test instructions in the memory is controlled to be converted from the invalid state to the valid state according to the second target number of scheduling orders, the initial empty-full state of the scheduling queue remains unchanged.

TABLE 1

0000	0001	0010	0011	0100	0101	0110	0111
								1000	1001	1010	1011	1100	1101	1110	1111

For setting the second target number of scheduling orders, in this embodiment of the present application, as a first optional implementation manner, in the case that the number of queue entries of the scheduling queue is small (for example, the number of queue entries of the scheduling queue is less than or equal to 4), the second target number of scheduling orders may be manually set by a tester.

Similarly, taking the number of queue entries of the scheduling queue as 4, specifically including scheduling queue entry 0, scheduling queue entry 1, scheduling queue entry 2, and scheduling queue entry 3 as an example, it is assumed that the first target number is 4, and the 4 test instructions are: the correspondence between the insn addr0, insn addr1, insn addr2, and insn addr3,4 test instructions and all queue items in the scheduling queue (storage locations of the 4 test instructions in the scheduling queue) is shown in table 2, and then 6 scheduling sequences shown in table 3 may be set to ensure that step S200 is executed, and when the operation data corresponding to the 4 test instructions in the memory is controlled to be converted from the invalid state to the valid state according to the 6 scheduling sequences shown in table 2, all empty and full state combinations of the scheduling queue in the scheduler included in the processor to be tested can be covered. It is understood that, in this case, the second target number is 6, that is, the scheduling orders of the second target number are the 6 scheduling orders shown in table 2. In addition, it is to be understood that in the embodiment of the present application, since "insn" is used to indicate a certain instruction in one instruction set, and does not refer to a specific instruction, in actual implementation, insn addr0 may be addr0, insn addr1 may be Sub r1 addr1, insn addr2 may be Xor r2 addr2, and insn addr3 may be addr3, and of course, insn addr0, insn addr1, insn addr2, and insn addr3 may also be other 4 specific instructions, which is not limited in this embodiment of the present application.

TABLE 2

Scheduling queue entries for a queue	Test instructions
		Dispatch queue entry 0	insn addr0
Scheduling queue entry 1	insn addr1
		Dispatch queue entry 2	insn addr2
Scheduling queue entry 3	insn addr3

TABLE 3

Sequence number of scheduling	Scheduling order
		Scheduling order 0	insn addr0、insn addr1、insn addr2、insn addr3
Scheduling order 1	insn addr1、insn addr2、insn addr3、insn addr0
		Scheduling order 2	insn addr2、insn addr3、insn addr0、insn addr1
Scheduling sequence 3	insn addr3、insn addr0、insn addr1、insn addr2
		Scheduling order 4	insn addr3、insn addr1、insn addr0、insn addr2
Scheduling order 5	insn addr2、insn addr0、insn addr1、insn addr3

Taking the scheduling sequence 0 as an example, the method controls the operation data corresponding to 4 test instructions in the memory to be converted from the invalid state to the valid state according to the scheduling sequence 0, and the combination of the empty and full states capable of covering a scheduling queue in a scheduler included in the processor to be tested includes: 1111. 1110, 1100, 1000 and 0000, the specific conversion process of which is shown in table 4.

TABLE 4

Taking dispatch sequence 1 as an example, controlling the operation data corresponding to 4 test instructions in the memory to be converted from an invalid state to an valid state according to dispatch sequence 1, and combining the empty and full states of a dispatch queue in a scheduler capable of covering a processor to be tested includes: 1111. 1101, 1001, 0001 and 0000, the specific conversion process of which is shown in table 5.

TABLE 5

Taking the scheduling sequence 2 as an example, controlling the operation data corresponding to 4 test instructions in the memory to be converted from the invalid state to the valid state according to the scheduling sequence 2, and combining the empty and full states of the scheduling queue in the scheduler, which can cover the processor to be tested, includes: 1111. 1011, 0011, 0010 and 0000, the specific conversion process thereof is shown in table 6.

TABLE 6

Taking the scheduling sequence 3 as an example, controlling the operation data corresponding to 4 test instructions in the memory to be converted from the invalid state to the valid state according to the scheduling sequence 3, and combining the empty and full states of the scheduling queue in the scheduler, which can cover the processor to be tested, includes: 1111. 0111, 0110, 0100 and 0000, and the specific conversion process is shown in table 7.

TABLE 7

Taking the scheduling sequence 4 as an example, the method controls the operation data corresponding to 4 test instructions in the memory to be converted from the invalid state to the valid state according to the scheduling sequence 4, and the combination of the empty and full states capable of covering the scheduling queue in the scheduler included in the processor to be tested includes: 1111. 0111, 0101, 0100 and 0000, and the specific conversion process is shown in Table 8.

TABLE 8

Taking the scheduling sequence 5 as an example, controlling the operation data corresponding to 4 test instructions in the memory to be converted from the invalid state to the valid state according to the scheduling sequence 5, and combining the empty and full states of the scheduling queue in the scheduler, which can cover the processor to be tested, includes: 1111. 1011, 1010, 1000 and 0000, the specific conversion process of which is shown in table 9.

TABLE 9

Obviously, the combination of the empty and full states of the scheduling queues shown in tables 4 to 9 can cover all the combinations of the empty and full states of the scheduling queues in the scheduler included in the processor under test.

However, in an actual implementation process, there may be a case where the number of queue items of the scheduling queue is large, and in the case where the number of queue items of the scheduling queue is large, if the second target number scheduling order is still manually set by a tester, the setting process is often tedious, so for setting the second target number scheduling order, in this embodiment of the application, as a second optional implementation manner, in the case where the number of queue items of the scheduling queue is large (for example, the number of queue items of the scheduling queue is greater than 4), the second target number scheduling order may be implemented by a preset scheduling order setting algorithm.

Certainly, in order to reduce the complexity of the process of setting the second target number of scheduling orders, under the condition that the number of queue entries of the scheduling queue is small, the second target number of scheduling orders may also be implemented by using a preset scheduling order setting algorithm, for example, when the number of queue entries of the scheduling queue is 4, the second target number of scheduling orders may also be implemented by using the preset scheduling order setting algorithm, which is not specifically limited in the embodiment of the present application.

Based on the above description, the method for testing a scheduler according to the embodiment of the present application may further include step S001 and step S002 before step S200 is executed to control the operation data corresponding to the first target number of test instructions in the memory to be converted from the invalid state to the valid state according to the second target number of scheduling orders, respectively.

And S001, acquiring the queue item number of the scheduling queue.

And step S002, obtaining a second target number scheduling sequence according to the number of queue items.

In the embodiment of the application, after the number of items of the scheduling queue is obtained, the number of items can be realized through a preset scheduling sequence setting algorithm, and the program idea of the scheduling sequence setting algorithm can be described through step S0021, step S0022, step S0023, and step S0024.

Step S0021, establishing a corresponding relation between the first target quantity test instruction and all queue entries in the scheduling queue.

As described above, in this embodiment of the present application, the correspondence between the first target number of test instructions and all queue entries in the scheduling queue may be understood as a storage location of the first target number of test instructions in the scheduling queue. Taking the number of queue entries of the scheduling queue as 4, specifically including a scheduling queue entry 0, a scheduling queue entry 1, a scheduling queue entry 2, and a scheduling queue entry 3, the first target number is 4, and the 4 test instructions are respectively: insn addr0, insn addr1, insn addr2 and insn addr3 are taken as examples, and the correspondence between 4 test instructions and all queue entries in the dispatch queue (storage locations of the 4 test instructions in the dispatch queue) is shown in table 2.

And step S0022, setting a third target quantity stepping value according to the queue item number.

In the embodiment of the present application, first, a step value interval may be set according to the number of queue entries, for example, if the number of queue entries is N, the step value interval may be set to [1, N-1], and then, an integer is taken out from the step value interval to serve as a third target number of step values. For example, if the number of queue entries N is 4, the step value interval is [1,3], and then the third target number is 3,3 step values, 1, 2, and 3, respectively.

And step S0023, traversing the scheduling queue according to the stepping values of the third target quantity by taking the queue item as the initial position for each queue item in the scheduling queue, and obtaining the scheduling sequence of the third target quantity according to the traversal result.

It should be noted that, in this embodiment, when step S0023 is executed, for a certain queue entry, for example, the scheduling queue entry 0 is used as a starting position, when the scheduling queue is traversed according to the third target number of step values respectively, each time one queue entry is accessed, the empty-full state of the queue entry is marked as empty from full, if the empty-full state of the queue entry that should be currently accessed is already marked as empty, all queue entries whose empty-full states are full at the current time need to be determined, and then, according to any scheduling order, the empty-full states of all queue entries whose empty-full states are full at the current time are respectively marked as empty. It should be noted that, in the embodiment of the present application, the empty-full state of a certain queue entry is marked as empty, which is understood to be that, it is assumed in advance that the data state of the operation data in the memory corresponding to the test instruction stored in a certain queue entry is a valid state, and after the test instruction stored in the queue entry is scheduled, the empty-full state of the queue entry is empty.

Similarly, taking the number of queue entries of the scheduling queue as 4, specifically including a scheduling queue entry 0, a scheduling queue entry 1, a scheduling queue entry 2, and a scheduling queue entry 3, the first target number is 4, and the number of the test instructions is respectively: insn addr0, insn addr1, insn addr2 and insn addr3 are taken as examples, the corresponding relation between 4 test instructions and all queue items in the scheduling queue is shown in table 2, and 3 stepping values are 1, 2 and 3 respectively, then step S0023 is performed by traversing the scheduling queue according to a third target number of stepping values by taking the queue items as initial positions for each queue item in the scheduling queue, and obtaining an execution process of a third target number of scheduling orders according to a traversal result, which can be described by combining tables 11 to 27. For convenience of description, the scheduling queue entry 0 is characterized as b0, the scheduling queue entry 1 is characterized as b1, the scheduling queue entry 2 is characterized as b2, and the scheduling queue entry is characterized as b3 in tables 11 to 27.

TABLE 11

TABLE 12

Watch 13

In this embodiment, when step S0023 is executed in table 11, table 12, and table 13, b0 is used as an initial position, the scheduling queues are traversed according to 3 step values, and 3 scheduling orders are obtained according to the traversal result, where the 3 scheduling orders are shown in table 14.

TABLE 14

Sequence number of scheduling	Scheduling order
		Scheduling order 0	insn addr0、insn addr1、insn addr2、insn addr3
Scheduling order 1	insn addr0、insn addr2、insn addr1、insn addr3
		Scheduling order 2	insn addr0、insn addr3、insn addr2、insn addr1

Watch 15

TABLE 16

TABLE 17

In this embodiment, when step S0023 is executed in table 15, table 16, and table 17, b1 is used as an initial position, the scheduling queues are traversed according to 3 step values, and 3 scheduling orders are obtained according to the traversal result, where the 3 scheduling orders are shown in table 18.

Watch 18

Sequence number of scheduling	Scheduling order
		Scheduling sequence 3	insn addr1、insn addr2、insn addr3、insn addr0
Scheduling order 4	insn addr1、insn addr3、insn addr2、insn addr0
		Scheduling order 5	insn addr1、insn addr0、insn addr3、insn addr2

Watch 19

Watch 20

TABLE 21

In this embodiment, when step S0023 is executed in table 19, table 20, and table 21, b2 is used as an initial position, the scheduling queue is traversed according to 3 stepping values, and 3 scheduling orders are obtained according to a traversal result, where the 3 scheduling orders are shown in table 22.

TABLE 22

Sequence number of scheduling	Scheduling order
		Scheduling order 6	insn addr2、insn addr3、insn addr0、insn addr1
Scheduling sequence 7	insn addr2、insn addr0、insn addr3、insn addr1
		Scheduling sequence 8	insn addr2、insn addr1、insn addr0、insn addr3

TABLE 23

Watch 24

TABLE 25

In this embodiment, when step S0023 is executed in table 23, table 24, and table 25, b3 is used as an initial position, the scheduling queues are traversed according to 3 step values, and 3 scheduling orders are obtained according to the traversal result, where the 3 scheduling orders are shown in table 26.

Watch 26

Sequence number of dispatch	Scheduling order
		Scheduling order 9	insn addr3、insn addr0、insn addr1、insn addr2
Scheduling sequence 10	insn addr3、insn addr1、insn addr0、insn addr2
		Scheduling order 11	insn addr3、insn addr2、insn addr1、insn addr0

Step S0024, the third target quantity scheduling sequences corresponding to each queue entry in the scheduling queue are collectively used as the second target quantity scheduling sequences.

When step S0023 is executed, the number of queue entries of the scheduling queue is 4, specifically including a scheduling queue entry 0, a scheduling queue entry 1, a scheduling queue entry 2, and a scheduling queue entry 3, the first target number is 4, and the number of 4 test instructions is respectively: for example, insn addr0, insn addr1, insn addr2, and insn addr3, 3 scheduling sequences corresponding to each queue entry in the scheduling queue are shown in table 14, table 18, table 22, and table 26, respectively, that is, the second target number is 12, and 12 scheduling sequences are integrated and shown in table 27.

Watch 27

Sequence number of dispatch	Scheduling order
		Scheduling order 0	insn addr0、insn addr1、insn addr2、insn addr3
Scheduling order 1	insn addr0、insn addr2、insn addr1、insn addr3
		Scheduling order 2	insn addr0、insn addr3、insn addr2、insn addr1
Scheduling order 3	insn addr1、insn addr2、insn addr3、insn addr0
		Scheduling order 4	insn addr1、insn addr3、insn addr2、insn addr0
Scheduling order 5	insn addr1、insn addr0、insn addr3、insn addr2
		Scheduling order 6	insn addr2、insn addr3、insn addr0、insn addr1
Scheduling order 7	insn addr2、insn addr0、insn addr3、insn addr1
		Scheduling order 8	insn addr2、insn addr1、insn addr0、insn addr3
Scheduling order 9	insn addr3、insn addr0、insn addr1、insn addr2
		Scheduling sequence 10	insn addr3、insn addr1、insn addr0、insn addr2
Scheduling order 11	insn addr3、insn addr2、insn addr1、insn addr0

It should be noted that, in the embodiment of the present application, the method for setting the second target number of scheduling orders by using the first optional implementation manner is generally only applicable to a case where the number of queue entries of the scheduling queue is small, and this implementation manner has strong controllability and a large degree of freedom because the second target number of scheduling orders are manually set by a tester, and can avoid a situation where a certain queue entry in the scheduling queue is empty and full in a more repeated manner, but the drawback of setting the second target number of scheduling orders by using the first optional implementation manner is that: under the condition that the number of queue entries of the scheduling queue is large, if the scheduling sequence of the second target number is still manually set by a tester, the setting process is often complicated. As for the method for setting the second target number of scheduling sequences by the second optional implementation manner, since the method is implemented by the preset scheduling sequence setting algorithm, which is usually only applicable to the regular events, in order to meet the requirement of the regular events, it is inevitable that a certain queue entry in the scheduling queue has a more repeated empty and full state, but the method for setting the second target number of scheduling sequences by the second optional implementation manner has the advantages that: under the condition that the number of queue entries of the scheduling queue is large, the second target number scheduling sequences can still be rapidly acquired.

After the second target number of scheduling orders are set through the first optional implementation manner or the second optional implementation manner, step S200 may be executed to control the operation data corresponding to the first target number of test instructions in the memory to be converted from the invalid state to the valid state according to the second target number of scheduling orders, respectively. As for step S200, in the embodiment of the present application, as an optional implementation manner, it may include step S210 and step S220.

Step S210, for each scheduling order in the second target number scheduling orders, a state transition instruction is generated at intervals according to the scheduling order.

Step S220, each time a bar state transition instruction is generated, sending the state transition instruction to the memory, so that the memory requests mapping target data from the next-level storage device of the memory according to the state transition instruction, where the target data is operation data required for executing a test instruction corresponding to the state transition instruction, and the operation data corresponding to the test instruction is converted from an invalid state to an valid state.

In the embodiment of the present application, the state transition instruction is a control instruction different from the test instruction, and belongs to a command for switching the operation data corresponding to a certain memory address from the invalid state to the valid state in the control memory, or may be understood as a control command for switching the operation data corresponding to a certain memory address from the invalid state to the valid state in the control memory by the scheduler. The scheduler testing platform is a simulation platform for implementing the scheduling testing method provided by the embodiment of the application. In addition, in the embodiment of the present application, the preset conversion duration may be specifically set according to the test precision, and the embodiment of the present application does not specifically limit this.

In addition, it should be noted that, in this embodiment of the present application, the storage is actually a first-level Cache memory (Cache), if the processor to be tested is a multi-Cache processor, that is, if the processor to be tested includes a second-level Cache in addition to the first-level Cache, or even more, the next-level storage device of the storage is the second-level Cache, and if the processor to be tested only includes the first-level Cache, the next-level storage device of the destination storage is an internal memory. It should be further noted that, in an actual implementation process of the scheduler testing method provided in the embodiment of the present application, a virtual memory model may be used to replace a memory, that is, in the embodiment of the present application, the memory may be a physical memory or a virtual memory model.

And taking the number of queue entries of the scheduling queue as 4, specifically including a scheduling queue entry 0, a scheduling queue entry 1, a scheduling queue entry 2 and a scheduling queue entry 3, wherein the first target number is 4, and the 4 test instructions are respectively: insn addr0, insn addr1, insn addr2 and insn addr3 are taken as examples, and for the scheduling order 0: the method comprises the steps of generating an insn addr0, insn addr1, insn addr2 and insn addr3, firstly, generating a state conversion instruction 0, sending the state conversion instruction 0 to a memory, enabling the memory to request a next-level storage device of the memory to map operation data required for executing insn addr0 according to the state conversion instruction 0 so as to convert the operation data corresponding to a storage address addr0 in the memory from an invalid state into an effective state, generating a state conversion instruction 1 after a first preset conversion duration, sending the state conversion instruction 1 to the memory, enabling the memory to request the next-level storage device of the memory to map the operation data required for executing insn addr1 according to the state conversion instruction 1 so as to convert the operation data corresponding to the storage address addr1 in the memory from the invalid state into the effective state, generating a state conversion instruction 2 after a second preset conversion duration, sending the state conversion instruction 2 to the memory, enabling the memory to request the next-level storage device of the insn addr2 according to convert the operation data required for executing the insn addr2 into the effective state, converting the operation data into the first preset conversion duration, and sending the operation data to the next-level storage device to convert the invalid state, and sending the operation data to the next-level storage device to generate the invalid state.

Step S300, the processor to be tested executes the first target quantity test instructions under each scheduling sequence of the second target quantity scheduling sequences to obtain a group of target execution results, so as to obtain a second target quantity group of target execution results.

In this embodiment of the present application, when the operation data corresponding to the first target number of test instructions in the memory is controlled to be converted from the invalid state to the valid state according to each scheduling order in the second target number of scheduling orders, the processor to be tested may schedule and execute the first target number of test instructions through a scheduler included in the processor to be tested, obtain a set of target execution results, and finally obtain second target number group target execution results corresponding to the second target number of scheduling orders one to one.

And step S400, obtaining a reliability test result aiming at the scheduler according to the target execution result of the second target quantity group.

In this embodiment, when step S400 is executed, the second target number group target execution results need to be compared with the standard execution results to obtain comparison results, and then reliability test results for the scheduler are obtained according to the comparison results, that is, in this embodiment, step S400 may include step S410 and step S420.

Step S410, comparing the second target quantity group target execution result with the standard execution result, respectively, to obtain a comparison result.

Step S420, obtaining a reliability test result for the scheduler according to the comparison result.

In practical implementation, if the comparison result indicates that a target execution result different from the standard execution result exists in the second target quantity group of target execution results, a first test result is obtained, wherein the first test result is used for indicating that the reliability of the scheduler does not meet the preset test requirement, and if the comparison result indicates that the target execution result different from the standard execution result does not exist in the second target quantity group of target execution results, a second test result is obtained, wherein the second test result is used for indicating that the reliability of the scheduler meets the preset test requirement.

Further, as for the standard execution result, in the embodiment of the present application, before executing step S400, it may be acquired through step S003.

And S003, executing the first target quantity test instructions by the processor model under any one scheduling sequence in the second target quantity scheduling sequences to obtain a group of execution results serving as standard execution results.

In this embodiment of the present application, for any scheduling order in the second target number scheduling orders, when the operation data corresponding to the first target number of test instructions in the memory is controlled to be converted from the invalid state to the valid state according to the scheduling order, the processor model schedules and executes the first target number of test instructions through the scheduler included in the processor model, so as to obtain a group of execution results, where the group of execution results is a standard execution result.

In summary, the scheduler testing method provided in the embodiment of the present application can send a first target number of test instructions to a to-be-tested processor, and control operation data corresponding to the first target number of test instructions in a memory to be converted from an invalid state to an valid state according to second target number scheduling orders, so as to cover all empty and full state combinations of a scheduling queue in the scheduler included in the to-be-tested processor, and then obtain a group of target execution results obtained by the to-be-tested processor executing the first target number of test instructions in each scheduling order in the second target number scheduling orders, so as to obtain a second target number group of target execution results, and finally obtain a reliability test result for the scheduler according to the second target number group of target execution results. Obviously, the core point of the scheduler testing method provided in the present application is that the operation data corresponding to the first target number of test instructions in the memory is controlled to be converted from the invalid state to the valid state according to the second target number of scheduling sequences, so as to cover all combinations of the empty and full states of the scheduling queue in the scheduler included in the processor to be tested.

Based on the same inventive concept as the scheduler testing method, the embodiment of the present application further provides a scheduler testing apparatus 200. Referring to fig. 3, a scheduler testing apparatus 200 according to an embodiment of the present application includes a driving module 210, a converting module 220, a target execution result obtaining module 230, and a testing result obtaining module 240.

The driving module 210 is configured to send the first target number of test instructions to the processor to be tested.

The conversion module 220 is configured to control, according to the second target number scheduling order, that the operation data corresponding to the first target number of test instructions in the memory is converted from the invalid state to the valid state, so as to cover all empty and full state combinations of the scheduling queue in the scheduler included in the processor to be tested.

The target execution result obtaining module 230 is configured to obtain a group of target execution results obtained by executing the first target quantity test instructions by the processor to be tested in each scheduling order of the second target quantity scheduling orders, so as to obtain a second target quantity group of target execution results.

And a test result obtaining module 240, configured to obtain a reliability test result for the scheduler according to the second target number group target execution result.

The scheduler testing apparatus 200 provided in the embodiment of the present application may further include an instruction generating module.

The instruction generation module is used for responding to the test starting request and generating a first target number of test instructions when the test starting request is received, operands corresponding to the first target number of test instructions are located in different storage spaces in a memory, and no correlation exists between any two test instructions in the first target number of test instructions.

In an embodiment of the present application, the transition module 220 may include a first state transition unit and a second state transition unit.

And the first state conversion unit is used for generating a state conversion instruction according to each scheduling sequence in the second target number scheduling sequences and at intervals of a preset conversion duration according to the scheduling sequence.

And the second state conversion unit is used for sending the state conversion instruction to the memory every time a strip state conversion instruction is generated, so that the memory requests the next-level storage device of the memory to map target data according to the state conversion instruction, wherein the target data is operation data required by executing a test instruction corresponding to the state conversion instruction, and the operation data corresponding to the test instruction is converted from an invalid state to a valid state.

The scheduler testing apparatus 200 provided in the embodiment of the present application may further include an item number obtaining module and a sequence setting module.

And the item number acquisition module is used for acquiring the queue item number of the scheduling queue.

And the sequence setting module is used for obtaining a second target number scheduling sequence according to the number of the queue items.

In this embodiment of the present application, the order setting module may include a correspondence creating unit, a step value setting unit, a queue traversing unit, and an order setting unit.

And the corresponding relation creating unit is used for creating the corresponding relation between the first target quantity of test instructions and all queue items in the scheduling queue.

And the step value setting unit is used for setting a step value of a third target number according to the number of the queue items.

And the queue traversing unit is used for traversing the scheduling queue according to the stepping values of the third target quantity by taking the queue entries as the initial positions for each queue entry in the scheduling queue, and obtaining the scheduling sequence of the third target quantity according to the traversing result.

And the sequence setting unit is used for taking the third target quantity scheduling sequences corresponding to each queue entry in the scheduling queue as the second target quantity scheduling sequences together.

In this embodiment, the test result obtaining module 240 may include a comparing unit and a test result obtaining unit.

And the comparison unit is used for comparing the target execution results of the second target quantity group with the standard execution results respectively to obtain comparison results.

And the test result acquisition unit is used for acquiring a reliability test result aiming at the scheduler according to the comparison result.

In this embodiment, the reliability test result may include a first test result and a second test result, and the test result obtaining unit may include a first test result obtaining subunit and a second test result obtaining subunit.

And the first test result obtaining subunit is used for obtaining a first test result when the comparison result represents that a target execution result different from the standard execution result exists in the second target quantity group target execution results, wherein the first test result is used for representing that the reliability of the scheduler does not meet the preset test requirement.

And the second test result obtaining subunit is configured to obtain a second test result when the comparison result indicates that no target execution result different from the standard execution result exists in the second target number group target execution results, where the second test result is used to indicate that the reliability of the scheduler meets the preset test requirement.

The scheduler testing apparatus 200 provided in the embodiment of the present application may further include a standard execution result obtaining module.

And the standard execution result acquisition module is used for acquiring any one of the second target quantity scheduling sequences, and the processor model executes the first target quantity of test instructions to obtain a group of execution results as a standard execution result.

Since the scheduler testing apparatus 200 provided in the embodiment of the present application is implemented based on the same inventive concept as the scheduler testing method, specific descriptions of each software module in the scheduler testing apparatus 200 can be referred to the related descriptions of the corresponding steps in the scheduler testing method embodiment, and are not described herein again.

In addition, an embodiment of the present application further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed, the scheduler testing method provided in the foregoing method embodiment is implemented.

To sum up, the scheduler testing method provided in this embodiment of the present application can send a first target number of test instructions to a to-be-tested processor, and respectively control, according to a second target number of scheduling orders, operation data corresponding to the first target number of test instructions in a memory to be converted from an invalid state to an valid state so as to cover all empty and full state combinations of a scheduling queue in a scheduler included in the to-be-tested processor, and then obtain, under each of the second target number of scheduling orders, a group of target execution results obtained by the to-be-tested processor executing the first target number of test instructions so as to obtain a second target number of group of target execution results, and finally obtain, according to the second target number of group of target execution results, a reliability test result for the scheduler. Obviously, the core point of the scheduler testing method provided by the present application is that the operation data corresponding to the first target number of test instructions in the memory is controlled to be converted from the invalid state to the valid state according to the second target number of scheduling sequences, so as to cover all combinations of the empty and full states of the scheduling queue in the scheduler included in the processor to be tested.

The scheduler testing apparatus, the electronic device and the computer readable storage medium provided in the embodiments of the present application have the same advantages as the scheduler testing method described above, and are not described herein again.

In the several embodiments provided in the embodiments of the present application, it should be understood that the disclosed method and apparatus may be implemented in other ways. The apparatus embodiments described above are merely illustrative, and for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions. In addition, the functional modules in each embodiment of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

Further, the functions may be stored in a computer-readable storage medium if they are implemented in the form of software functional modules and sold or used as independent products. Based on such understanding, the technical solutions of the present application, or portions thereof, which substantially or partly contribute to the prior art, may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to perform all or part of the steps of the method described in each embodiment of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a U disk, a removable hard disk, a ROM, a RAM, a magnetic disk, or an optical disk.

It is further noted that, herein, relational terms such as "first," "second," "third," and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

Claims

1. A scheduler testing method, comprising:

sending a first target number of test instructions to a processor to be tested;

respectively controlling the operation data corresponding to the first target number of test instructions in the memory to be converted from an invalid state to an effective state according to a second target number scheduling sequence so as to cover all empty and full state combinations of a scheduling queue in a scheduler included in the processor to be tested;

acquiring a group of target execution results of the processor to be tested, wherein the group of target execution results are acquired by executing the first target quantity test instructions under each scheduling sequence of the second target quantity scheduling sequences so as to acquire a second target quantity group of target execution results;

obtaining a reliability test result aiming at the scheduler according to the second target quantity group target execution result;

before the step of controlling the operation data corresponding to the first target number of test instructions in the memory to be converted from the invalid state to the valid state according to the second target number of scheduling sequences, the scheduler testing method further includes:

acquiring the queue item number of the scheduling queue;

creating a corresponding relation between the first target quantity test instruction and all queue items in the scheduling queue;

for each queue entry in the scheduling queue, traversing the scheduling queue according to the third target quantity step values by taking the queue entry as an initial position, and obtaining a third target quantity scheduling sequence according to a traversal result;

2. The scheduler testing method according to claim 1, wherein before sending the first target number of test instructions to the processor under test, the scheduler testing method further comprises:

and if a test starting request is received, responding to the test starting request, and generating the first target quantity of test instructions, wherein operands corresponding to the first target quantity of test instructions are located in different storage spaces in the memory, and no correlation exists between any two test instructions in the first target quantity of test instructions.

3. The scheduler testing method according to claim 1, wherein said controlling the operation data corresponding to the first target number of test instructions in the memory to be converted from the invalid state to the valid state according to the second target number of scheduling orders, respectively, comprises:

generating a state transition instruction for each scheduling sequence in the second target number scheduling sequences at intervals of a preset transition duration according to the scheduling sequence;

and sending the state conversion instruction to the memory every time a strip state conversion instruction is generated, so that the memory requests mapping target data from a next-level storage device of the memory according to the state conversion instruction, wherein the target data is operation data required by executing a test instruction corresponding to the state conversion instruction, and the operation data corresponding to the test instruction is converted from an invalid state to a valid state.

4. The scheduler testing method according to claim 1, wherein said obtaining reliability test results for the scheduler according to the second target number group target execution results comprises:

comparing the second target quantity group target execution results with standard execution results respectively to obtain comparison results;

and obtaining a reliability test result aiming at the scheduler according to the comparison result.

5. The scheduler testing method according to claim 4, wherein the reliability test result comprises a first test result and a second test result, and the obtaining the reliability test result for the scheduler according to the comparison result comprises:

if the comparison result represents that a target execution result different from the standard execution result exists in the target execution results of the second target quantity group, obtaining the first test result, wherein the first test result is used for representing that the reliability of the scheduler does not meet the preset test requirement;

and if the comparison result represents that no target execution result different from the standard execution result exists in the second target quantity group target execution results, obtaining a second test result, wherein the second test result is used for representing that the reliability of the scheduler meets a preset test requirement.

6. The scheduler testing method of claim 4, wherein before comparing the second target number group target execution result with a standard execution result and obtaining a comparison result, the scheduler testing method further comprises:

and under any scheduling sequence in the second target quantity scheduling sequences, the processor model executes the first target quantity of test instructions to obtain a group of execution results as the standard execution results.

7. A scheduler testing apparatus, comprising:

the conversion module is used for controlling the operation data corresponding to the first target number of test instructions in the memory to be converted from an invalid state to an effective state according to a second target number scheduling sequence so as to cover all empty and full state combinations of a scheduling queue in a scheduler included in the processor to be tested;

a target execution result obtaining module, configured to obtain each scheduling order of the second target number scheduling orders, where the processor to be tested executes the first target number of test instructions to obtain a group of target execution results, so as to obtain a second target number group of target execution results;

a test result obtaining module, configured to obtain a reliability test result for the scheduler according to the second target number group target execution result;

the item number acquisition module is used for acquiring the queue item number of the scheduling queue;

the corresponding relation establishing unit is used for establishing the corresponding relation between the first target quantity test instructions and all queue items in the scheduling queue;

the step value setting unit is used for setting step values of a third target number according to the number of the queue items;

the queue traversing unit is used for traversing the scheduling queue according to the stepping values of the third target quantity by taking the queue items as initial positions aiming at each queue item in the scheduling queue and obtaining a scheduling sequence of the third target quantity according to a traversing result;

8. An electronic device, comprising a processor and a memory device, the memory device having a computer program stored thereon, the processor being configured to execute the computer program to implement the scheduler testing method of any of claims 1-6.

9. A computer-readable storage medium, having stored thereon a computer program which, when executed, implements the scheduler testing method of any of claims 1-6.