CN112379552A - Display panel and manufacturing method thereof - Google Patents
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- CN112379552A CN112379552A CN202011412085.6A CN202011412085A CN112379552A CN 112379552 A CN112379552 A CN 112379552A CN 202011412085 A CN202011412085 A CN 202011412085A CN 112379552 A CN112379552 A CN 112379552A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 69
- 239000004973 liquid crystal related substance Substances 0.000 claims abstract description 17
- 239000000463 material Substances 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 6
- 230000003071 parasitic effect Effects 0.000 abstract description 11
- 239000010408 film Substances 0.000 description 11
- 238000010586 diagram Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 230000007423 decrease Effects 0.000 description 4
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 4
- 230000000149 penetrating effect Effects 0.000 description 4
- 239000010409 thin film Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000001808 coupling effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Chemical & Material Sciences (AREA)
- Mathematical Physics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
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Abstract
In the display panel and the manufacturing method thereof disclosed by the application, the display panel comprises an array substrate, a color film substrate and a liquid crystal layer arranged between the array substrate and the color film substrate, wherein the array substrate comprises a lower plate common electrode, an insulating layer and a conducting wire, a plurality of through holes are formed in the conducting wire, and the through holes penetrate through the conducting wire. In addition, the conducting wire is the scanning line, and the through holes are formed in the conducting wire, so that the overlapping area of the conducting wire and the lower plate common electrode can be reduced, the overlapping area of the scanning line and the lower plate common electrode is reduced, parasitic capacitance generated between the scanning line and the lower plate common electrode is reduced, the stability of the lower plate common electrode signal is improved, and the stability of pixel signals in the panel is further maintained.
Description
Technical Field
The present disclosure relates to display technologies, and particularly to a display panel and a manufacturing method thereof.
Background
Currently, in the tft-lcd panel display industry, a panel manufacturer usually inputs scan line signals into the panel from two sides through a Gate Driver on Array (GOA) circuit, so that the scan lines cross and overlap with the lower common electrode, thereby generating a parasitic capacitance.
Moreover, since the scan line signal varies by a relatively large amount, it can be increased from-10 volts to 28 volts in general, and even the scan line signal may vary by a relatively large amount. Due to the existence of the capacitive coupling effect, the scan line is liable to interfere with the signal of the lower plate common electrode, thereby affecting the stability of the signal of the lower plate common electrode, further affecting the stability of the pixel signal inside the panel, and causing the problems of crosstalk and the like.
Therefore, how to reduce the parasitic capacitance between the scan line and the lower common electrode is an urgent problem to be solved by panel manufacturers.
Disclosure of Invention
The embodiment of the application provides a display panel and a manufacturing method thereof, which can solve the technical problem that the parasitic capacitance between a scanning line and a common electrode of a lower plate is overlarge.
An embodiment of the present application provides a display panel, including:
the display panel comprises an array substrate, a color film substrate and a liquid crystal layer arranged between the array substrate and the color film substrate, wherein the array substrate comprises:
a lower plate common electrode;
an insulating layer disposed on the lower plate common electrode;
the wire is arranged on the surface, far away from the lower plate common electrode, of the insulating layer, the projection of the lower plate common electrode is partially overlapped with the lower plate common electrode, a plurality of through holes are formed in the wire, and the through holes penetrate through the wire.
In the display panel provided by the embodiment of the application, the diameter of the minimum circumcircle of the cross section of the through hole is gradually reduced along the direction from the side, away from the insulating layer, of the wire to the side, close to the insulating layer, of the wire.
In the display panel provided by the embodiment of the application, the distance between two adjacent through holes is not less than the width of the conducting wire.
In the display panel provided by the embodiment of the application, the overlapping area of the projection of the conducting wire on the lower plate common electrode and the lower plate common electrode becomes smaller as the space between two adjacent through holes becomes smaller.
In the display panel provided by the embodiment of the application, the length of the diameter of the smallest circumscribed circle of the cross section of the part of the through hole, which is far away from the insulating layer, is equal to the width of the conducting wire.
In the display panel provided by the embodiment of the application, the cross section of the part of the through hole far away from the lower plate common electrode and the cross section of the part of the through hole close to the lower plate common electrode are both rectangular.
In the display panel provided in the embodiment of the present application, the display panel further includes a GOA circuit, and the GOA circuit is connected to the wire via hole.
The application also provides a manufacturing method of the display panel, which comprises the following steps:
providing an array substrate, a color film substrate and a liquid crystal material;
attaching the array substrate and the color film substrate in an opposite manner, and dripping the liquid crystal material between the array substrate and the color film substrate to obtain a liquid crystal box; wherein the content of the first and second substances,
before the step of providing the array substrate, the color film substrate and the liquid crystal material, the manufacturing method further comprises the step of forming the array substrate, wherein the step of forming the array substrate comprises the following steps:
forming a lower plate common electrode on the substrate;
forming an insulating layer on the lower plate common electrode;
forming a conductive line on the insulating layer, a projection of the conductive line on the lower plate common electrode partially overlapping the lower plate common electrode;
and a plurality of through holes are formed in the conducting wire and penetrate through the conducting wire.
In the method for manufacturing the display panel, the diameter of the minimum circumscribed circle of the cross section of the through hole is gradually reduced along the direction from the side of the wire far away from the insulating layer to the side of the wire close to the insulating layer.
In the method for manufacturing the display panel provided by the embodiment of the application, the cross section of the part of the through hole far away from the lower plate common electrode and the cross section of the part of the through hole close to the lower plate common electrode are both rectangular.
In the display panel and the manufacturing method thereof provided by the embodiment of the application, the conducting wire is a scanning line, and the through hole is formed in the scanning line, so that the overlapping area of the scanning line and the lower plate common electrode can be reduced, the parasitic capacitance generated between the scanning line and the lower plate common electrode is reduced, the stability of the lower plate common electrode signal is improved, and the stability of the pixel signal in the panel is further maintained. In addition, the through holes are formed in the scanning lines, and the scanning lines are formed behind the insulating layer and the lower plate common electrode, so that the through holes are formed in the scanning lines, the phenomenon that an insulator between the scanning lines and the lower plate common electrode is uneven in film forming is avoided, and the risk that the insulating layer is broken in high temperature and high humidity or other conditions to cause short circuit between the lower plate common electrode and the scanning lines is avoided.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic view of a first structure of an array substrate according to an embodiment of the present disclosure.
Fig. 2 is a schematic view of a second structure of the array substrate according to the embodiment of the present application.
Fig. 3 is a schematic view of a first structure of a display panel according to an embodiment of the present disclosure.
Fig. 4 is a second structural schematic diagram of a display panel according to an embodiment of the present application.
Fig. 5 is a schematic diagram of a third structure of a display panel according to an embodiment of the present application.
Fig. 6 is a schematic flowchart of a manufacturing method of a display panel according to an embodiment of the present disclosure.
Fig. 7 is a sub-flow diagram illustrating a manufacturing method of a display panel according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "length," "width," "thickness," "upper," "lower," and the like, as used herein, refer to an orientation or positional relationship as shown in the drawings, which is used for convenience in describing the present application and to simplify the description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be taken as limiting the present application. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between.
Specifically, referring to fig. 1, fig. 1 is a schematic view of a first structure of an array substrate according to an embodiment of the present disclosure, as shown in fig. 1, an array substrate 101 according to an embodiment of the present disclosure includes a lower plate common electrode 1011 and a conducting wire 1013 disposed on the lower plate common electrode 1011, a projection of the conducting wire 1013 on the lower plate common electrode 1011 partially overlaps with the lower plate common electrode 1011, and the conducting wire 1013 has a plurality of through holes 1014 formed therein, and the through holes 1014 penetrate through the conducting wire 1013.
The array substrate 101 further includes a substrate, a thin film transistor layer, and a planarization layer, where the thin film transistor is disposed on the substrate, the planarization layer is disposed on the thin film transistor, and the lower common electrode 1011 is disposed on the planarization layer.
Here, it is understood that the through hole 1014 penetrates the wire 1013, and providing the through hole 1014 penetrating the wire 1013 on the wire 1013 can reduce the overlapping area of the wire 1013 and the lower plate common electrode 1011; since the lead wire 1013 is a scan line, reducing the overlapping area between the lead wire 1013 and the lower plate common electrode 1011 can reduce the overlapping area between the scan line and the lower plate common electrode 1011, thereby reducing the parasitic capacitance between the scan line and the lower plate common electrode 1011, improving the signal stability of the lower plate common electrode 1011, and further maintaining the signal stability of the pixels inside the panel.
Wherein, in one embodiment, the spacing between two adjacent vias 1014 is no less than the width of the wire 1013.
When the pitch between two adjacent vias 1014 is smaller than the width of the wire 1013, the wire 1013 between two adjacent vias 1014 is too small to be broken, and therefore, the pitch between two adjacent vias 1014 needs to be not smaller than the width of the wire 1013.
In addition, as the pitch between two adjacent through holes 1014 is reduced, the larger the area of the lead 1013 occupied by the through holes 1014, that means, the smaller the overlapping area of the lead 1013 and the lower plate common electrode 1011 becomes; when the pitch between two adjacent through holes 1014 is equal to the width of the wire 1013, the area occupied by the through holes 1014 on the wire 1013 is maximized, and thus the overlapping area of the wire 1013 and the lower plate common electrode 1011 is minimized. Therefore, when the pitch between two adjacent through holes 1014 is equal to the width of the wire 1013, the overlapping area of the wire 1013 and the lower plate common electrode 1011 is minimized.
Wherein the cross section of the portion of the through hole 1014 far from the lower plate common electrode 1011 and the cross section of the portion of the through hole 1014 near the lower plate common electrode 1011 are both rectangular.
Wherein the cross section of the portion of the through hole 1014 distant from the lower plate common electrode 1011 and the cross section of the portion of the through hole 1014 close to the lower plate common electrode 1011 are set to be rectangular. Of course, the particular shape of the cross-section of the through-hole 1014 may be set as appropriate for the particular situation.
Specifically, referring to fig. 2, fig. 2 is a second structural schematic diagram of the array substrate according to the embodiment of the present disclosure, as shown in fig. 1, an array substrate 101 according to the embodiment of the present disclosure includes a lower plate common electrode 1011 and a conducting wire 1013 disposed on the lower plate common electrode 1011, a projection of the conducting wire 1013 on the lower plate common electrode 1011 partially overlaps with the lower plate common electrode 1011, and the conducting wire 1013 has a plurality of through holes 1014, and the through holes 1014 penetrate through the conducting wire 1013.
Wherein the through hole 1014 penetrates through the wire 1013, and the through hole 1014 penetrating through the wire 1013 is provided on the wire 1013, so that the overlapping area of the wire 1013 and the lower plate common electrode 1011 can be reduced; since the lead wire 1013 is a scan line, reducing the overlapping area between the lead wire 1013 and the lower plate common electrode 1011 can reduce the overlapping area between the scan line and the lower plate common electrode 1011, thereby reducing the parasitic capacitance between the scan line and the lower plate common electrode 1011, improving the signal stability of the lower plate common electrode 1011, and further maintaining the signal stability of the pixels inside the panel.
In one embodiment, the cross section of the portion of the through hole 1014 away from the lower plate common electrode 1011 and the cross section of the portion of the through hole 1014 adjacent to the lower plate common electrode 1011 are both circular.
Here, it is understood that, providing the cross section of the portion of the through hole 1014 distant from the lower plate common electrode 1011 and the cross section of the portion of the through hole 1014 near the lower plate common electrode 1011 as circles facilitates the formation of the through hole 1014 by an etching process. Of course, the particular shape of the cross-section of the through-hole 1014 may be set as appropriate for the particular situation.
Specifically, referring to fig. 3, fig. 3 is a schematic view of a first structure of a display panel according to an embodiment of the present disclosure, and as shown in fig. 3, a display panel 10 according to an embodiment of the present disclosure includes an array substrate 101, a color filter substrate 102, and a liquid crystal layer 103 disposed between the array substrate 101 and the color filter substrate 102, wherein,
the array substrate 101 includes a lower plate common electrode 1011, an insulating layer 1012 and a conducting wire 1013, wherein the insulating layer 1012 is disposed on the lower plate common electrode 1011, the conducting wire 1013 is disposed on a side of the insulating layer 1012 away from the lower plate common electrode 1011, a projection of the conducting wire 1013 on the lower plate common electrode 1011 partially overlaps the lower plate common electrode 1011, and a plurality of through holes 1014 are opened on the conducting wire 1013, and the through holes 1014 penetrate through the conducting wire 1013.
It is understood that the through hole 1014 penetrates through the wire 1013, so the depth of the through hole 1014 is equal to the thickness of the wire 1013, and the through hole 1014 penetrating through the wire 1013 is provided on the wire 1013, so that the overlapping area of the wire 1013 and the lower plate common electrode 1011 can be reduced, and the wire 1013 is the scan line, so that the overlapping area of the scan line and the lower plate common electrode 1011 can be reduced, so as to reduce the parasitic capacitance between the scan line and the lower plate common electrode 1011, so that the stability of the signal of the lower plate common electrode 1011 can be improved, and the stability of the pixel signal inside the panel can be further maintained.
It can be understood that, since the wire 1013 is formed after the insulating layer 1012 and the lower plate common electrode 1011, the through hole 1014 is formed in the wire 1013, which does not affect the formation of the insulating layer 1012 and the lower plate common electrode 1011, and the insulating layer 1012 and the lower plate common electrode 1011 can ensure the smooth and flat surface thereof, so that the insulating layer 1012 does not generate a film breaking phenomenon under high temperature and high humidity or other conditions, and certainly, the insulating layer 1012 does not cause the risk of short circuit between the lower plate common electrode 1011 and the scan line.
In one embodiment, the diameter of the smallest circumscribed circle of the cross-section of the via 1014 gradually decreases along the direction from the side of the wire 1013 away from the insulating layer 1012 to the side of the wire 1013 near the insulating layer 1012.
It is understood that the via 1014 is formed by etching, and the via 1014 is etched by etching from the side of the wire 1013 away from the insulating layer 1012 to the side of the wire 1013 close to the insulating layer 1012 to form the via 1014. It can be seen that the time that the wire 1013 is etched from the side of the wire 1013 away from the insulating layer 1012 to the side of the wire 1013 close to the insulating layer 1012 becomes shorter and shorter, and thus the diameter of the smallest circumscribed circle of the cross-section of the finally formed via 1014 gradually decreases along the direction from the side of the wire 1013 away from the insulating layer 1012 to the side of the wire 1013 close to the insulating layer 1012.
Wherein, in one embodiment, the shape of the through-hole 1014 comprises an inverted trapezoid.
It is to be understood that the shape of the via 1014 is not limited to the inverted trapezoid, as long as the aperture of the via 1014 gradually decreases along the direction from the side of the wire 1013 away from the insulating layer 1012 to the side of the wire 1013 close to the insulating layer 1012.
Specifically, referring to fig. 4, fig. 4 is a second schematic structural diagram of the display panel provided in the embodiment of the present application, and as shown in fig. 4, the display panel 10 provided in the embodiment of the present application includes an array substrate 101, a color filter substrate 102, and a liquid crystal layer 103 disposed between the array substrate 101 and the color filter substrate 102, wherein,
the array substrate 101 includes a lower plate common electrode 1011, an insulating layer 1012 and a conducting wire 1013, wherein the insulating layer 1012 is disposed on the lower plate common electrode 1011, the conducting wire 1013 is disposed on a side of the insulating layer 1012 away from the lower plate common electrode 1011, a projection of the conducting wire 1013 on the lower plate common electrode 1011 partially overlaps the lower plate common electrode 1011, and a plurality of through holes 1014 are opened on the conducting wire 1013, and the through holes 1014 penetrate through the conducting wire 1013.
Wherein the diameter of the smallest circumscribed circle of the cross-section of the portion of the via 1014 away from the insulating layer 1012 has a length equal to the width of the wire 1013 in one embodiment.
It can be understood that, since the wire 1013 is a scan line, it is necessary to reduce the overlapping area between the scan line and the lower plate common electrode 1011 as much as possible to reduce the overlapping area between the wire 1013 and the lower plate common electrode 1011, and it is necessary to increase the cross-sectional area of the through hole 1014 to reduce the overlapping area between the wire 1013 and the lower plate common electrode 1011, and therefore, on the basis of the requirement that the wire 1013 is not broken, it is necessary to etch more wires 1013, one of which can be etched in the width direction of the wire 1013 and the other of which can be etched in the length direction of the wire 1013. However, the etching in the width direction of the wire 1013 does not affect the fracture of the wire 1013, so that, in the width direction of the wire 1013, one end of the wire 1013 away from the insulating layer 1012 is completely etched away, and the length of the diameter of the smallest circumscribed circle of the cross section of the portion of the via 1014 away from the insulating layer 1012 is equal to the width of the wire 1013.
Specifically, referring to fig. 5, fig. 5 is a schematic view of a third structure of the display panel according to the embodiment of the present disclosure, as shown in fig. 5, a display panel 10 according to the embodiment of the present disclosure includes an array substrate 101, a color filter substrate 102, and a liquid crystal layer 103 disposed between the array substrate 101 and the color filter substrate 102, wherein,
the array substrate 101 includes a lower plate common electrode 1011, an insulating layer 1012 and a conducting wire 1013, wherein the insulating layer 1012 is disposed on the lower plate common electrode 1011, the conducting wire 1013 is disposed on a side of the insulating layer 1012 away from the lower plate common electrode 1011, a projection of the conducting wire 1013 on the lower plate common electrode 1011 partially overlaps the lower plate common electrode 1011, and a plurality of through holes 1014 are opened on the conducting wire 1013, and the through holes 1014 penetrate through the conducting wire 1013.
In addition, the display panel 10 further includes a GOA circuit 104, and the GOA circuit 104 is connected to the lead 1013 through a hole 105.
As can be understood, the GOA circuit signal in the GOA circuit 104 is transmitted to the conducting wire 1013 through the hole 105, and is transferred to the inside of the display panel 10 through the conducting wire 1013.
In the display panel provided by the embodiment of the present application, the conducting wire is a scan line, and the through hole is formed in the scan line, so that an overlapping area between the scan line and the lower plate common electrode can be reduced, so that a parasitic capacitance generated between the scan line and the lower plate common electrode is reduced, stability of a signal of the lower plate common electrode is improved, and stability of a pixel signal inside the panel is further maintained.
Specifically, referring to fig. 6, fig. 6 is a schematic flow chart of a manufacturing method of a display panel provided in the embodiment of the present application, and as shown in fig. 6, the manufacturing method of the display panel provided in the embodiment of the present application includes the following steps:
301. forming an array substrate;
specifically, referring to fig. 7, fig. 7 is a sub-flow diagram of a manufacturing method of a display panel according to an embodiment of the present application, and as shown in fig. 7, step 301 includes:
3011. forming a lower plate common electrode on the substrate;
3012. forming an insulating layer on the lower plate common electrode;
3013. forming a conductive line on the insulating layer, a projection of the conductive line on the lower plate common electrode partially overlapping the lower plate common electrode;
as can be understood, the conductive lines are scanning lines, and the scanning lines are mainly used for transmitting the medium GOA driving signals of the GOA circuits to the inside of the display panel through the scanning lines.
3014. And a plurality of through holes are formed in the conducting wire and penetrate through the conducting wire.
As can be understood, the through hole penetrates through the lead, and the through hole penetrating through the lead is arranged on the lead, so that the overlapping area of the lead and the lower plate common electrode can be reduced; since the conducting wire is the scanning wire, the overlapping area of the conducting wire and the lower plate common electrode is reduced, and the overlapping area of the scanning wire and the lower plate common electrode can be reduced, so that the parasitic capacitance between the scanning wire and the lower plate common electrode can be reduced, the stability of the lower plate common electrode signal can be improved, and the stability of the pixel signal in the panel can be further maintained.
In one embodiment, the diameter of the smallest circumscribed circle of the cross section of the through hole gradually decreases along the direction from the side of the wire far away from the insulating layer to the side of the wire close to the insulating layer.
Wherein, in one embodiment, a cross section of a portion of the through hole away from the lower plate common electrode and a cross section of a portion of the through hole close to the lower plate common electrode are both rectangular.
It is to be understood that, among others, it is to be understood that forming the through-hole through an etching process may be facilitated by providing a cross-section of a portion of the through-hole away from the common electrode of the lower plate and a cross-section of a portion of the through-hole close to the common electrode of the lower plate to be rectangular. Of course, the specific shape of the cross-section of the through-hole can be set according to specific circumstances.
302. Providing an array substrate, a color film substrate and a liquid crystal material;
303. and oppositely attaching the array substrate and the color film substrate, and dripping the liquid crystal material between the array substrate and the color film substrate to obtain a liquid crystal box.
In the method for manufacturing a display panel according to the above-mentioned embodiments of the present application, the conductive line is a scan line, and the through hole is formed in the scan line, so that an overlapping area between the scan line and the lower plate common electrode can be reduced, so that a parasitic capacitance generated between the scan line and the lower plate common electrode is reduced, stability of the lower plate common electrode signal is improved, and stability of a pixel signal inside the panel is further maintained.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The display panel and the manufacturing method thereof provided by the embodiment of the present application are described in detail above, and a specific example is applied in the description to explain the principle and the implementation manner of the present application, and the description of the embodiment is only used to help understanding the technical scheme and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
1. The display panel is characterized by comprising an array substrate, a color film substrate and a liquid crystal layer arranged between the array substrate and the color film substrate, wherein the array substrate comprises:
a lower plate common electrode;
an insulating layer disposed on the lower plate common electrode;
the wire is arranged on the surface, far away from the lower plate common electrode, of the insulating layer, the projection of the lower plate common electrode is partially overlapped with the lower plate common electrode, a plurality of through holes are formed in the wire, and the through holes penetrate through the wire.
2. The display panel according to claim 1, wherein a diameter of a smallest circumscribed circle of a cross-section of the through-hole is gradually reduced in a direction from a side of the wire away from the insulating layer to a side of the wire close to the insulating layer.
3. The display panel according to claim 2, wherein a pitch between two adjacent through holes is not less than a width of the conductive line.
4. The display panel of claim 3, wherein a projection of the conductive line on the lower plate common electrode overlaps the lower plate common electrode in an area that becomes smaller as a pitch between two adjacent through holes becomes smaller.
5. The display panel according to claim 2, wherein a length of a diameter of a smallest circumscribed circle of a cross section of a portion of the via hole away from the insulating layer is equal to a width of the wire.
6. The display panel of claim 2, wherein a cross-section of a portion of the through-hole distal from the lower plate common electrode and a cross-section of a portion of the through-hole proximal to the lower plate common electrode are each rectangular.
7. The display panel according to claim 1, wherein the display panel further comprises a GOA circuit, and the GOA circuit is connected to the wire passing hole.
8. A manufacturing method of a display panel is characterized by comprising the following steps:
providing an array substrate, a color film substrate and a liquid crystal material;
attaching the array substrate and the color film substrate in an opposite manner, and dripping the liquid crystal material between the array substrate and the color film substrate to obtain a liquid crystal box;
before the step of providing the array substrate, the color film substrate and the liquid crystal material, the manufacturing method further includes:
forming an array substrate;
the step of forming the array substrate includes:
forming a lower plate common electrode on the substrate;
forming an insulating layer on the lower plate common electrode;
forming a conductive line on the insulating layer, a projection of the conductive line on the lower plate common electrode partially overlapping the lower plate common electrode;
and a plurality of through holes are formed in the conducting wire and penetrate through the conducting wire.
9. The method for manufacturing a display panel according to claim 8, wherein a diameter of a minimum circumscribed circle of a cross section of the through hole is gradually reduced in a direction from a side of the conductive line away from the insulating layer to a side of the conductive line close to the insulating layer.
10. The method of manufacturing a display panel according to claim 9, wherein a cross section of a portion of the through hole that is distant from the lower plate common electrode and a cross section of a portion of the through hole that is close to the lower plate common electrode are each rectangular.
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Application publication date: 20210219 |