CN112366190A - High-voltage semiconductor device terminal with low sensitivity to surface charges - Google Patents

High-voltage semiconductor device terminal with low sensitivity to surface charges Download PDF

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Publication number
CN112366190A
CN112366190A CN202011247049.9A CN202011247049A CN112366190A CN 112366190 A CN112366190 A CN 112366190A CN 202011247049 A CN202011247049 A CN 202011247049A CN 112366190 A CN112366190 A CN 112366190A
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China
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wall
semiconductor device
groove
fixedly connected
hole
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CN202011247049.9A
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Chinese (zh)
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CN112366190B (en
Inventor
李伟
何文牧
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Hangzhou Sc Saibo Electronics Co ltd
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Hangzhou Sc Saibo Electronics Co ltd
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Priority to CN202011247049.9A priority Critical patent/CN112366190B/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • H01L23/3672Foil-like cooling fins or heat sinks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/32Holders for supporting the complete device in operation, i.e. detachable fixtures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Materials Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The invention discloses a high-voltage semiconductor device terminal with low sensitivity to surface charges, which comprises a semiconductor device body, a shell, a through groove, insections, a metal sheet, a radiating fin, a first accommodating groove, a limiting block, a spring, a clamping block, a third accommodating groove, a second binding post, a clamping groove, pins, an elastic sheet, a third through hole, screws, threaded holes and a cushion block, compared with the traditional high-voltage semiconductor device terminal, the high-voltage semiconductor device terminal is provided with the radiating fin which can radiate the heat of the semiconductor device terminal and prevent the overheating damage, the invention is provided with a replaceable base which can be replaced after the pins are broken, is environment-friendly and economical, can also rotate to separately detect the semiconductor device terminal and the pins and is convenient to check circuit faults, and has an electrostatic shielding function, can shield an external electric field and an electric field generated by the semiconductor device terminal, the electric field interference between the elements is reduced, and the electrostatic breakdown is prevented.

Description

High-voltage semiconductor device terminal with low sensitivity to surface charges
Technical Field
The invention relates to the technical field of semiconductor device terminals, in particular to a high-voltage semiconductor device terminal with low sensitivity to surface charges.
Background
The semiconductor device is an electronic device with the conductivity between a good conductor and an insulator, and the special electrical characteristics of a semiconductor material are utilized to complete specific functions, the electronic device can be used for generating, controlling, receiving, converting, amplifying signals and carrying out energy conversion, the conventional semiconductor device terminal lacks a heat dissipation structure, the service life of the semiconductor device terminal can be shortened, the conventional semiconductor device terminal pin is fixed with a body, once the pin is broken, the whole semiconductor device terminal can become a waste product, and the waste can be caused, and the conventional semiconductor device terminal lacks an electrostatic shielding device, so that external electric field interference and electrostatic breakdown can be easily caused.
Disclosure of Invention
It is an object of the present invention to provide a high voltage semiconductor device terminal with low sensitivity to surface charges to solve the problems set forth in the background art described above.
In order to solve the technical problems, the invention provides the following technical scheme: a high-voltage semiconductor device terminal with low sensitivity to surface charges comprises a semiconductor device body, a shell, a through groove, insections, a metal sheet, a radiating fin, a first through hole, a first stop block, a sliding groove, a connecting shaft, a base, a second through hole, a first accommodating groove, a second stop block, a second accommodating groove, a first binding post, a limiting groove, a limiting block, a spring, a clamping block, a third accommodating groove, a second binding post, a clamping groove, a pin, an elastic sheet, a third through hole, a screw, a threaded hole, a cushion block, N-type silicon, P-type silicon and a silicon dioxide protective layer, wherein the outer wall of the bottom end of the semiconductor device body is fixedly connected with the connecting shaft, the base is sleeved on the outer wall of one side of the connecting shaft, the second through hole is formed in the outer wall of the top end of the base, the connecting shaft is sleeved on the inner wall, a second stop block is sleeved on the inner wall of one side of the first accommodating groove, a third through hole is formed in the outer wall of the bottom end of the second stop block, a screw is sleeved on the inner wall of one side of the third through hole, a threaded hole is formed in the outer wall of the bottom end of the connecting shaft, the screw is in threaded connection with the inner wall of one side of the threaded hole, second accommodating grooves are symmetrically formed in the outer wall of the top end of the base, a first binding post is fixedly connected to the inner wall of one side of the second accommodating groove, a limiting groove is formed in the outer wall of the top end of the first binding post, a limiting block is slidably connected to the inner wall of one side of the limiting groove, a spring is fixedly connected to the outer wall of the bottom end of the limiting block, a clamping block is fixedly connected to the outer wall of the top end of the spring, and third, fixedly connected with second terminal on one side inner wall of third holding tank, the draw-in groove has been seted up on the bottom outer wall of second terminal, and the fixture block is connected on one side inner wall of draw-in groove.
According to the technical scheme, the outer shell is sleeved on the outer wall of one side of the semiconductor device body, the sliding blocks are symmetrically fixed on the inner walls of the two sides of the outer shell, the sliding grooves are symmetrically formed in the outer walls of the two sides of the semiconductor device body, and the sliding blocks are connected to the inner wall of one side of the sliding grooves in a sliding mode.
According to the technical scheme, the outer walls of the two sides of the shell are symmetrically provided with insections.
According to the technical scheme, the metal sheet is fixedly connected to the outer wall of the top end of the semiconductor device body, the radiating fin is fixedly connected to the outer wall of the top end of the metal sheet, the through groove is formed in the outer wall of the top end of the shell, the radiating fin is sleeved on the inner wall of one side of the through groove, and the first stop block is fixedly connected to the outer wall of the top end of the radiating fin.
According to the technical scheme, the outer wall of one side of the radiating fin is provided with the first through hole.
According to the technical scheme, the pin is fixedly connected to the outer wall of the bottom end of the first wiring terminal, the cushion block is sleeved on the outer wall of one side of the pin, and the cushion block is fixedly connected to the outer wall of the bottom end of the base.
According to the technical scheme, the outer wall of the base is fixedly provided with the elastic pieces which are attached to and connected with the inner wall of the shell.
According to the technical scheme, fixedly connected with N type silicon on one side inner wall of semiconductor device body, and second terminal fixed connection is on one side outer wall of N type silicon, fixedly connected with P type silicon on one side inner wall of N type silicon, fixedly connected with silica protective layer on one side outer wall of P type silicon, and silica protective layer fixed connection is on one side outer wall of N type silicon, it is connected with the contact to inlay on one side inner wall of silica protective layer, and contact fixed connection is on one side outer wall of second terminal.
Compared with the prior art, the invention has the following beneficial effects: compared with the existing high-voltage semiconductor device terminal, the high-voltage semiconductor device terminal is provided with the radiating fin which can radiate heat of the semiconductor device terminal and prevent overheating damage, the high-voltage semiconductor device terminal is provided with the replaceable base which can be replaced after the pins are broken, the high-voltage semiconductor device terminal is environment-friendly and economical, the base can also rotate to separately detect the semiconductor device terminal and the pins and conveniently check circuit faults, and the high-voltage semiconductor device terminal is provided with the electrostatic shielding function which can shield an external electric field and an electric field generated by the semiconductor device terminal, reduce electric field interference among elements and prevent electrostatic breakdown.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic view of the overall side cut-away construction of the present invention;
FIG. 2 is an enlarged view of the structure of area A in FIG. 1;
FIG. 3 is a schematic overall front cut-away construction of the present invention;
FIG. 4 is an enlarged view of the structure of the area B in FIG. 3;
FIG. 5 is an enlarged view of the structure of the area C in FIG. 3;
FIG. 6 is a perspective view of the heat sink of the present invention;
FIG. 7 is a schematic perspective view of the housing of the present invention;
fig. 8 is a schematic perspective view of a semiconductor device body of the present invention;
in the figure: 1. a semiconductor device body; 2. a housing; 3. a through groove; 4. insection; 5. a metal sheet; 6. a heat sink; 7. a first through hole; 8. a first stopper; 9. a slider; 10. a chute; 11. a connecting shaft; 12. a base; 13. a second through hole; 14. a first accommodating groove; 15. a second stopper; 16. a second accommodating groove; 17. a first terminal post; 18. a limiting groove; 19. a limiting block; 20. a spring; 21. a clamping block; 22. a third accommodating groove; 23. a second terminal; 24. a card slot; 25. a pin; 26. a spring plate; 27. a third through hole; 28. a screw; 29. a threaded hole; 30. cushion blocks; 31. n-type silicon; 32. p-type silicon; 33. and a silicon dioxide protective layer.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1-8, the present invention provides a technical solution: a high-voltage semiconductor device terminal with low sensitivity to surface charges comprises a semiconductor device body 1, a shell 2, a through groove 3, insections 4, a metal sheet 5, a radiating fin 6, a first through hole 7, a first stop block 8, a slide block 9, a slide groove 10, a connecting shaft 11, a base 12, a second through hole 13, a first accommodating groove 14, a second stop block 15, a second accommodating groove 16, a first wiring terminal 17, a limiting groove 18, a limiting block 19, a spring 20, a clamping block 21, a third accommodating groove 22, a second wiring terminal 23, a clamping groove 24, a pin 25, an elastic sheet 26, a third through hole 27, a screw 28, a threaded hole 29, a cushion block 30, N-type silicon 31, P-type silicon 32 and a silicon dioxide protective layer 33, wherein the connecting shaft 11 is fixedly connected to the outer wall of the bottom end of the semiconductor device body 1, the base 12 is sleeved on the outer wall of one side of the connecting shaft 11, the, the connecting shaft 11 is sleeved on the inner wall of one side of the second through hole 13, the inner wall of one side of the second through hole 13 is provided with a first accommodating groove 14, the inner wall of one side of the first accommodating groove 14 is sleeved with a second stopper 15, the outer wall of the bottom end of the second stopper 15 is provided with a third through hole 27, the inner wall of one side of the third through hole 27 is sleeved with a screw 28, the outer wall of the bottom end of the connecting shaft 11 is provided with a threaded hole 29, the screw 28 is in threaded connection with the inner wall of one side of the threaded hole 29, the outer wall of the top end of the base 12 is symmetrically provided with second accommodating grooves 16, the inner wall of one side of the second accommodating grooves 16 is fixedly connected with a first binding post 17, the outer wall of the top end of the first binding post 17 is provided with a limiting groove 18, the inner wall of one side of the limiting groove 18 is slidably connected with a limiting block, a clamping block 21 is fixedly connected to the outer wall of the top end of the limiting block 19, third accommodating grooves 22 are symmetrically formed in the outer wall of the bottom end of the semiconductor device body 1, a second wiring terminal 23 is fixedly connected to the inner wall of one side of each third accommodating groove 22, a clamping groove 24 is formed in the outer wall of the bottom end of each second wiring terminal 23, and the clamping block 21 is clamped and connected to the inner wall of one side of the clamping groove 24; the outer shell 2 is sleeved on the outer wall of one side of the semiconductor device body 1, the sliding blocks 9 are symmetrically fixed on the inner walls of two sides of the outer shell 2, the sliding grooves 10 are symmetrically formed in the outer walls of two sides of the semiconductor device body 1, the sliding blocks 9 are connected to the inner wall of one side of the sliding grooves 10 in a sliding mode, the outer shell 2 is used for constructing a shielding body, and the sliding grooves 10 and the sliding blocks 9 can enable the outer shell 2 to slide flexibly; the outer walls of the two sides of the shell 2 are symmetrically provided with insections 4 for skid resistance; the semiconductor device comprises a semiconductor device body 1, a metal sheet 5, a radiating fin 6, a through groove 3 and a shielding body, wherein the metal sheet 5 is fixedly connected to the outer wall of the top end of the semiconductor device body 1, the radiating fin 6 is fixedly connected to the outer wall of the top end of the metal sheet 5, the through groove 3 is formed in the outer wall of the top end of the shell 2, the radiating fin 6 is sleeved on the inner wall of one side of the through groove 3, a first stop block 8 is fixedly connected to the outer wall of the top end of the radiating fin 6, the metal sheet 5 is used; the outer wall of one side of the radiating fin 6 is provided with a first through hole 7, so that the contact area of the radiating fin 6 and air is increased, and the radiating effect is improved; a pin 25 is fixedly connected to the outer wall of the bottom end of the first binding post 17, a cushion block 30 is sleeved on the outer wall of one side of the pin 25, the cushion block 30 is fixedly connected to the outer wall of the bottom end of the base 12, the pin 25 is used for welding installation, and the cushion block 30 is used for heightening the base 12 to prevent heat transfer; the outer wall of the base 12 is distributed and fixed with the elastic sheets 26, the elastic sheets 26 are attached and connected to the inner wall of the shell 2, and the insulated base 12, the conductive elastic sheets 26, the conductive shell 2 and the metal sheets 5 form a closed shell to shield an external electric field; the semiconductor device comprises a semiconductor device body 1, wherein an N-type silicon 31 is fixedly connected to the inner wall of one side of the semiconductor device body 1, a second wiring terminal 23 is fixedly connected to the outer wall of one side of the N-type silicon 31, a P-type silicon 32 is fixedly connected to the inner wall of one side of the N-type silicon 31, a silicon dioxide protective layer 33 is fixedly connected to the outer wall of one side of the P-type silicon 32, the silicon dioxide protective layer 33 is fixedly connected to the outer wall of one side of the N-type silicon 31, a contact is connected to the inner wall of one side of the silicon dioxide protective layer 33 in an embedded mode, the contact is fixedly connected to the outer wall of one side of the second wiring terminal 23, and the;
when the invention is used, the pin 25 can be welded or inserted on the circuit board, if the pin 25 is damaged and broken, and the semiconductor device body 1 is still intact, the pin 25 can be taken down from the circuit board, then the screw 28 is unscrewed, the semiconductor device body 1 is taken down, a new base 12 is replaced, the base 12 is sleeved on the connecting shaft 11 through the second through hole 13, then the second stop block 15 is fixed on the connecting shaft 11 through the screw 28, the use can be continued, when the circuit at the position of the semiconductor device body 1 is failed, the first stop block 8 can be pressed by a forefinger, the insection 4 on the shell 2 is pinched by a thumb and a middle finger, then the shell 2 slides upwards along the radiating fin 6 in the through groove 3, at the moment, the slide block 9 slides in the sliding groove 10, the shell 2 is separated from the base 12, at the moment, the shell 2 can be rotated, the fixture block 21 is separated from the clamping groove 24, and the first binding post, at this moment, the detection probe can be abutted on the fixture block 21, whether the detection pin 25 is in a rosin joint or not, the detection probe is abutted in the clamping groove 24, whether the semiconductor device body 1 is damaged or not is detected, wherein the base 12, the shell 2, the metal sheet 5 and the elastic sheet 26 can form a shielding shell body for preventing electrostatic breakdown and external electric field interference, the radiating fin 6 provided with the first through hole 7 can accelerate the heat dissipation of the semiconductor device body 1 and prevent overheating damage, the second accommodating groove 16 is used for installing the first binding post 17, the third accommodating groove 22 is used for installing the second binding post 23, the first accommodating groove 14 is used for accommodating the second binding post 15, the limiting block 19 in the limiting groove 18 is used for limiting the fixture block 21, the spring 20 can enable the fixture block 21 to be tightly attached to the clamping groove 24, the third through hole 27 and the threaded hole 29 are used for installing the screw 28, and.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art will understand that various changes, modifications and substitutions can be made without departing from the spirit and scope of the invention as defined by the appended claims. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (8)

1. A high-voltage semiconductor device terminal with low sensitivity to surface charges comprises a semiconductor device body (1), a shell (2), a through groove (3), insections (4), a metal sheet (5), a radiating fin (6), a first through hole (7), a first stop block (8), a sliding block (9), a sliding groove (10), a connecting shaft (11), a base (12), a second through hole (13), a first accommodating groove (14), a second stop block (15), a second accommodating groove (16), a first binding post (17), a limiting groove (18), a limiting block (19), a spring (20), a clamping block (21), a third accommodating groove (22), a second binding post (23), a clamping groove (24), pins (25), an elastic sheet (26), a third through hole (27), a screw (28), a threaded hole (29), a cushion block (30), N-type silicon (31), P-type silicon (32) and a silicon dioxide protective layer (33), the method is characterized in that: a connecting shaft (11) is fixedly connected to the outer wall of the bottom end of the semiconductor device body (1), a base (12) is sleeved on the outer wall of one side of the connecting shaft (11), a second through hole (13) is formed in the outer wall of the top end of the base (12), the connecting shaft (11) is sleeved on the inner wall of one side of the second through hole (13), a first accommodating groove (14) is formed in the inner wall of one side of the second through hole (13), a second stop block (15) is sleeved on the inner wall of one side of the first accommodating groove (14), a third through hole (27) is formed in the outer wall of the bottom end of the second stop block (15), a screw (28) is sleeved on the inner wall of one side of the third through hole (27), a threaded hole (29) is formed in the outer wall of the bottom end of the connecting shaft (11), the screw (28) is in threaded connection with the inner wall of one side of the threaded hole (29), and second accommodating, a first binding post (17) is fixedly connected on the inner wall of one side of the second accommodating groove (16), a limiting groove (18) is formed in the outer wall of the top end of the first binding post (17), a limiting block (19) is connected to the inner wall of one side of the limiting groove (18) in a sliding manner, a spring (20) is fixedly connected to the outer wall of the bottom end of the limiting block (19), and one end of the spring (20) is fixedly connected on the inner wall of the bottom end of the limit groove (18), a clamping block (21) is fixedly connected on the outer wall of the top end of the limiting block (19), third accommodating grooves (22) are symmetrically formed in the outer wall of the bottom end of the semiconductor device body (1), a second binding post (23) is fixedly connected on the inner wall of one side of the third accommodating groove (22), a clamping groove (24) is formed in the outer wall of the bottom end of the second binding post (23), and the clamping block (21) is clamped and connected to the inner wall of one side of the clamping groove (24).
2. A high voltage semiconductor device termination with low sensitivity to surface charge according to claim 1, characterized in that: the semiconductor device is characterized in that a shell (2) is sleeved on the outer wall of one side of the semiconductor device body (1), sliding blocks (9) are symmetrically fixed on the inner walls of two sides of the shell (2), sliding grooves (10) are symmetrically formed in the outer walls of two sides of the semiconductor device body (1), and the sliding blocks (9) are connected to the inner wall of one side of the sliding grooves (10) in a sliding mode.
3. A high voltage semiconductor device termination with low sensitivity to surface charge according to claim 1, characterized in that: the outer walls of the two sides of the shell (2) are symmetrically provided with insections (4).
4. A high voltage semiconductor device termination with low sensitivity to surface charge according to claim 1, characterized in that: fixedly connected with sheetmetal (5) on the top outer wall of semiconductor device body (1), fixedly connected with fin (6) on the top outer wall of sheetmetal (5), logical groove (3) have been seted up on the top outer wall of shell (2), and fin (6) cup joint on the one side inner wall that leads to groove (3), first dog (8) of fixedly connected with on the top outer wall of fin (6).
5. A high voltage semiconductor device termination with low sensitivity to surface charge according to claim 1, characterized in that: and a first through hole (7) is formed in the outer wall of one side of the radiating fin (6).
6. A high voltage semiconductor device termination with low sensitivity to surface charge according to claim 1, characterized in that: fixedly connected with pin (25) on the bottom outer wall of first terminal (17), cup joint cushion (30) on the one side outer wall of pin (25), and cushion (30) fixed connection is on the bottom outer wall of base (12).
7. A high voltage semiconductor device termination with low sensitivity to surface charge according to claim 1, characterized in that: the outer wall of the base (12) is fixedly provided with elastic pieces (26), and the elastic pieces (26) are attached to and connected with the inner wall of the shell (2).
8. A high voltage semiconductor device termination with low sensitivity to surface charge according to claim 1, characterized in that: fixedly connected with N type silicon (31) on one side inner wall of semiconductor device body (1), and second terminal (23) fixed connection is on one side outer wall of N type silicon (31), fixedly connected with P type silicon (32) on one side inner wall of N type silicon (31), fixedly connected with silica protective layer (33) on one side outer wall of P type silicon (32), and silica protective layer (33) fixed connection is on one side outer wall of N type silicon (31), inlay on one side inner wall of silica protective layer (33) and be connected with the contact, and contact fixed connection is on one side outer wall of second terminal (23).
CN202011247049.9A 2020-11-10 2020-11-10 High-voltage semiconductor device terminal with low sensitivity to surface charge Active CN112366190B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117727708A (en) * 2023-12-15 2024-03-19 宁波君芯半导体有限公司 Silicon carbide power device and processing method thereof

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Publication number Priority date Publication date Assignee Title
JPH09139448A (en) * 1995-11-13 1997-05-27 Fujitsu Denso Ltd Semiconductor fitting, its mounting method and semiconductor device using it
CN109041422A (en) * 2018-09-10 2018-12-18 广州高雅电器有限公司 A kind of Spliced type LED circuit board
CN208420782U (en) * 2018-06-13 2019-01-22 伟华科技(天津)有限公司 A kind of semiconductor-type gas sensor
CN211014574U (en) * 2019-10-16 2020-07-14 安徽扬能新能源科技有限公司 Car as a house battery charge time detects accounting device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09139448A (en) * 1995-11-13 1997-05-27 Fujitsu Denso Ltd Semiconductor fitting, its mounting method and semiconductor device using it
CN208420782U (en) * 2018-06-13 2019-01-22 伟华科技(天津)有限公司 A kind of semiconductor-type gas sensor
CN109041422A (en) * 2018-09-10 2018-12-18 广州高雅电器有限公司 A kind of Spliced type LED circuit board
CN211014574U (en) * 2019-10-16 2020-07-14 安徽扬能新能源科技有限公司 Car as a house battery charge time detects accounting device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117727708A (en) * 2023-12-15 2024-03-19 宁波君芯半导体有限公司 Silicon carbide power device and processing method thereof
CN117727708B (en) * 2023-12-15 2024-05-28 宁波君芯半导体有限公司 Silicon carbide power device and processing method thereof

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