CN112363759A - Register configuration method and device, CPU chip and electronic equipment - Google Patents
Register configuration method and device, CPU chip and electronic equipment Download PDFInfo
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
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- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
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- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
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Abstract
The embodiment of the invention discloses a register configuration method and device, a CPU chip and electronic equipment. The register configuration method comprises the following steps: pre-configuring a main configuration register and a shadow register to have the same system address; the master end interface receives a configuration request of a master end and sends the configuration request for configuring the master configuration register to at least one slave end interface in a broadcast mode; the slave interface receives the configuration request and determines whether the master configuration register or the shadow register is configured by the slave according to the system address in the configuration request. In the invention, the master end only needs to broadcast the configuration of the master configuration register to all the system bus slave ends without knowing the information of the shadow register in the whole design, so the design of the system bus master end is relatively simple and is easy to physically realize.
Description
Technical Field
The present invention relates to the field of integrated circuit design, and in particular, to a register configuration method and apparatus, a processor chip, and an electronic device.
Background
With the development of integrated circuits, the integration level of chips and the complexity of circuits are increasing, and more functional modules are integrated into a single chip. Especially for large-scale SOC chip design, a large number of functional modules are integrated in a chip, and functions which can be realized only by a chip set before can be realized by one chip. However, the area of a single chip is increasing, and higher requirements are put on physical design.
Among the large number of functional blocks of the chip, many functional blocks have functional dependencies and require the same configuration information. However, due to the limitation of physical design, these functional modules are likely not adjacent to each other in physical implementation, and may even be physically far away from each other, so that it is not desirable to share the same configuration information among the functional modules by using the conventional physical connection method.
The scheme of the shadow register is developed, namely, the configuration register (hereinafter referred to as a main configuration register) is added into one functional module, the shadow register is added into other functional modules needing the same configuration information, and the shadow register is synchronously modified when the main configuration register is modified each time, so that the configuration information can be ensured to be consistent among a plurality of functional modules. However, when the shadow register is implemented, the main configuration register and the shadow register are configured one by one mainly through software. That is, software is required to keep track of all shadow register information. Most application software may not have knowledge of all shadow registers for reasons that may involve the chip architecture.
Therefore, current shadow register implementations have certain limitations.
Disclosure of Invention
In view of this, embodiments of the present invention provide a register configuration method and apparatus, a CPU chip, and an electronic device.
To achieve the above object, an aspect of the embodiments of the present invention provides a register configuration apparatus, including:
the configuration module is used for pre-configuring the same system address of the main configuration register and the shadow register;
the master end interface module is used for receiving a configuration request of a master end and sending the configuration request for configuring the master configuration register to at least one slave end interface module in a broadcast mode;
and the slave end interface module is used for receiving the configuration request and determining whether the master configuration register or the shadow register is configured by the slave end according to the system address in the configuration request.
Furthermore, the master interface module is further configured to receive a configuration request from the master, and send the configuration request for configuring the general configuration register to a slave interface module in a unicast manner;
the slave-end interface module is further configured to receive the configuration request and deliver the configuration request to the slave end to configure the common configuration register.
Further, the master interface module sends the configuration request to the slave interface module through a system bus or an on-chip internet.
Further, the configuration module is further configured to configure the common configuration register and the main configuration register as different system address domain segments;
the master-end interface module and/or the slave-end interface module are specifically configured to, after receiving the configuration request, identify, according to the domain segment to which the system address belongs, that the configuration request is to configure a master configuration register or configure the general configuration register.
Further, the slave-end interface module is specifically configured to:
judging whether the system address belongs to an address field segment of a local register or not according to a local main configuration register/shadow register address translation table;
and when the system address is judged to belong to the address field segment of the local register, the slave end is handed to configure the main configuration register or the shadow register, and a response result of whether the processing is successful is fed back.
Further, the slave interface module is further configured to directly feed back a response result of successful processing when it is determined that the system address does not belong to the address field segment of the local register.
Further, the master interface module is further configured to:
waiting for response results fed back by all the slave interface modules;
and when all the response results are successfully processed, feeding back the success of processing the configuration request to the master terminal.
Another aspect of the embodiments of the present invention further provides a register configuration method, including:
pre-configuring a main configuration register and a shadow register to have the same system address;
a master end interface receives a configuration request of a master end and sends the configuration request of the master configuration register to at least one slave end interface in a broadcast mode;
and the slave-end interface receives the configuration request and determines whether the master configuration register or the shadow register is configured by the slave end according to the system address in the configuration request.
Further, the interface of the main end receives the configuration request of the main end, and sends the configuration request of the system address as a common configuration register to the interface of a slave end in a unicast mode;
and receiving the configuration request from the slave-end interface, and delivering the configuration request to the slave-end to configure the common configuration register.
Further, the master interface sends the configuration request to the slave interface through a system bus or an on-chip internet.
Further, the method further comprises:
pre-configuring the common configuration register and the main configuration register to be different system address field sections;
after a main end interface and/or a slave end interface receives a configuration request, the configuration request is identified to configure a main configuration register or configure the common configuration register according to the domain section of the system address.
Further, the receiving, by the slave interface, the configuration request and determining whether the master configuration register or the shadow register is configured by the slave according to the system address in the configuration request includes:
judging whether the system address belongs to an address field segment of a local register or not according to a local main configuration register/shadow register address translation table;
and when the system address is judged to belong to the address field segment of the local register, the slave end configures the main configuration register or the shadow register and feeds back a response result of whether the processing is successful or not.
Further, the method further comprises:
and when the system address is judged not to belong to the address field section of the local register, directly feeding back a response result of successful processing.
Further, the method further comprises:
the master end interface waits for response results fed back by all the slave ends;
and when all the response results are successfully processed, feeding back the success of processing the configuration request to the master terminal.
Another aspect of the embodiments of the present invention provides a CPU chip, including: at least one processor core, the processor core, to:
receiving a configuration request of a master end through a master end interface, and sending the configuration request for configuring the master configuration register to at least one slave end interface in a broadcasting mode;
receiving the configuration request through a slave interface, and determining whether the master configuration register or the shadow register is configured by a slave according to a system address in the configuration request:
wherein the pre-configured main configuration register and the shadow register have the same system address.
Further, the processor core is further configured to:
receiving a configuration request of a master end through a master end interface, and sending the configuration request for configuring a common configuration register to a slave end interface in a unicast mode;
and receiving the configuration request through a slave-end interface, and delivering the configuration request to a slave-end to configure the common configuration register.
Further, the processor core is further configured to send the configuration request of the master interface to the slave interface through a system bus or an on-chip internet.
Further, the processor core is further configured to, after receiving the configuration request at the master interface and/or the slave interface, identify, according to the domain segment to which the system address belongs, that the configuration request is to configure the master configuration register or configure the general configuration register:
and the common configuration register and the main configuration register are configured in advance to be different system address field sections.
Further, the processor core is specifically configured to determine, through the slave interface, whether the system address belongs to an address field segment of a local register according to a local primary configuration register/shadow register address translation table;
and when the system address is judged to belong to the address field segment of the local register, the slave end configures the main configuration register or the shadow register and feeds back a response result of whether the processing is successful or not.
Further, the processor core is configured to directly feed back a response result of successful processing when the slave interface determines that the system address does not belong to the address field segment of the local register.
Further, the processor core is used for waiting for response results fed back by all the slave terminals through the master terminal interface;
and when all the response results are successfully processed, feeding back the success of processing the configuration request to the master terminal.
Another aspect of an embodiment of the present invention provides an electronic device, including: the device comprises a shell, a processor, a memory, a circuit board and a power circuit, wherein the circuit board is arranged in a space enclosed by the shell, and the processor and the memory are arranged on the circuit board; a power supply circuit for supplying power to each circuit or device of the electronic apparatus; the memory is used for storing executable program codes; the processor executes a program corresponding to the executable program code by reading the executable program code stored in the memory, for executing the aforementioned register configuration method.
In the register configuration method, the register configuration device, the CPU chip, and the electronic apparatus provided in the embodiments of the present invention, the shadow register and the main configuration register thereof use the same system address, that is, as long as a configuration request is sent out with the system address as the main configuration register, both the main configuration register and the corresponding shadow register respond to the configuration request; and the system bus master end only needs to broadcast the configuration of the master configuration register to all the system bus slave ends without knowing the information of the shadow register in the whole design, so the design of the system bus master end is relatively simple and is easy to physically realize. Therefore, the realization of the shadow register in the invention is based on the improvement of the chip architecture, is transparent to the application software, and the software only needs to configure the main configuration register without concerning the relevant information of the main configuration register and the shadow register in the chip. Therefore, the embodiment of the invention can ensure that the change of the hardware architecture does not influence the design of the software.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a register allocation apparatus according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating system address partitioning according to an embodiment of the present invention;
FIG. 3 is a diagram of a host interface module according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a slave interface module in an embodiment of the present invention;
FIG. 5 is a diagram illustrating an address translation table for main configuration registers/shadow registers according to an embodiment of the present invention;
FIG. 6 is a flow chart of a register configuration method provided in an embodiment of the present invention;
FIG. 7 is a block diagram of a register allocation apparatus according to an embodiment of the present invention;
FIG. 8 is a diagram illustrating data flow when the shadow register is configured by the register configuration apparatus in FIG. 7;
FIG. 9 is a data flow diagram illustrating the configuration of a general configuration register by the register configuration apparatus of FIG. 7;
fig. 10 is a schematic structural diagram of a CPU chip according to an embodiment of the present invention;
fig. 11 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The register configuration device and the register configuration method provided by the embodiment of the invention relate to the design of a chip architecture. Specifically, a plurality of functional modules are integrated in the same chip, the functional modules are interconnected through a system bus or an on-chip interconnection network, and the functional modules can be controlled through control registers in the modules. When the chip is initialized or operated, the configuration register of each module can be configured by software or corresponding functional modules through a bus or a network on a chip. Here, one of the functional modules is defined as a master module, the relevant configuration register is defined as a master configuration register, and the configuration register identical to the master configuration register in the master module is defined as a shadow register in the other functional modules. The configuration register without shadow register in the system is defined as the ordinary configuration register. That is, the common configuration register has only one design implementation in the whole system, and has no corresponding shadow register. The main configuration register has only one design implementation in the whole system, but 1 or more corresponding shadow registers. The shadow register is designed and realized by 1 part or more in the whole system, a main configuration register corresponds to the shadow register, and the content and the configuration of the shadow register need to be consistent with those of the main configuration register. The method is suitable for a scene needing to use the shadow register to synchronize the configuration information among a plurality of functional modules in the chip design.
As shown in fig. 1, an embodiment of the present invention provides a register configuration apparatus, which includes a configuration module 11, a master interface module 12, and a slave interface module 13. In the invention, each functional module is mounted to a system bus or an on-chip interconnection network through an independent interface module. And according to the message processing relationship of the functional module, the system is divided into a master end and a slave end. The master interface module 12 is responsible for forwarding a request sent by a function module of the master to a system bus or an on-chip interconnection network. The slave bus interface module is responsible for receiving a request sent by a system bus or an on-chip internet and forwarding the request to the slave functional module. Therefore, when the register configuration is realized, the implementation manner of each block is as follows.
The configuration module 11 is used for pre-configuring that the main configuration register and the shadow register have the same system address;
the master interface module 12 is configured to receive a configuration request from a master, and send the configuration request to the at least one slave interface module 13 in a broadcast manner;
and the slave-side interface module 13 is used for receiving the configuration request and determining whether the master configuration register or the shadow register is configured by the slave side according to the system address in the configuration request.
In the register configuration apparatus provided in the embodiment of the present invention, the shadow register and the main configuration register thereof use the same system address, that is, as long as the configuration request with the system address as the main configuration register is issued, both the main configuration register and the corresponding shadow register respond to the configuration request. And the slave end determines whether to complete the configuration request by sending the configuration request of the master end to the slave end in a broadcasting mode. Therefore, the register configuration device can complete the configuration of all the shadow registers by designing the internal structure of the chip without paying attention to the relevant information of the main configuration register and the shadow registers in the chip, and has the advantages of high efficiency, strong expansibility, low logic resource overhead, friendly physical realization and the like.
Wherein, the system address is divided in the invention. For primary configuration registers with shadow registers, it is necessary to ensure that the shadow registers all use the same system address as their primary configuration registers. And the configuration register without the shadow register is a common configuration register. Thus, when the configuration request is received to configure the main configuration register, the slave end can complete the configuration of the main configuration register or the shadow register according to the system address. Therefore, no matter the increase and decrease of the system bus master end/the system bus slave end can not affect other parts of the system, so that the system has stronger expansibility.
Correspondingly, when configuring the common configuration register, the master interface module 12 sends a configuration request sent by the master for the common configuration register to a slave interface module 13 in a unicast manner; the slave interface module 13 is further configured to receive a configuration request sent by the master for configuring the general configuration register, and deliver the configuration request to the slave functional module for configuring the general configuration register according to the configuration request. In embodiments of the present invention, the general configuration registers have only one design implementation within the overall system. Therefore, after determining the configuration request, the master interface module 12 may directly complete the configuration by the corresponding slave in a unicast manner.
As mentioned above, the master interface module 12 and the slave interface module 13 are interconnected by a system bus or an on-chip interconnection network. Therefore, in order to send the configuration information of the main configuration register and the shadow register to each corresponding functional module, the system bus or the on-chip interconnect network needs to have a broadcast function, that is, the system bus or the on-chip interconnect network can send the configuration information sent from the functional module of one main end to each of the slave functional modules mounted on the system bus or the on-chip interconnect network. The configuration information sent to the main configuration register/the shadow register is transmitted in a broadcast mode in a system bus/on-chip interconnection network, and the configuration information sent to the common configuration register is transmitted in a traditional unicast mode in the system bus/on-chip interconnection network.
Further, in order to facilitate the distinction of the interface modules of the master and the slave to the configuration request, in an optional embodiment of the present invention, in the configuration module 11, all the master configuration registers/shadow registers in the system are addressed individually, and are distinguished from the common configuration registers; therefore, for the general configuration register, it needs to be pre-configured with a different system address field section from the main configuration register. Thus, after the master interface module 12 or the slave interface module 13 receives the configuration request, it identifies whether the configuration request is to configure the master configuration register or configure the normal configuration register according to the domain segment of the system address.
As shown in fig. 2, the system address of the configuration register is divided, and a dedicated address field segment is divided for all the main configuration registers/shadow registers. While the main configuration register/shadow register and the normal configuration register have different address field segments. The register a and the register b are main configuration registers, the register a0 and the register a1 are shadow registers of the register a and have the same system address as the register a, and the register b0 and the register b1 are shadow registers of the register b and have the same system address as the register b. Because the system addresses of the main configuration register and the shadow register are the same, namely, as long as a configuration request with the system address as the main configuration register is sent out, the main configuration register of the slave end or the corresponding shadow register can respond to the configuration request.
It should be noted that, in the foregoing embodiment, the general configuration register and the main configuration register/shadow register are distinguished by an addressing manner, but the two types of registers may also be distinguished by other manners, for example, all address information of the main configuration register/shadow register of the system may be maintained at the main end of the configuration information system bus. Therefore, the distinction between the normal configuration register and the main configuration register/shadow register is only exemplary, and is not intended to limit the scope of the present invention.
As shown in fig. 3 and 4, after receiving the configuration request of the function module at the master, the master interface module 12 determines whether the request configures the master configuration register or the normal configuration register according to the system address field in the configuration request. After determining the type of the configuration request, the configuration request is forwarded to the system bus in a broadcast or unicast manner. Similarly, after receiving the configuration request sent by the system bus, the slave-end interface module 13 determines whether the configuration request configures the master configuration register or the normal configuration register according to the system address field segment, determines the type of the configuration request, and then performs corresponding processing.
Further, after receiving the configuration request for configuring the master configuration register, the slave-end interface module 13 determines whether the system address belongs to the address field of the local register according to the local master configuration register/shadow register address translation table; when the system address belongs to the address field segment of the local register, the slave end is given to configure a main configuration register or a shadow register, and whether the response result of successful processing is fed back or not is fed back; and when the system address does not belong to the address field section of the local register, directly sending a response result of successful processing. After the slave-end functional module configures the main configuration register or the shadow register, a response result of successful processing is fed back, and when the slave-end equipment does not work normally or the master end does not have authority, a response result of failed processing is returned.
The primary configuration register/shadow register address translation table herein may be implemented in a variety of forms including, but not limited to, hardware logic implementations, ROM, configurable registers, SRAM, etc.
It can be known that only the address information of the shadow register used by the subsequent functional module needs to be configured in advance at the system bus slave end interface module 13, so that from the viewpoint of chip design, only the address of the shadow register used by the corresponding slave end functional module needs to be converted, the shadow register used by other functional modules does not need to be concerned, the design complication can be avoided, and the design is easy to physically realize.
Specifically, the slave interface module 13 recognizes that the address of the configuration request belongs to the system address field of the master configuration register/shadow register, and then determines whether the system address belongs to the master configuration register or the shadow register of the slave functional module corresponding to the slave interface module 13 according to a locally maintained shadow register address translation table, and if the system address belongs to the master configuration register or the shadow register of the slave functional module corresponding to the slave interface module, translates the requested system address into the local address corresponding to the master configuration register/shadow register in the slave functional module and forwards the configuration request to the corresponding slave functional module; if the slave functional module does not belong to the main configuration register or the shadow register of the corresponding slave functional module, a response is directly replied to the system bus, and the response state is successful in processing. If the requesting system address does not belong to the primary configuration register/shadow register address field segment, the request is forwarded directly to the corresponding slave functional module. Each slave interface module 13 needs to maintain an address translation table which only records all the main configuration registers/shadow registers in the slave functional module connected to it, the index of the address translation table is the system address of the main configuration register/shadow register, and the content of the address translation table is the local address used by the main configuration register/shadow register in the slave functional module. The shadow register address translation table is shown in figure 5.
Based on the above, the slave interface module 13 in the embodiment of the present invention only needs to maintain the master configuration register/shadow register of the corresponding slave functional module, instead of maintaining all the master configuration registers/shadow registers in the entire system. The content quantity of the local shadow register address translation table is controllable, and the local shadow register address translation table is relatively easy to physically implement. The shadow register address translation table can be configured, can also be realized in a hardware logic solidification form, and can be flexibly designed according to the system requirements. Therefore, in the present invention, only the address information of the shadow register used by the corresponding slave functional module needs to be configured in advance at the system bus slave interface module 13. From the viewpoint of chip design, only the address of the shadow register used by the subsequent functional module needs to be converted, the shadow registers used by other functional modules do not need to be concerned, the design complication can be avoided, and the design is easy to physically realize.
As shown in fig. 6, another aspect of the present invention further provides a register configuration method. The method is based on the register configuration device and specifically comprises the following steps:
step 601, pre-configuring a main configuration register and a shadow register to have the same system address;
wherein in this step, the system address is divided in advance. For primary configuration registers with shadow registers, it is necessary to ensure that the shadow registers all use the same system address as their primary configuration registers.
Step 602, a master interface receives a configuration request of a master, and sends the configuration request for configuring a master configuration register to at least one slave interface in a broadcast manner;
step 603, the slave interface receives the configuration request, and determines whether the master configuration register or the shadow register is configured by the slave according to the system address in the configuration request.
It can be known that, when the configuration request is received to configure the primary configuration register, the slave can complete the configuration of the primary configuration register or the shadow register according to the system address. Therefore, the increase and decrease of the system bus master end/the system bus slave end can be independently carried out, so that the system has stronger expansibility. In addition, the system bus master does not need to know the information of the shadow register in the whole design, and only needs to broadcast the configuration of the master configuration register to all the system bus slaves, so that the design of the system bus master is relatively simple, and the physical implementation is easy.
Wherein the configuration request is sent to the slave interface through a system bus or an on-chip interconnection network.
Further, in some embodiments, the register configuration method further includes: the method comprises the steps that a main end interface receives a configuration request of a main end, and the configuration request for configuring a common configuration register is sent to a slave end interface in a unicast mode;
and receiving a configuration request from the slave-side interface and delivering the configuration request to the slave-side configuration common configuration register.
Further, in some embodiments, in order to facilitate the differentiation of the configuration requests by the interface modules of the master and slave, the common configuration register and the master configuration register are configured in advance as different system address field segments. In the above steps, after the master interface and the slave interface receive the configuration request, the master configuration register or the common configuration register is configured according to the domain segment to which the system address belongs to identify that the configuration request is configured. Certainly, the configuration requests for configuring the main configuration register and the general configuration register may also be distinguished in other ways, and the embodiment of the present invention is not particularly limited.
Specifically, for step 603, the receiving, by the slave interface, the configuration request, and determining whether the master configuration register or the shadow register is configured by the slave according to the system address in the configuration request specifically includes:
judging whether a system address belongs to an address field segment of a local register according to a local main configuration register/shadow register address translation table;
when the system address is judged to belong to the address field segment of the local register, the slave end configures a main configuration register or a shadow register and feeds back a response result of whether the processing is successful or not; and when the system address is judged not to belong to the address field section of the local register, directly feeding back a response result of successful processing.
After the slave end is configured with the master configuration register or the shadow register, a response result of successful processing is fed back, and when the slave end device does not work normally or the master end does not have authority, a response result of failed processing is returned.
Based on the above, each slave interface locally maintains a master configuration register/shadow register address translation table, and according to the address translation table, it can be determined whether the master configuration register or the shadow register to be configured belongs to the register in the corresponding slave. When the register belongs to a main configuration register or a shadow register in the slave end, the configuration of the register can be carried out. And when the register does not belong to the local register, the corresponding slave end does not perform corresponding processing, and a response of successful processing is directly sent to the master end.
The main configuration register/shadow register address translation table has controllable content and is easy to physically realize. In practical implementation, the method can be set in a flexible configuration or hardware solidification mode. Furthermore, from the viewpoint of chip design, only the slave interface needs to convert the address of the main configuration register/shadow register used by the corresponding slave, and the shadow register used by other functional modules does not need to be concerned, so that the design complexity can be avoided, and the design is easy to physically implement.
Further, in some embodiments, the register configuration method further includes:
the master end interface waits for response results fed back by all the slave ends;
and when all the response results are successfully processed, feeding back the configuration request to the master end, wherein the configuration request is successfully processed.
It can be known that, for the configuration request, after the processing is completed, the slave end needs to feed back a response indicating whether the processing is successful to the master end, so that the master end determines whether the processing of the configuration request is successful, whether subsequent processing work such as resending is needed, and the like, and further improves the configuration process of the register.
It should be noted that, in the method embodiment, only the implementation of each step is briefly described. For details of the individual steps, reference may be made to the description in the device example. The method embodiment is not described in detail.
The technical contents of the present invention will be further described in detail with reference to specific examples.
Fig. 7 is a schematic diagram of a general internal architecture of a chip according to an alternative embodiment of the present invention. The system includes 2 master function modules M0, M1, and 3 slave function modules A, B, C. The 5 functional modules are interconnected through a system bus, and each functional module is respectively mounted on the system bus or an on-chip interconnection network through an interface module. The inside of the functional module of 3 slaves all has configuration registers: the A module comprises an a0 register and an a1 register, the B module comprises a B0 register and a B1 register, and the C module comprises a C0 register and a C1 register; the a0 register of the A module is a main configuration register, and the B0 register of the corresponding B module is a shadow register of the a0 register of the A module; the C1 register of the C Module is the main configuration register and correspondingly the B1 register of the B Module is the shadow register of the C1 register of the C Module. For the setting of system address, here, system addresses 0x1000 to 0x2000 are divided into main configuration register/shadow register address field segments, and the rest addresses are normal register addresses: that is, the addresses of the configuration registers of the 3 slave functional modules are respectively: 0x1000(a0 register), 0x0(a1 register), 0x1000(b0 register), 0x1004(b1 register), 0x4(c0 register), 0x1004(c1 register).
As shown in fig. 8, a data flow diagram of the configuration shadow register inside the chip provided in fig. 7 is shown. When the main function module M0 needs to configure the a0 register of the module a, the method specifically includes:
step 801, M0 issues a configuration request of a0 register;
step 802, the M0 interface module recognizes that the system address 0x1000 of the configuration request belongs to the address field of the configuration register with the shadow register, and sets the broadcast type of the configuration request and forwards the configuration request to the system bus or the on-chip internet;
step 803, the system bus or the on-chip internet broadcasts the configuration request to the interface module A, the interface module B and the interface module C;
step 804, the interface module a recognizes that the system address 0x1000 of the configuration request belongs to the address field of the configuration register with the shadow register, recognizes that the received configuration request address belongs to the corresponding module a by looking up the local main configuration register/shadow register address translation table, translates the system address into the address of the configuration register inside the module a according to the address translation table, and sends the configuration request to the module a;
the B interface module recognizes that a system address 0x1000 of a configuration request belongs to a configuration register address with a shadow register, recognizes that the received configuration request address belongs to a corresponding B module by searching a local main configuration register/shadow register address translation table, translates the system address into an internal configuration register address of the B module according to the address translation table, and sends the configuration request to the B module;
the C interface module recognizes that the system address 0x1000 of the configuration request belongs to the configuration register address with the shadow register, and finds that the system address of the configuration request does not belong to the C module by looking up the local master configuration register/shadow register address translation table, and therefore directly returns a processing success response to the M0 interface module.
Step 805, the module a receives the configuration request to configure a0 register, and returns the response result to the M0 interface module through the module a; the B module receives the configuration request to configure the B0 register and returns the response result to the M0 interface module through the B interface module;
in step 806, the M0 interface module receives the response results returned by the modules a, B, and C, and if the results are all successful, returns a processing success response to the M0 module, otherwise returns a processing failure response to the M0 module.
Similarly, the configuration flow of the M1 module to the c1 register and the b1 register is available, and will not be described herein.
Further, as shown in fig. 9, a data flow diagram of the general configuration register inside the chip provided in fig. 7 is shown. When the main function module M0 needs to configure the a1 register of the module a, the method specifically includes:
step 901, M0 issues a configuration request for a1 register;
step 902, the M0 interface module recognizes that the system address 0x0 of the configuration request belongs to the address of the common configuration register, and sets the unicast type of the configuration request and forwards the configuration request to the system bus or the on-chip internet;
step 903, the system bus or the on-chip internet sends a configuration request unicast to the a interface module.
Step 904, the a interface module recognizes that the system address 0x0 of the configuration request belongs to the address of the common configuration register, and directly sends the configuration request to the a module;
step 905, the module a receives the configuration request to configure the a1 register, and returns the response result to the M0 interface module through the module a;
in step 906, the M0 interface module receives the response result returned by the a module, and if the results are both successful, returns a processing success response to the M0 module.
Based on the above, in the embodiment of the present invention, all the main configuration registers/shadow registers in the system are addressed separately, and are distinguished from the normal configuration registers. Software (or other functional modules for sending configuration information) only needs to configure the main configuration register, and the configuration of all shadow registers can be completed without concerning the information of the shadow registers. The system bus master does not need to know the information of the shadow register in the whole design, and only needs to broadcast the configuration of the master configuration register to all the system bus slaves, so that the system bus master is relatively simple in design and easy to physically realize. And each system bus slave end only needs to maintain the address of the main configuration register/shadow register to which the subsequent functional module belongs through an address translation table, and does not need to pay attention to all the main configuration registers/shadow registers in the system, so that the controllability of the design scale can be ensured, the physical implementation is easy, and the occupation of logic resources is less. The increase and decrease of the system bus master end/the system bus slave end or the design modification of the shadow register of part of the system bus slave end can not affect other parts in the design, thereby ensuring the independence and the expandability of the system.
Accordingly, as shown in fig. 10, an embodiment of the present invention provides a CPU chip 10 including at least one processor core 101. A processor core 101 to:
receiving a configuration request of a master end through a master end interface, and sending the configuration request for configuring a master configuration register to at least one slave end interface in a broadcasting mode;
receiving a configuration request through a slave-side interface, and determining whether a master configuration register or a shadow register is configured by a slave side according to a system address in the configuration request:
wherein the pre-configured main configuration register and the shadow register have the same system address.
In some embodiments, a processor core 101 to:
receiving a configuration request of a master end through a master end interface, and sending the configuration request for configuring a common configuration register to a slave end interface in a unicast mode;
and receiving a configuration request through the slave-side interface and handing the configuration request to the slave-side to configure the common configuration register.
In some embodiments, a processor core 101 to:
and sending the configuration request of the master-side interface to the slave-side interface through a system bus or an on-chip interconnection network.
In some embodiments, a processor core 101 to:
after the main end interface and the slave end interface receive the configuration request, identifying whether the configuration request is a configuration main configuration register or a configuration common configuration register according to the domain section of the system address:
the common configuration register and the main configuration register are configured in advance to be different system address field sections.
In some embodiments, a processor core 101 to:
judging whether a system address belongs to an address field section of a local register or not through a slave-end interface according to a local main configuration register/shadow register address translation table;
when the system address is judged to belong to the address field segment of the local register, the slave end configures the main configuration register or the shadow register and feeds back whether the response result is processed successfully or not.
In some embodiments, a processor core 101 to:
and when the slave-end interface judges that the system address does not belong to the address domain section of the local register, directly feeding back a response result of successful processing.
In some embodiments, a processor core 101 to:
waiting for response results fed back by all the slave ends through the master end interface;
and when all the response results are successfully processed, feeding back the configuration request to the master end, wherein the configuration request is successfully processed.
The CPU chip of this embodiment may adopt the above technical solution of the register configuration method, and the implementation principle and the technical effect are similar, which are not described herein again.
Accordingly, as shown in fig. 11, an electronic device provided by an embodiment of the present invention may include: the electronic device comprises a shell 61, a processor 62, a memory 63, a circuit board 64 and a power circuit 65, wherein the circuit board 64 is arranged inside a space enclosed by the shell 61, and the processor 62 and the memory 63 are arranged on the circuit board 64; a power supply circuit 65 for supplying power to each circuit or device of the electronic apparatus; the memory 63 is used to store executable program code; the processor 62 executes a program corresponding to the executable program code by reading the executable program code stored in the memory 63, for executing any one of the register configuration methods provided in the foregoing embodiments.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The term "comprising", without further limitation, means that the element so defined is not excluded from the group consisting of additional identical elements in the process, method, article, or apparatus that comprises the element.
All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments.
For convenience of description, the above devices are described separately in terms of functional division into various units/modules. Of course, the functionality of the units/modules may be implemented in one or more software and/or hardware implementations of the invention.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (22)
1. A register configuration apparatus, comprising:
the configuration module is used for pre-configuring the same system address of the main configuration register and the shadow register;
the master end interface module is used for receiving a configuration request of a master end and sending the configuration request for configuring the master configuration register to at least one slave end interface module in a broadcast mode;
and the slave end interface module is used for receiving the configuration request and determining whether the master configuration register or the shadow register is configured by the slave end according to the system address in the configuration request.
2. The register configuration apparatus according to claim 1,
the master end interface module is also used for receiving a configuration request of the master end and sending the configuration request for configuring the common configuration register to a slave end interface module in a unicast mode;
the slave-end interface module is further configured to receive the configuration request and deliver the configuration request to the slave end to configure the common configuration register.
3. The register configuration apparatus according to claim 1 or 2, wherein the master interface module sends the configuration request to the slave interface module through a system bus or an on-chip interconnection network.
4. The register configuring apparatus according to claim 2, wherein the configuring module is further configured to pre-configure the general configuration register and the main configuration register to be different system address field segments;
the master-end interface module and/or the slave-end interface module are specifically configured to, after receiving the configuration request, identify, according to the domain segment to which the system address belongs, that the configuration request is to configure a master configuration register or configure the general configuration register.
5. The register configuration device according to claim 1 or 4, wherein the slave interface module is specifically configured to:
judging whether the system address belongs to an address field segment of a local register or not according to a local main configuration register/shadow register address translation table;
and when the system address is judged to belong to the address field segment of the local register, the slave end is handed to configure the main configuration register or the shadow register, and a response result of whether the processing is successful is fed back.
6. The register configuration device according to claim 5, wherein the slave interface module is further configured to directly feed back a response result of successful processing when it is determined that the system address does not belong to the address field segment of the local register.
7. The register configuration apparatus according to claim 1, wherein the master interface module is further configured to:
waiting for response results fed back by all the slave interface modules;
and when all the response results are successfully processed, feeding back the success of processing the configuration request to the master terminal.
8. A register configuration method, comprising:
pre-configuring a main configuration register and a shadow register to have the same system address;
a master end interface receives a configuration request of a master end and sends the configuration request for configuring the master configuration register to at least one slave end interface in a broadcast mode;
and the slave-end interface receives the configuration request and determines whether the master configuration register or the shadow register is configured by the slave end according to the system address in the configuration request.
9. The register configuration method according to claim 8, further comprising:
the method comprises the steps that a main end interface receives a configuration request of a main end, and the configuration request for configuring a common configuration register is sent to a slave end interface in a unicast mode;
and receiving the configuration request from the slave-end interface, and delivering the configuration request to the slave-end to configure the common configuration register.
10. A register configuration method according to claim 8 or 9, wherein the master interface sends the configuration request to the slave interface via a system bus or an on-chip interconnect network.
11. The register configuration method according to claim 9, further comprising:
pre-configuring the common configuration register and the main configuration register to be different system address field sections;
after a main end interface and/or a slave end interface receives a configuration request, the configuration request is identified to configure a main configuration register or configure the common configuration register according to the domain section of the system address.
12. The register configuration method according to claim 8 or 11, wherein the receiving the configuration request by the slave interface and determining whether the master configuration register or the shadow register is configured by the slave according to the system address in the configuration request comprises:
judging whether the system address belongs to an address field segment of a local register or not according to a local main configuration register/shadow register address translation table;
and when the system address is judged to belong to the address field segment of the local register, the slave end configures the main configuration register or the shadow register and feeds back a response result of whether the processing is successful or not.
13. The register configuration method according to claim 12, further comprising:
and when the system address is judged not to belong to the address field section of the local register, directly feeding back a response result of successful processing.
14. The register configuration method according to claim 8, further comprising:
the master end interface waits for response results fed back by all the slave ends;
and when all the response results are successfully processed, feeding back the success of processing the configuration request to the master terminal.
15. A CPU chip, comprising: at least one processor core, the processor core to:
receiving a configuration request of a master end through a master end interface, and sending the configuration request for configuring the master configuration register to at least one slave end interface in a broadcasting mode;
receiving the configuration request through a slave interface, and determining whether the master configuration register or the shadow register is configured by a slave according to a system address in the configuration request:
wherein the pre-configured main configuration register and the shadow register have the same system address.
16. The CPU chip of claim 15, wherein the processor core is further configured to:
receiving a configuration request of a master end through a master end interface, and sending the configuration request for configuring a common configuration register to a slave end interface in a unicast mode;
and receiving the configuration request through a slave-end interface, and delivering the configuration request to a slave-end to configure the common configuration register.
17. The CPU chip of claim 15, wherein the processor core is configured to:
and sending the configuration request of the master end interface to the slave end interface through a system bus or an on-chip internet.
18. The CPU chip of claim 15, wherein the processor core is further configured to:
after a main end interface and/or a slave end interface receives a configuration request, identifying whether the configuration request is to configure a main configuration register or configure the common configuration register according to a domain section to which a system address belongs:
and the common configuration register and the main configuration register are configured in advance to be different system address field sections.
19. The CPU chip according to claim 15 or 18, wherein the processor core is specifically configured to:
judging whether the system address belongs to an address field segment of a local register or not through the slave-end interface according to a local main configuration register/shadow register address translation table;
and when the system address is judged to belong to the address field segment of the local register, the slave end configures the main configuration register or the shadow register and feeds back a response result of whether the processing is successful or not.
20. The CPU chip of claim 19, wherein the processor core is further configured to:
and when the slave-end interface judges that the system address does not belong to the address domain section of the local register, directly feeding back a response result of successful processing.
21. The CPU chip of claim 15, wherein the processor core is further configured to:
waiting for response results fed back by all the slave terminals through the master terminal interface;
and when all the response results are successfully processed, feeding back the success of processing the configuration request to the master terminal.
22. An electronic device, comprising: the device comprises a shell, a processor, a memory, a circuit board and a power circuit, wherein the circuit board is arranged in a space enclosed by the shell, and the processor and the memory are arranged on the circuit board; a power supply circuit for supplying power to each circuit or device of the electronic apparatus; the memory is used for storing executable program codes; the processor executes a program corresponding to an executable program code by reading the executable program code stored in the memory, for executing the register configuration method of any one of the preceding claims 8 to 14.
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