CN112349700B - Airtight high heat conduction LCP packaging substrate and multi-chip system level packaging structure - Google Patents
Airtight high heat conduction LCP packaging substrate and multi-chip system level packaging structure Download PDFInfo
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Abstract
The invention discloses an airtight high-heat-conductivity LCP packaging substrate and a multi-chip system level packaging structure, wherein the LCP packaging substrate comprises n layers of patterned metal circuit layers distributed from the surface to the bottom, and the n layers of patterned metal circuit layers on the bottom are provided with structures for welding BGA solder balls; n-1 insulating dielectric layers positioned between adjacent patterned metal circuit layers; a plurality of blind grooves which are positioned in the insulating medium layer between the first patterned metal circuit layer and the second patterned metal circuit layer and are opened towards the first patterned metal circuit layer on the surface; the blind grooves comprise common chip mounting blind grooves and high-power chip mounting blind grooves; the metal block is positioned in the insulating medium layer and connected with the bottom of the high-power chip mounting blind groove; and a plurality of blind holes penetrating and connecting the adjacent patterned metal circuit layers. The LCP packaging substrate can meet the requirements of multiple chips, high air tightness, high electromagnetic shielding, high heat conduction and high reliable interconnection on system level packaging.
Description
Technical Field
The invention relates to the technical field of integrated circuits and chip packaging, in particular to an airtight high-heat-conductivity LCP packaging substrate and a multi-chip system level packaging structure, which are used for high-reliability system level packaging for high-frequency applications such as radio frequency, microwave, millimeter wave and the like.
Background
With the advancement of semiconductor and integrated circuit technologies, the requirements of system integration are further improved, and the current electronic circuit design and manufacture are both developed towards smaller size and higher integration density, so that considerable work is performed in the field of multi-chip packaging. In an advanced package form, a plurality of Radio Frequency (RF) chips, digital Integrated Circuit (IC) chips, micro chip type components, and the like are assembled on a package substrate by SIP technology and then integrated into one package body. The multi-chip packaging form shortens the pin distance between chips, greatly improves the packaging density and can meet the requirements of system-in-package to a certain extent.
The packaging modes can be generally divided into two types according to different packaging substrate materials: one is a multilayer ceramic package having a cavity structure, and the other is a plastic package using a multilayer PCB substrate as a chip substrate material.
The ceramic package substrate has the advantages of high integration density, high reliability, high air tightness, high heat conductivity, excellent corrosion resistance and the like. However, due to the thermal mismatch between the ceramic material and the PCB material, large-size package cannot be performed, and meanwhile, the ceramic package has the problem of extremely high manufacturing cost.
The plastic packaging substrate has the characteristics of low cost, relatively simple process and higher interconnection density, and can realize secondary high-density interconnection with the PCB motherboard in the form of BGA and the like. The biggest defect is that the common PCB material has high moisture absorption rate and poor water vapor blocking performance, and can not realize airtight packaging; meanwhile, the dielectric properties (dielectric constant and dielectric loss) of the common resin material are limited, and the resin material cannot be applied to radio frequency/microwave transmission. These deficiencies limit the application of plastic packages in high reliability, high performance chip packages, whose main field of application is consumer electronics today.
The Liquid Crystal Polymer (LCP) material has the outstanding advantages of excellent dielectric transmission characteristics, extremely low moisture absorption rate, water permeability and oxygen permeability, planar thermal expansion coefficient matched with copper, high heat resistance, chemical corrosion resistance and the like, meets the severe requirements of a radio frequency/microwave chip on a packaging substrate material, and is a new generation of substrate material with high reliability, high performance, huge potential in the chip packaging application field and wide application prospect.
Chinese patent CN106486427A, CN206259334U discloses a packaging case based on LCP substrate and a preparation method, wherein the LCP substrate is used as a substrate layer for mounting a chip, and technologies such as chip assembly, metal enclosure, and cover plate welding are used as auxiliary materials, so as to provide a solution for airtight packaging of the chip. In this package form, a specific structure and a manufacturing method as a package substrate are not given; the packaging form lacks an external interconnection interface, so that the secondary cascade of the packaging body cannot be realized; the LCP substrate does not have the characteristic of circuit partition, cannot provide a good electromagnetic shielding basis for a multi-chip complex system, and the problem of circuit crosstalk is difficult to avoid.
Chinese patent CN102593077a discloses a liquid crystal polymer packaging structure, which is a structure for airtight packaging of chips formed by combining a high melting point LCP composite cover plate and a low melting point LCP tube shell by hot melting. The package structure is too simple and does not relate to specific structural features and implementation methods of the substrate.
Chinese patent CN104282632B discloses a packaging case based on LCP substrate and a method for preparing the same, which uses LCP multilayer substrate as carrier to hermetically package chips. The LCP packaging substrate structure is divided into a surface sealing layer, a chip mounting layer, a welding layer, an interconnection layer and the like, and each component structure characteristic is limited. In the substrate structure, the holes of the circuit interconnection layer are positioned at the periphery of the chip sealing area, and the periphery of the chip is non-airtight due to the existence of the through holes; the surface layer is defined as a sealing area, and is designed separately from the inner bonding layer, and is electrically disconnected or only connected with the ground. The disclosed implementation method adopts a mode of multi-lamination and hot pressing. The LCP adhesive film material is thermoplastic in nature and theoretically cannot be laminated multiple times, so the process of this construction is very difficult and impractical to achieve.
Chinese patent CN107324273B discloses a packaging method for MEMS devices based on LCP multilayer stacking technology, in which a cap for MEMS devices is prepared by multilayer LCP stacking lamination, and LCP materials are directly applied to plastic packaging of single chips. In the invention, the LCP material only plays a role of a packaging cap, and the application field does not relate to a packaging substrate, and wiring design cannot be performed.
Chinese patent CN102683220B discloses a method for fabricating a multi-layer organic liquid crystal polymer substrate structure, in which active and passive devices can be embedded into the multi-layer liquid crystal polymer substrate simultaneously, so as to achieve hermetic packaging of the chip. The active device with the salient points is connected to the LCP substrate by using a flip-chip bonding technology, then the LCP adhesive film is windowed, laminated and finally interconnected through a metalized through hole, and finally the packaging structure is formed. The packaging structure adopts a manufacturing route of the chip embedded substrate, is mainly oriented to single-chip packaging, and is not applicable to multi-chip packaging application with high electromagnetic shielding requirements; the interconnection holes of the substrate are manufactured through one-time drilling metallization, the interconnection function of the substrate is simple, and the complex interconnection requirements of the multi-chip package cannot be met.
Chinese patent CN106252339B discloses a high-density radio frequency multi-chip package structure, which uses a multi-layer substrate and a housing as a carrier, and stacks a plurality of chips and devices in a vertical direction for three-dimensional high-density hybrid integration. The multi-chip package is essentially mixed integration in a multi-chip package body, has limited electromagnetic shielding performance, relates to multi-temperature gradient and solder selection, and has difficult process realization.
Chinese patent CN103165479B discloses a method for manufacturing a multi-chip system-in-package structure, in which a plurality of chips are integrated on an interposer in a manner of vertically stacking the multi-chips to form a system-in-package structure. The structure is suitable for high-density integration of the IC chip, but is not suitable for electromagnetic shielding requirements of multiple radio frequency chips.
Chinese patent CN103930989B discloses a radio frequency package on package circuit, which forms a two-level package of a radio frequency package on package (PoP) circuit by vertical stacking of two radio frequency packages. The structure package body does not relate to the electromagnetic shielding problem of the chip in the single package body in detail, and the substrate has simple function and is not described in detail in the aspect of the substrate structure.
U.S. patent No. 2019/0080817Al discloses a manufacturing method of an LCP resin multilayer substrate, which can improve flatness and avoid manufacturing problems such as warping caused by glue shortage by using special LCP paste as an adhesive layer and a thickness adjusting layer of the LCP multilayer substrate. The interconnected holes of the substrate structure are filled with the conductive paste, and the substrate manufactured by the method cannot bear high-temperature application occasions because the adhesive component of the conductive paste volatilizes at high temperature to cause the risk of substrate delamination, bubbling and even board explosion. And the adhesion of the LCP paste to the LCP layer, the LCP paste to the conductive paste, is much poorer theoretically than in conventional LCP adhesive film lamination methods. The multilayer LCP substrate manufactured in this way is not suitable for radio frequency chip packaging applications with high interconnect hole reliability.
The prior art has not realized a technical solution for realizing a packaging substrate and a system-in-package structure which meet the requirements of system-in-package of multiple chips, high air tightness, high electromagnetic shielding, high heat conduction and high reliable interconnection by using LCP.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: in order to solve the above problems, an airtight high-thermal-conductivity LCP packaging substrate and a multi-chip system-in-package structure based on the same are provided, wherein the LCP packaging substrate utilizes excellent high-frequency transmission characteristics, extremely low moisture absorption and water permeability of Liquid Crystal Polymer (LCP) materials, and high thermal conductivity of embedded metal blocks, so as to meet the system-in-package requirements of multi-chip, high airtight requirements, high electromagnetic shielding, high thermal conductivity and high reliable interconnection.
The invention provides an LCP packaging substrate, which comprises:
n layers of patterned metal circuit layers distributed from the surface to the bottom surface, wherein the n layers of patterned metal circuit layers on the bottom surface are provided with structures for welding BGA solder balls;
n-1 insulating dielectric layers positioned between adjacent patterned metal circuit layers;
a plurality of blind grooves which are positioned in the insulating medium layer between the first patterned metal circuit layer and the second patterned metal circuit layer and are opened towards the first patterned metal circuit layer on the surface; the blind grooves comprise common chip mounting blind grooves and high-power chip mounting blind grooves;
the metal block is positioned in the insulating medium layer and connected with the bottom of the high-power chip mounting blind groove;
and a plurality of blind holes penetrating and connecting the adjacent patterned metal circuit layers.
Further, the first patterned metal circuit layer comprises a circle of surrounding metal layer at the outer edge and a plurality of groups of chip I/O welding and signal transmission circuit layers at the inner side of the surrounding metal layer, each group of chip I/O welding and signal transmission circuit layers is in a rectangular or irregularly-shaped island shape, and each group of chip I/O welding and signal transmission circuit layers is connected with the surrounding metal layer through an electric insulation area; the electrical property of the surrounding metal layer is a grounding layer, and the technological property is an airtight welding layer; the upper surface of the first patterned metal circuit layer is sequentially provided with a coating layer and an upper surface solder resist layer; the coating layer covers the surrounding metal layer and each group of chip I/O welding and signal transmission line layers; the upper surface solder mask comprises a first surrounding solder mask layer and a plurality of second surrounding solder mask layers, wherein each second surrounding solder mask layer correspondingly surrounds each electric insulation area, and the first surrounding solder mask layer surrounds all the second surrounding solder mask layers;
each group of chip I/O welding and signal transmission line layers comprises a chip I/O welding pad, a signal transmission line and one or more blind grooves; the transmission of signals in each group of chip I/O welding and signal transmission circuit layers is completed jointly through the chip I/O welding and signal transmission circuit in each group of chip I/O welding and signal transmission circuit layers or through corresponding parts in each layer of blind holes and the lower layer of patterned metal circuit layers; the I/O welding of two or more groups of chips and the signal transmission between the signal transmission layers are completed by the blind holes of each layer and the corresponding parts in the lower patterned metal circuit layer.
Further, the n-1 insulating dielectric layers are each composed of an LCP substrate.
Further, the common chip mounting blind groove and the high-power chip mounting blind groove are chip I/O pads or patterns around the opening of the first patterned metal circuit layer; the bottom of the common chip mounting blind groove is a large-area metal grounding layer in the second patterned metal circuit layer; and coating layers are arranged at the bottoms of the common chip mounting blind groove and the high-power chip mounting blind groove.
Further, the number and size of the blind slots are determined according to the number and size of the mounted chips.
Further, the thickness of the metal block is determined according to the heat dissipation requirement of the high-power chip; and the bottom of the metal block is connected with a blind hole below the metal block for grounding.
Further, the metal block is made of copper metal.
Further, all blind holes can be aligned or staggered and stacked in the vertical direction, so that the requirement of interconnection of any layer in the n layers of patterned metal circuit layers can be met; the diameter of each blind hole is the same, the depth-diameter ratio of the blind holes is less than or equal to 1, and the blind holes are filled with solid electroplated copper.
Further, the lower surface of the n-th patterned metal circuit layer is provided with a coating layer; the LCP packaging substrate is provided with a bonding pad or a pattern for external secondary cascade I/O welding and a lower surface solder mask layer on a coating layer on the lower surface of the n-th patterned metal circuit layer; the window of the lower surface solder mask layer is circular and distributed in grid array for welding BGA solder balls.
The invention also provides a multi-chip system-in-package structure, comprising: the LCP packaging substrate, the BGA solder balls, the chips, the metal surrounding frame and the metal cover plate;
the BGA solder balls are welded on the bottom surface of the LCP packaging substrate and serve as secondary cascade I/O interfaces of the multi-chip system-in-package structure;
the metal surrounding frame is internally provided with metal separation ribs; the metal surrounding frame and the metal spacer ribs are welded on the upper surface of the LCP packaging substrate, and the metal cover plate is welded on the metal surrounding frame and the metal spacer ribs, so that a plurality of cavity structures with airtight packaging performance and electromagnetic shielding performance are formed between the LCP packaging substrate and the metal cover plate through the metal surrounding frame and the metal spacer ribs; each cavity structure comprises one or more blind grooves; each blind groove is used for installing a chip, when the installed chip has no electromagnetic shielding requirement, the blind grooves are installed in the same cavity structure, and when the installed chip has the electromagnetic shielding requirement, the blind grooves are installed in different cavity structures; the chip is adhered to the blind groove through conductive adhesive, and is electrically interconnected with the chip I/O welding and signal transmission circuit layer in the first patterned metal circuit layer in a gold wire bonding mode.
In summary, due to the adoption of the technical scheme, the beneficial effects of the invention are as follows:
1. the invention realizes the LCP packaging substrate for multi-chip airtight packaging by utilizing the excellent high-frequency transmission characteristic, extremely low moisture absorption and water permeability and oxygen transmittance of the Liquid Crystal Polymer (LCP) material and the high heat conduction characteristic of the embedded metal block.
2. The LCP packaging substrate is manufactured based on a full LCP material system, and can realize any layer interconnection wiring of a multi-layer graph circuit; the LCP packaging substrate comprises a plurality of blind grooves for chip installation, is matched with electromagnetic compatibility and process compatibility design of a substrate surface layer circuit and an embedded heat dissipation metal block, and is of an airtight packaging structure capable of meeting system-level packaging requirements of multiple chips, high airtight requirements, high electromagnetic shielding, high heat conduction and high reliable interconnection.
3. The multi-chip system level packaging structure realized by adopting the LCP packaging substrate realizes external secondary cascade connection by using the high-density grid array type BGA solder balls, has good compatibility with a PCB motherboard, and can be used for large-size and high-integration-density system level packaging.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic view showing the structure of an LCP package substrate according to embodiment 1 of the present invention;
wherein: 1-LCP package substrate; 11-patterning the metal circuit layer; 111-a first patterned metal circuit layer; 112-second through n-1 th patterned metal wiring layers; 113-nth patterned metal line layer; 121-a common chip mounting blind groove; 122-mounting a blind groove on a high-power chip; 13-coating layer; 14-blind holes; 141-a blind hole for grounding; 15-an insulating medium layer; 16-an intra-substrate signal transmission path; 17-upper surface solder mask; 18-a lower surface solder mask layer; 19-metal block.
FIG. 2 is a schematic diagram of a first patterned metal circuit layer according to embodiment 1 of the present invention;
wherein, 21, 22, 23-chip I/O welding and signal transmission line layer; 211. 221, 231-chip mounting blind slot positions; 212. 222, 232 chip I/O pads and signal transmission lines; 213. 223, 233-electrically insulating regions; 171. 172, 173-a second surrounding solder mask; 24-surrounding the metal layer; 174-a first surrounding solder mask; 16-signal transmission path within the substrate.
FIG. 3 is a schematic diagram of a sixth patterned metal circuit layer according to embodiment 1 of the present invention;
wherein, 18-lower surface solder mask; 181-grid array type solder mask windowing; 182-package substrate to external secondary cascade I/O pads or patterns.
Fig. 4a, 4b, and 4c are schematic structural diagrams of the metal block manufacturing process according to embodiment 1 of the present invention. Wherein: 191-blind groove cavity opening structure; 192-plating dry film resistance.
FIG. 5 is a schematic diagram of a multi-chip system-in-package structure based on LCP package substrate of embodiment 2 of the present invention;
wherein: 61-a multi-chip system in package structure; 1-LCP package substrate; 2-BGA solder balls; 3-chip; 31-a high power chip; 4-gold wire; 5-a metal surrounding frame; 51-metal spacer ribs; 6-a metal cover plate; 7-cavity structure; 16-signal transmission path within the substrate.
Detailed Description
The features and capabilities of the present invention are described in further detail below in connection with the examples.
Example 1
As shown in fig. 1, an airtight high thermal conductivity LCP package substrate of the present embodiment includes:
n layers of patterned metal circuit layers distributed from the surface to the bottom surface, wherein the n layers of patterned metal circuit layers on the bottom surface are provided with structures for welding BGA solder balls;
n-1 insulating dielectric layers positioned between adjacent patterned metal circuit layers;
a plurality of blind grooves which are positioned in the insulating medium layer between the first patterned metal circuit layer and the second patterned metal circuit layer and are opened towards the first patterned metal circuit layer on the surface; the blind grooves comprise common chip mounting blind grooves and high-power chip mounting blind grooves;
the metal block is positioned in the insulating medium layer and connected with the bottom of the high-power chip mounting blind groove;
and a plurality of blind holes penetrating and connecting the adjacent patterned metal circuit layers.
1. n layers of patterned metal circuit layers:
as shown in fig. 2, the first patterned metal circuit layer 111 includes a ring of surrounding metal layer 24 at an outer edge and a plurality of groups of chip I/O solder and signal transmission circuit layers 21, 22, 23 inside the surrounding metal layer 24, each group of chip I/O solder and signal transmission circuit layers 21, 22, 23 has a rectangular or irregularly shaped island, and each group of chip I/O solder and signal transmission circuit layers 21, 22, 23 is connected to the surrounding metal layer 24 via an electrically insulating region 213, 223, 233; the electrical property of the surrounding metal layer 24 is a ground layer and the process property is an airtight welding layer; the upper surface of the first patterned metal circuit layer 111 is sequentially provided with a coating layer 13 and an upper surface solder resist layer 17; the coating layer 13 covers the surrounding metal layer 24 and each group of chip I/O welding and signal transmission line layers 21, 22 and 23; the upper surface solder mask 17 comprises a first surrounding solder mask 174 and a plurality of second surrounding solder masks 171, 172, 173, wherein each second surrounding solder mask 171, 172, 173 surrounds each electrically insulating region 213, 223, 233, and the first surrounding solder mask 174 surrounds all second surrounding solder masks 171, 172, 173;
each group of chip I/O welding and signal transmission line layers 21, 22 and 23 comprises chip I/O welding pads, signal transmission lines 212, 222 and 232 and one or more blind grooves; the transmission of signals in each group of chip I/O soldering and signal transmission line layers 21, 22, 23 is completed jointly through the chip I/O pads and signal transmission lines 212, 222, 232 in the group of chip I/O soldering and signal transmission line layers 21, 22, 23 or through corresponding parts in each blind hole 14 and the lower patterned metal line layer (the second layer to the n-1 patterned metal line layer 112 and the n-th patterned metal line layer 113); the I/O bonding of two or more chips and the signal transmission between the signal transmission layers are completed by the blind holes 14 and the corresponding parts of the lower patterned metal circuit layers (the second layer to the n-1 layer patterned metal circuit layer 112 and the n-1 layer patterned metal circuit layer 113), such as the transmission path 16 in FIG. 2.
The second to n-1 th patterned metal circuit layers 112, which include a plurality of groups of chip I/O solder and signal transmission circuit layers, an electrically insulating region and a surrounding metal layer, are conventional patterned metal circuit layers, and their specific structures are not described herein.
As shown in fig. 3, the lower surface of the n-th patterned metal circuit layer 113 has a coating layer; on the coating layer of the lower surface of the n-th patterned metal circuit layer 113, there are provided a pad or pattern 182 for external secondary cascade I/O soldering of the LCP package substrate 1, and a lower surface solder resist layer 18; the lower surface solder mask layer 18 has a circular window 181 and is distributed in a grid array for soldering the BGA solder balls 2.
2. Insulating dielectric layer
The n-1 insulating dielectric layers 15 are each composed of an LCP substrate, that is, the insulating dielectric layer 15 is made of a Liquid Crystal Polymer (LCP) to utilize the excellent high frequency transmission characteristics, extremely low moisture absorption and water permeability of the LCP material.
3. Blind groove
The common die-mounting blind groove 121 and the high-power die-mounting blind groove 122 are die I/O pads or patterns (i.e., die I/O pads or patterns in the die I/O pads and signal transmission lines 212, 222, 232) around the opening of the first patterned metal line layer 111; the bottom of the common chip mounting blind groove 121 is a large-area metal grounding layer in the second patterned metal circuit layer 112; the bottoms of the normal chip mounting blind groove 121 and the high power chip mounting blind groove 122 are provided with a coating layer 13. The number and size of the blind slots (121, 122) are determined according to the number and size of the mounted chips.
4. Metal block
The thickness of the metal block 19 is determined according to the heat dissipation requirement of the high-power chip, for example, in fig. 1, the metal block may occupy 1 insulating dielectric layer or 2 insulating dielectric layers; and the bottom of the metal block 19 is connected with a blind hole 141 for grounding thereunder. The metal block 19 needs to have high heat conduction characteristics, and copper metal can be selected generally.
The metal block 19 can be manufactured by performing pattern electroplating thickening on the high-power chip mounting blind groove 122; the method comprises the following steps:
as shown in fig. 4 a: the patterned metal circuit layer and the insulating medium layer in the blind groove are removed by laser and other modes at the preset blind groove to form the preset blind groove cavity opening structure 191.
As shown in fig. 4 b: the blind trench cavity structure 191 is pattern plated to thicken to form the embedded metal block 19.
As shown in fig. 4 c: the plating resist dry film 192 on the upper and lower surfaces is removed. Finally, pressing a single-sided copper-clad LCP substrate (a first patterned metal circuit layer is manufactured on the copper-clad side) to form the LCP multilayer substrate required by the invention.
5. Blind hole
All the blind holes 14 can be aligned or staggered in the vertical direction for realizing any layer interconnection requirement in the n-layer patterned metal circuit layer 11. In addition, the diameter of each blind hole 14 is the same, the depth-to-diameter ratio of the blind holes is less than or equal to 1, and the blind holes 14 are filled with solid electroplated copper. All the blind holes 14 have the same diameter, and on one hand, the solid electroplated copper can be uniformly manufactured for the purpose of post filling; more importantly, the integrated packaging substrate can be uniformly deformed in the later high-temperature assembly process, so that the interconnection reliability of the integrated packaging substrate is improved. The depth-diameter ratio of the blind holes is less than or equal to 1, so that the process of filling the blind holes with solid copper plating can be better realized, and the defect of copper plating holes is avoided.
Example 2
As shown in fig. 5, based on the LCP package substrate described in embodiment 1, the present embodiment provides a multi-chip system-in-package structure 61, including: the LCP package substrate 1 as described in embodiment 1, and BGA solder balls 2, chip 3, metal enclosure 5, and metal cover plate 6;
the BGA solder balls 2 are welded on the bottom surface of the LCP packaging substrate 1 and serve as a secondary cascade I/O interface of the multi-chip system-in-package structure 61;
the metal surrounding frame 5 is internally provided with metal separation ribs 51; the metal surrounding frame 5 and the metal barrier ribs 51 are welded on the upper surface of the LCP packaging substrate 1, the metal cover plate 6 is welded on the metal surrounding frame 5 and the metal barrier ribs 51, so that a plurality of cavity structures 7 with airtight packaging performance and electromagnetic shielding performance are formed between the LCP packaging substrate 1 and the metal cover plate 6 through the metal surrounding frame 5 and the metal barrier ribs 51; each cavity structure 7 contains one or more blind slots (which may be normal chip mounting blind slots 121 and/or high power chip mounting blind slots 122); each blind slot is used for installing one chip 3 (the chip corresponds to the blind slot, namely, the high-power chip 31 is installed in the high-power chip installation blind slot 122), when the installed chip 3 has no electromagnetic shielding requirement, the chip can be installed in the same cavity structure 7, and when the installed chip 3 has the electromagnetic shielding requirement, the chip is installed in different cavity structures 7; the chip 3 is adhered to the blind groove through conductive adhesive, and is electrically interconnected with the chip I/O welding and signal transmission circuit layers 21, 22 and 23 in the first patterned metal circuit layer 111 in a bonding mode of the gold wire 4;
the transmission of signals in each group of chip I/O soldering and signal transmission line layers 21, 22, 23 is completed jointly through the chip I/O pads and signal transmission lines 212, 222, 232 in the group of chip I/O soldering and signal transmission line layers 21, 22, 23 or through corresponding parts in each blind hole 14 and the lower patterned metal line layer (the second layer to the n-1 patterned metal line layer 112 and the n-th patterned metal line layer 113); the I/O bonding of two or more chips and the signal transmission between the signal transmission layers 21, 22, 23 are completed by the blind holes 14 and the corresponding parts of the lower patterned metal circuit layers (the second layer to the n-1 layer patterned metal circuit layer 112 and the n-1 layer patterned metal circuit layer 113), such as the transmission path 16 in FIG. 5.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (8)
1. An airtight high thermal conductivity LCP package substrate, comprising:
n layers of patterned metal circuit layers distributed from the surface to the bottom surface, wherein the n layers of patterned metal circuit layers on the bottom surface are provided with structures for welding BGA solder balls;
n-1 insulating dielectric layers positioned between adjacent patterned metal circuit layers; the n-1 insulating medium layers are all composed of LCP substrates;
a plurality of blind grooves which are positioned in the insulating medium layer between the first patterned metal circuit layer and the second patterned metal circuit layer and are opened towards the first patterned metal circuit layer on the surface; the blind grooves comprise common chip mounting blind grooves and high-power chip mounting blind grooves;
the metal block is positioned in the insulating medium layer and connected with the bottom of the high-power chip mounting blind groove;
a plurality of blind holes penetrating and connecting adjacent patterned metal circuit layers;
the first patterned metal circuit layer comprises a circle of surrounding metal layer at the outer edge and a plurality of groups of chip I/O welding and signal transmission circuit layers at the inner side of the surrounding metal layer, each group of chip I/O welding and signal transmission circuit layers is in a rectangular or irregularly-shaped island shape, and each group of chip I/O welding and signal transmission circuit layers is connected with the surrounding metal layer through an electric insulation area; the electrical property of the surrounding metal layer is a grounding layer, and the technological property is an airtight welding layer; the upper surface of the first patterned metal circuit layer is sequentially provided with a coating layer and an upper surface solder resist layer; the coating layer covers the surrounding metal layer and each group of chip I/O welding and signal transmission line layers; the upper surface solder mask comprises a first surrounding solder mask layer and a plurality of second surrounding solder mask layers, wherein each second surrounding solder mask layer correspondingly surrounds each electric insulation area, and the first surrounding solder mask layer surrounds all the second surrounding solder mask layers;
each group of chip I/O welding and signal transmission line layers comprises a chip I/O welding pad, a signal transmission line and one or more blind grooves; the transmission of signals in each group of chip I/O welding and signal transmission circuit layers is completed jointly through the chip I/O welding and signal transmission circuit in each group of chip I/O welding and signal transmission circuit layers or through corresponding parts in each layer of blind holes and the lower layer of patterned metal circuit layers; the I/O welding of two or more groups of chips and the signal transmission between the signal transmission layers are completed by the blind holes of each layer and the corresponding parts in the lower patterned metal circuit layer.
2. The LCP package substrate of claim 1, wherein the common die attach blind trench and the high power die attach blind trench are die I/O pads or patterns around the opening of the first patterned metal wiring layer; the bottom of the common chip mounting blind groove is a large-area metal grounding layer in the second patterned metal circuit layer; and coating layers are arranged at the bottoms of the common chip mounting blind groove and the high-power chip mounting blind groove.
3. The LCP package substrate of claim 1, wherein the number and size of the blind slots are determined according to the number and size of the mounted chips.
4. The LCP package substrate of claim 1, wherein the thickness of the metal block is determined according to heat dissipation requirements of the high power chip; and the bottom of the metal block is connected with a blind hole below the metal block for grounding.
5. The LCP package substrate of claim 4, wherein the metal block is copper metal.
6. The LCP package substrate of claim 1, wherein all blind vias are vertically aligned or staggered to achieve any of the interconnect requirements of the n patterned metal wiring layers; the diameter of each blind hole is the same, the depth-diameter ratio of the blind holes is less than or equal to 1, and the blind holes are filled with solid electroplated copper.
7. The LCP package substrate of claim 1, wherein the n-th patterned metal wiring layer has a coating layer on a lower surface thereof; the LCP packaging substrate is provided with a bonding pad or a pattern for external secondary cascade I/O welding and a lower surface solder mask layer on a coating layer on the lower surface of the n-th patterned metal circuit layer; the window of the lower surface solder mask layer is circular and distributed in grid array for welding BGA solder balls.
8. A multi-chip system-in-package structure, comprising: the LCP package substrate of any one of claims 1-7, and BGA solder balls, chips, metal frames, and metal covers;
the BGA solder balls are welded on the bottom surface of the LCP packaging substrate and serve as secondary cascade I/O interfaces of the multi-chip system-in-package structure;
the metal surrounding frame is internally provided with metal separation ribs; the metal surrounding frame and the metal spacer ribs are welded on the upper surface of the LCP packaging substrate, and the metal cover plate is welded on the metal surrounding frame and the metal spacer ribs, so that a plurality of cavity structures with airtight packaging performance and electromagnetic shielding performance are formed between the LCP packaging substrate and the metal cover plate through the metal surrounding frame and the metal spacer ribs; each cavity structure comprises one or more blind grooves; each blind groove is used for installing a chip, when the installed chip has no electromagnetic shielding requirement, the blind grooves are installed in the same cavity structure, and when the installed chip has the electromagnetic shielding requirement, the blind grooves are installed in different cavity structures; the chip is adhered to the blind groove through conductive adhesive, and is electrically interconnected with the chip I/O welding and signal transmission circuit layer in the first patterned metal circuit layer in a gold wire bonding mode.
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| CN114615794A (en) * | 2022-02-22 | 2022-06-10 | 华为技术有限公司 | Circuit board, board-level architecture and electronic equipment |
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