CN112347725A - Modeling method and device of pixel unit - Google Patents
Modeling method and device of pixel unit Download PDFInfo
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Abstract
The invention relates to a modeling method and a device of a pixel unit, wherein the method comprises the following steps: acquiring photoelectric conversion data of a doped region, the doped region including: the clamp layer, the first doped region and the epitaxial layer; determining a current source model according to the photoelectric conversion data; acquiring first capacitance data of a capacitor formed in a doped region; determining a first capacitance model according to the first capacitance data; acquiring second capacitance data of a capacitor formed by the output area and the isolation area; determining a second capacitance model according to the second capacitance data; acquiring electrical data of an MOS (metal oxide semiconductor) tube consisting of a transmission gate, a clamping layer and an isolation region; determining an MOS tube model according to the electrical data; and constructing a current source model, a first capacitance model, a second capacitance model and an MOS (metal oxide semiconductor) transistor model to obtain a pixel unit model. Therefore, when the pixel unit is modeled, the pixel unit model can be directly obtained, and the efficiency of modeling the pixel unit is further improved.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a modeling method and device of a pixel unit.
Background
An image sensor is a Device for converting an optical signal into an electrical signal, wherein the image sensor may be classified into a Complementary Metal Oxide Semiconductor (CMOS) image sensor and a Charge Coupled Device (CCD) image sensor according to the difference of elements, and the CMOS image sensor has advantages of smaller size, lower power consumption and higher integration level in the same image quality scene as the CCD image sensor, so the CMOS image sensor is widely used.
In the prior art, a CMOS image sensor includes at least: the pixel array comprises a plurality of pixel units, wherein the pixel units can adopt photodiodes to realize photoelectric conversion. In the process of designing a pixel unit, a developer may model and simulate the pixel unit by calling an existing device model in a Computer Aided Design (TCAD) tool, so as to optimize the Design of the pixel unit.
However, the inventor of the present invention found in the process of modeling the pixel unit that there is no existing pixel unit model in the existing device model modeling, resulting in a low efficiency of modeling the pixel unit.
Disclosure of Invention
The disclosure aims to provide a modeling method and a device for a pixel unit, which are used for solving the problem of low efficiency of modeling the pixel unit.
In order to achieve the above object, in a first aspect of the embodiments of the present disclosure, a modeling method of a pixel unit is provided, including:
acquiring photoelectric conversion data of a doped region, the doped region comprising: the semiconductor device comprises a clamping layer, a first doping region and an epitaxial layer, wherein a first type of material doped in the first doping region is different from a semiconductor material type of a second type of material doped in the clamping layer and the epitaxial layer;
determining a current source model according to the photoelectric conversion data;
acquiring first capacitance data of a capacitor formed in the doped region;
determining a first capacitance model according to the first capacitance data;
acquiring second capacitance data of a capacitor formed by the output region and the isolation region;
determining a second capacitance model according to the second capacitance data;
acquiring electrical data of an MOS (metal oxide semiconductor) tube consisting of a transmission gate, the clamping layer and the isolation region;
determining an MOS tube model according to the electrical data;
and building the current source model, the first capacitance model, the second capacitance model and the MOS tube model to obtain a pixel unit model.
Further, before the constructing the current source model, the first capacitance model, the second capacitance model, and the MOS transistor model to obtain the pixel unit model, the method further includes:
acquiring first delay parameter information of the doped region, wherein the first delay parameter information comprises any one or a combination of the following items: the doping concentration of the doping region, the shape of the first doping region, the contact area between the first doping region and the transmission gate and the thickness of the epitaxial layer;
determining a first delay model according to the first delay parameter information;
acquiring second delay parameter information of the doped region, wherein the second delay parameter information comprises any one or a combination of the following items: a voltage difference between the first doped region and the output region, an initial number of electrons inside the first doped region, a length of the first doped region, and a voltage of the transfer gate;
determining a second delay model according to the second delay parameter information;
the building the current source model, the first capacitance model, the second capacitance model and the MOS transistor model to obtain a pixel unit model includes:
and building the current source model, the first capacitance model, the second capacitance model, the first delay model, the second delay model and the MOS tube model to obtain a pixel unit model.
Further, the MOS transistor model includes:
the MOS transistor comprises a first MOS transistor model formed by the transmission gate and the clamping layer and a second MOS transistor model formed by the transmission gate and the isolation region.
Further, the MOS transistor model further includes:
and D, directly connecting the drain electrode of the first MOS tube model with the source electrode of the second MOS tube model, wherein the drain electrode capacitance of the first MOS tube model is set to be 0, and the source electrode capacitance of the second MOS tube model is set to be 0.
Further, with the drain electrode of first MOS transistor model with the source electrode of second MOS transistor model directly links, the drain electrode electric capacity of first MOS transistor model sets up to 0, the source electrode electric capacity of second MOS transistor model sets up to 0, include:
setting a source-drain junction capacitance per unit area of the first MOS transistor model to be 0, setting a source-drain side wall junction capacitance per unit length of the first MOS transistor model to be 0, setting a gate-drain overlap capacitance per unit width of the first MOS transistor model to be 0, and setting a gate-source overlap capacitance of the first MOS transistor model to be 0;
setting the unit area source-drain junction capacitance of the second MOS tube model to be 0, setting the unit length source-drain side wall junction capacitance of the second MOS tube model to be 0, setting the unit width gate-drain overlap capacitance of the second MOS tube model to be 0, and setting the gate-source overlap capacitance of the second MOS tube model to be 0.
Further, the photoelectric conversion data includes a difference between a first current and a leakage current, the first current includes a current formed by photoelectric conversion of all light waves received by the pixel unit, the leakage current includes a current flowing out in a reverse direction of a PN junction, and the PN junction includes a space charge region formed between the first doped region and the epitaxial layer.
In a first aspect of the embodiments of the present disclosure, a modeling apparatus for a pixel unit is provided, including:
a first obtaining module, configured to obtain photoelectric conversion data of a doped region, where the doped region includes: the semiconductor device comprises a clamping layer, a first doping region and an epitaxial layer, wherein a first type of material doped in the first doping region is different from a semiconductor material type of a second type of material doped in the clamping layer and the epitaxial layer;
the first processing module is used for determining a current source model according to the photoelectric conversion data;
the second acquisition module is used for acquiring first capacitance data of a capacitor formed by the doped region;
the second processing module is used for determining a first capacitance model according to the first capacitance data;
the third acquisition module is used for acquiring second capacitance data of a capacitor formed by the output region and the isolation region;
the third processing module is used for determining a second capacitance model according to the second capacitance data;
the fourth acquisition module is used for acquiring the electrical data of the MOS tube formed by the transmission gate, the clamping layer and the isolation region;
the fourth processing module is used for determining the MOS tube model according to the electrical data;
and the building module is used for building the current source model, the first capacitance model, the second capacitance model and the MOS tube model to obtain a pixel unit model.
Further, the method also comprises the following steps: a fifth obtaining module, configured to obtain first delay parameter information of the doped region, where the first delay parameter information includes any one of or a combination of the following: the doping concentration of the doping region, the shape of the first doping region, the contact area between the first doping region and the transmission gate and the thickness of the epitaxial layer;
a fifth processing module, configured to determine a first delay model according to the first delay parameter information;
a sixth obtaining module, configured to obtain second delay parameter information of the doped region, where the second delay parameter information includes any one of or a combination of the following: a voltage difference between the first doped region and the output region, an initial number of electrons inside the first doped region, a length of the first doped region, and a voltage of the transfer gate;
a sixth processing module, configured to determine a second delay model according to the second delay parameter information;
the building module is configured to build the current source model, the first capacitance model, the second capacitance model, the first delay model, the second delay model, and the MOS transistor model to obtain a pixel unit model.
Further, the MOS transistor model includes: the MOS transistor comprises a first MOS transistor model formed by the transmission gate and the clamping layer and a second MOS transistor model formed by the transmission gate and the isolation region.
Further, the MOS transistor model further includes:
and D, directly connecting the drain electrode of the first MOS tube model with the source electrode of the second MOS tube model, wherein the drain electrode capacitance of the first MOS tube model is set to be 0, and the source electrode capacitance of the second MOS tube model is set to be 0.
By the technical scheme, the modeling method and device of the pixel unit provided by the disclosure comprise the following steps: acquiring photoelectric conversion data of a doped region, the doped region comprising: the semiconductor device comprises a clamping layer, a first doping region and an epitaxial layer, wherein a first type of material doped in the first doping region is different from a semiconductor material type of a second type of material doped in the clamping layer and the epitaxial layer; determining a current source model according to the photoelectric conversion data; acquiring first capacitance data of a capacitor formed in the doped region; determining a first capacitance model according to the first capacitance data; acquiring second capacitance data of a capacitor formed by the output area and the isolation area; determining a second capacitance model according to the second capacitance data; acquiring electrical data of an MOS (metal oxide semiconductor) tube consisting of a transmission gate, the clamping layer and the isolation region; determining an MOS tube model according to the electrical data; and building the current source model, the first capacitance model, the second capacitance model and the MOS tube model to obtain a pixel unit model. Therefore, when the pixel unit is modeled, the pixel unit model can be directly obtained, and the efficiency of modeling the pixel unit is further improved.
Additional features and advantages of the disclosure will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure without limiting the disclosure. In the drawings:
FIG. 1 is a schematic structural diagram of a pixel unit according to an embodiment of a modeling method of the pixel unit of the invention;
FIG. 2 is a schematic diagram of an embodiment of a modeling method for a pixel cell of the present invention;
FIG. 3 is a schematic structural diagram of a modeling apparatus for a pixel unit according to an embodiment of the invention;
fig. 4 is a schematic structural diagram of another embodiment of a modeling apparatus for a pixel unit according to the present invention.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the exemplary embodiments below are not intended to represent all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.
Fig. 1 is a schematic structural diagram of a pixel unit according to an embodiment of a modeling method of the pixel unit of the invention, as shown in fig. 1, the pixel unit includes: the P-type substrate P-sub1 is provided with a P-type epitaxial layer P-epi2, one region of the P-type epitaxial layer P-epi2 is provided with an N-type doped region PDN3, meanwhile, the upper surface of the N-type doped region PDN3 is provided with a clamping layer 6, the other region of the P-type epitaxial layer P-epi2 is provided with an isolation region, an output region FD4 is arranged in the isolation region, a transmission gate TX5 is formed on the upper surface of the P-type epitaxial layer P-epi2, and the lower surface of the transmission gate TX5 is directly connected with the output region FD4 and the N-type doped region PDN3 respectively. Specifically, when power is applied to the transfer gate TX5, an inversion layer is formed between the N-type doped region PDN3 and the output region FD4, and the inversion layer serves as a conduction channel through which photo-generated electrons of the N-type doped region PDN3 are output from the output region FD 4.
It should be noted that this embodiment also provides another structure of a pixel unit, which is similar to the structure shown in fig. 1, except that the type of the doped material in the same region is different from that in fig. 1, for example, the pixel unit includes: the N-type substrate N-sub and the N-type substrate N-sub are provided with an N-type epitaxial layer N-epi2, one region of the N-type epitaxial layer N-epi2 is provided with a P-type doped region, meanwhile, a clamping layer is arranged on the upper surface of the P-type doped region, the other region of the N-type epitaxial layer N-epi is provided with an isolation region, an output region is arranged in the isolation region, a transmission gate is formed on the upper surface of the N-type epitaxial layer N-epi, and the lower surface of the transmission gate is directly connected with the output region and the P-type doped region respectively.
In this embodiment, the obtaining of the equivalent circuit of the pixel unit through the above structure of the pixel unit specifically includes:
the current source comprises a clamping layer, a first doping region and an epitaxial layer, and is used for performing photoelectric conversion and outputting a current region;
one end of the first capacitor is arranged between the current source and the source electrode of the MOS tube, and the first capacitor comprises a capacitor formed by a clamping layer, a first doping region and an epitaxial layer;
the source electrode of the MOS tube is connected with one end of the first capacitor, the drain electrode of the MOS tube is connected with one end of the second capacitor, and the MOS tube comprises a transmission gate, the clamping layer and the isolation region;
the second capacitor comprises an area formed by an output area and an isolation area.
Fig. 2 is a schematic diagram of an embodiment of a modeling method of a pixel unit according to the present invention, and as shown in fig. 2, the embodiment provides a modeling method of a pixel unit, including:
The doped region in this embodiment includes: the clamp layer, the first doping area and the epitaxial layer are formed, and the first type of material doped in the first doping area is different from the second type of material doped in the clamp layer and the epitaxial layer. The clamp layer in this embodiment is formed by heavy doping of the second type material, thereby deactivating surface dangling bonds, effectively reducing the generation of dark current.
For example, the semiconductor material includes a P-type semiconductor material and an N-type semiconductor material, that is, when the first type material may be a P-type semiconductor material, the second type material may be an N-type semiconductor material; or, when the first type material may be an N-type semiconductor material, the second type material may be a P-type semiconductor material, where the P-type semiconductor material may be an ion of any one of group iii elements or group ii elements or a compound thereof, and the N-type semiconductor material may be an ion of any one of group v elements or a compound thereof; the second type material doped in the clamping layer and the second type material doped in the epitaxial layer may be the same or different, for example, for different materials, the second type material doped in the clamping layer may be an ion of one element of group v elements or a compound thereof, and the second type material doped in the epitaxial layer may be an ion of another element of group v elements or a compound thereof, wherein the concentration of the second type material doped in the clamping layer is different from the concentration of the second type material doped in the epitaxial layer.
Specifically, multiple sets of actually measured data are obtained, and each set of data includes: the voltage X is set on the pixel unit, and the output current I of the doped region corresponding to the voltage X.
specifically, firstly, actually measuring a voltage X set on a pixel unit and an output current I of a doped region corresponding to the voltage X; then, according to the actually measured data sets, I and X, by the first formula: i ═ a2+ (a1-a2)/(1+ (X/X0)∧P)，
After fitting, specific values of the parameters in the first formula, i.e., a1, a2, and X0, are obtained, thereby establishing the current source model.
the first capacitor in this embodiment is a capacitor formed by the clamping layer, the first doped region, and the epitaxial layer.
Specifically, actually measured sets of data Q1 and X, i.e., the voltage X set on the pixel unit and the charge number Q1 of the doped region corresponding to the voltage X, are obtained.
specifically, first, the actually measured voltage X set on the pixel unit and the charge number Q1 of the doped region corresponding to the voltage X; then, based on the actually measured sets of data, i.e., Q1 and X,
and by a second formula: q1 ═ a2+ (a1-a2)/(1+ exp ((X/X0)/dX)),
after fitting, the parameters of the second formula, i.e., a1, a2, X0, dX, are obtained, thereby establishing the first capacitance model.
specifically, a plurality of sets Q2 and X, i.e., a voltage X set on the pixel unit and a charge number Q2 of a capacitor formed by the isolation region and the output region corresponding to the voltage X, are actually measured. It should be noted that, when the voltage applied to the gate of the MOS transistor is large enough to turn on the MOS transistor, the voltage X set on the second capacitor is equal to the voltage X set on the first capacitor, otherwise, when the MOS transistor is not fully turned on, the voltage X set on the second capacitor is not equal to the voltage X set on the first capacitor.
specifically, first, the actually measured voltage X set on the pixel unit and the charge number Q2 of the doped region corresponding to the voltage X; then, based on the actually measured sets of Q2 and X,
and by a third formula: q2 ═ a2+ (a1-a2)/(1+ exp ((X/X0)/dX)),
after fitting, the parameters of the third formula, i.e., a1, a2, X0, dX, are obtained, thereby establishing the second capacitance model.
208, determining an MOS tube model according to the electrical data;
and 209, building the current source model, the first capacitance model, the second capacitance model and the MOS transistor model to obtain a pixel unit model.
Specifically, the output end of the current source model and the output end of the first capacitor model are respectively connected with one end of the MOS tube model, and the other end of the MOS tube model is connected with the input end of the second capacitor model, so that the pixel unit model is obtained.
In this embodiment, by acquiring photoelectric conversion data of a doped region, the doped region includes: the semiconductor device comprises a clamping layer, a first doping region and an epitaxial layer, wherein a first type of material doped in the first doping region is different from a semiconductor material type of a second type of material doped in the clamping layer and the epitaxial layer; determining a current source model according to the photoelectric conversion data; acquiring first capacitance data of a capacitor formed in the doped region; determining a first capacitance model according to the first capacitance data; acquiring second capacitance data of a capacitor formed by the output area and the isolation area; determining a second capacitance model according to the second capacitance data; acquiring electrical data of an MOS (metal oxide semiconductor) tube consisting of a transmission gate, the clamping layer and the isolation region; determining an MOS tube model according to the electrical data; and building the current source model, the first capacitance model, the second capacitance model and the MOS tube model to obtain a pixel unit model. Therefore, when the pixel unit is modeled, the pixel unit model can be directly obtained, and the efficiency of modeling the pixel unit is further improved.
On the basis of the foregoing embodiment, before the building the current source model, the first capacitance model, the second capacitance model, and the MOS transistor model to obtain the pixel unit model, the method further includes:
acquiring first delay parameter information of the doped region, wherein the first delay parameter information comprises any one or a combination of the following items: the doping concentration of the doping region, the shape of the first doping region, the contact area between the first doping region and the transmission gate and the thickness of the epitaxial layer;
determining a first delay model according to the first delay parameter information;
acquiring second delay parameter information of the first doped region and the output region, wherein the second delay parameter information includes any one or a combination of the following items: the voltage difference between the first doping region and the output region, the number of electrons in the first doping region, the length and the shape of the first doping region, the voltage of the transmission gate, the doping concentration of the first doping region and the doping dosage of the first doping region;
determining a second delay model according to the second delay parameter information;
the building the current source model, the first capacitance model, the second capacitance model and the MOS transistor model to obtain a pixel unit model includes:
and building the current source model, the first capacitance model, the second capacitance model, the first delay model, the second delay model and the MOS tube model to obtain a pixel unit model. Specifically, the first delay model is used for simulating the moving time information of electrons in a depletion region along a first direction, wherein the depletion region includes a first doped region and a region formed by an epitaxial layer on the epitaxial layer, and for example, the first delay model includes: the delay time is in direct proportion to the thickness of the epitaxial layer, the delay time is in direct proportion to the contact area, the contact area is the contact area between the first doping area and the transmission gate, the delay time and the shape of the first doping area are in a nonlinear relation, the doping concentration of the first doping area is in inverse proportion to the delay time, and the doping concentration of the epitaxial layer is in direct proportion to the delay time.
The second delay model is used for simulating the moving time information of electrons in the depletion region along a second direction, the second direction is perpendicular to the first direction, and the second direction may be a direction from the first doped region to the output region, where the depletion region includes the first doped region and a region formed on the epitaxial layer by the epitaxial layer, for example, the second delay model includes: the delay time is in direct proportion to the number of initial electrons in the first doped region, in inverse proportion to the length of the first doped region and the voltage difference, and in nonlinear relation to the voltage of the transmission gate.
On the basis of the above embodiment, the MOS transistor model includes: the first MOS tube model formed by the transmission gate TX and the clamping layer and the second MOS tube model formed by the transmission gate TX and the isolation region.
Further, on the basis of the above embodiment, the MOS transistor model further includes:
and D, directly connecting the drain electrode of the first MOS tube model with the source electrode of the second MOS tube model, wherein the drain electrode capacitance of the first MOS tube model is set to be 0, and the source electrode capacitance of the second MOS tube model is set to be 0.
The specific implementation is that the drain electrode of the first MOS tube model is directly connected with the source electrode of the second MOS tube model, the drain electrode capacitance of the first MOS tube model is set to be 0, and the method that the source electrode capacitance of the second MOS tube model is set to be 0 comprises the following steps:
setting a source-drain junction capacitance per unit area of the first MOS transistor model to be 0, setting a source-drain side wall junction capacitance per unit length of the first MOS transistor model to be 0, setting a gate-drain overlap capacitance per unit width of the first MOS transistor model to be 0, and setting a gate-source overlap capacitance of the first MOS transistor model to be 0;
setting the unit area source-drain junction capacitance of the second MOS tube model to be 0, setting the unit length source-drain side wall junction capacitance of the second MOS tube model to be 0, setting the unit width gate-drain overlap capacitance of the second MOS tube model to be 0, and setting the gate-source overlap capacitance of the second MOS tube model to be 0.
Further, on the basis of the above embodiment, the photoelectric conversion data includes a difference between a first current and a leakage current, the first current includes a current formed by photoelectric conversion of all light waves received by the pixel unit, the leakage current includes a current flowing out in a reverse direction of a PN junction, and the PN junction includes a space charge region formed between the first doped region and the epitaxial layer.
In this embodiment, through implementation of the foregoing embodiment, a pixel unit model with higher accuracy can be obtained, and when modeling a pixel unit, the pixel unit model can be directly obtained, and efficiency of modeling the pixel unit is improved.
Fig. 3 is a schematic structural diagram of an embodiment of a modeling apparatus for a pixel unit according to the present invention, and as shown in fig. 3, the embodiment provides a modeling apparatus for a pixel unit, including: a first obtaining module 301, a first processing module 302, a second obtaining module 303, a second processing module 304, a third obtaining module 305, a third processing module 306, a fourth obtaining module 307, a fourth processing module 308, and a building module 309, wherein,
a first obtaining module 301, configured to obtain photoelectric conversion data of a doped region, where the doped region includes: the semiconductor device comprises a clamping layer, a first doping region and an epitaxial layer, wherein a first type of material doped in the first doping region is different from a semiconductor material type of a second type of material doped in the clamping layer and the epitaxial layer;
a first processing module 302, configured to determine a current source model according to the photoelectric conversion data;
a second obtaining module 303, configured to obtain first capacitance data of a capacitance formed in the doped region;
a second processing module 304, configured to determine a first capacitance model according to the first capacitance data;
a third obtaining module 305, configured to obtain second capacitance data of a capacitance formed by the output region and the isolation region;
a third processing module 306, configured to determine a second capacitance model according to the second capacitance data;
a fourth obtaining module 307, configured to obtain electrical data of an MOS transistor formed by the transmission gate, the clamping layer CPX, and the isolation region;
the fourth processing module 308 is configured to determine a MOS transistor model according to the electrical data;
a building module 309, configured to build the current source model, the first capacitance model, the second capacitance model, and the MOS transistor model to obtain a pixel unit model.
Specifically, the implementation manner of each module in this embodiment is similar to the method and the technical effect shown in fig. 2, and is not described herein again.
In this embodiment, by acquiring photoelectric conversion data of a doped region, the doped region includes: the semiconductor device comprises a clamping layer, a first doping region and an epitaxial layer, wherein a first type of material doped in the first doping region is different from a semiconductor material type of a second type of material doped in the clamping layer and the epitaxial layer; determining a current source model according to the photoelectric conversion data; acquiring first capacitance data of a capacitor formed in the doped region; determining a first capacitance model according to the first capacitance data; acquiring second capacitance data of a capacitor formed by the output area and the isolation area; determining a second capacitance model according to the second capacitance data; acquiring electrical data of an MOS (metal oxide semiconductor) tube consisting of a transmission gate, the clamping layer and the isolation region; determining an MOS tube model according to the electrical data; and building the current source model, the first capacitance model, the second capacitance model and the MOS tube model to obtain a pixel unit model. Therefore, when the pixel unit is modeled, the pixel unit model can be directly obtained, and the efficiency of modeling the pixel unit is further improved.
Fig. 4 is a schematic structural diagram of another embodiment of the modeling apparatus for a pixel unit of the present invention, and as shown in fig. 4, on the basis of the above embodiment, the present embodiment provides a modeling apparatus for a pixel unit, further including: a fifth obtaining module 310, a fifth processing module 311, and a sixth obtaining module 312; a sixth processing module 313, wherein,
a fifth obtaining module 310, configured to obtain first delay parameter information of the doped region, where the first delay parameter information includes any one or a combination of the following: the doping concentration of the doping region, the shape of the first doping region, the contact area between the first doping region and the transmission gate and the thickness of the epitaxial layer;
a fifth processing module 311, configured to determine a first delay model according to the first delay parameter information;
a sixth obtaining module 312, configured to obtain second delay parameter information of the first doped region and the output region, where the second delay parameter information includes: the voltage difference between the first doping region and the output region, the number of electrons in the first doping region, the length and the shape of the first doping region, the voltage of the transmission gate, the doping concentration of the first doping region and the doping dosage of the first doping region;
a sixth processing module 313, configured to determine a second delay model according to the second delay parameter information;
the building module 309 is configured to build the current source model, the first capacitance model, the second capacitance model, the first delay model, the second delay model, and the MOS transistor model to obtain a pixel unit model.
On the basis of the above embodiment, the MOS transistor model includes: the MOS transistor comprises a first MOS transistor model formed by the transmission gate and the clamping layer and a second MOS transistor model formed by the transmission gate and the isolation region.
Further, on the basis of the above embodiment, the MOS transistor model further includes:
and D, directly connecting the drain electrode of the first MOS tube model with the source electrode of the second MOS tube model, wherein the drain electrode capacitance of the first MOS tube model is set to be 0, and the source electrode capacitance of the second MOS tube model is set to be 0.
Further, on the basis of the foregoing embodiment, the fourth processing module 308 is further configured to set a source-drain junction capacitance per unit area of the first MOS transistor model to 0, set a side wall junction capacitance per unit length of a source-drain of the first MOS transistor model to 0, set a gate-drain overlap capacitance per unit width of the first MOS transistor model to 0, and set a gate-source overlap capacitance of the first MOS transistor model to 0;
setting the unit area source-drain junction capacitance of the second MOS tube model to be 0, setting the unit length source-drain side wall junction capacitance of the second MOS tube model to be 0, setting the unit width gate-drain overlap capacitance of the second MOS tube model to be 0, and setting the gate-source overlap capacitance of the second MOS tube model to be 0.
Further, on the basis of the above embodiment, the photoelectric conversion data includes a difference between a first current and a leakage current, the first current includes a current of all optical wave conversions acquired by the pixel unit, the leakage current includes a current flowing out in a reverse direction of a PN junction, and the PN junction includes a space charge region formed between the first doped region and the epitaxial layer.
Specifically, the implementation manner of each module in this embodiment is similar to the method and the technical effect shown in fig. 2, and is not described herein again.
It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. Meanwhile, any combination can be made between various different embodiments of the disclosure, and the disclosure should be regarded as the disclosure of the disclosure as long as the combination does not depart from the idea of the disclosure. The present disclosure is not limited to the precise structures that have been described above, and the scope of the present disclosure is limited only by the appended claims.
Claims (10)
1. A method of modeling a pixel cell, comprising:
acquiring photoelectric conversion data of a doped region, the doped region comprising: the semiconductor device comprises a clamping layer, a first doping region and an epitaxial layer, wherein a first type of material doped in the first doping region is different from a semiconductor material type of a second type of material doped in the clamping layer and the epitaxial layer;
determining a current source model according to the photoelectric conversion data;
acquiring first capacitance data of a capacitor formed in the doped region;
determining a first capacitance model according to the first capacitance data;
acquiring second capacitance data of a capacitor formed by the output region and the isolation region;
determining a second capacitance model according to the second capacitance data;
acquiring electrical data of an MOS (metal oxide semiconductor) tube consisting of a transmission gate, the clamping layer and the isolation region;
determining an MOS tube model according to the electrical data;
and building the current source model, the first capacitance model, the second capacitance model and the MOS tube model to obtain a pixel unit model.
2. The method of claim 1, wherein before the constructing the current source model, the first capacitance model, the second capacitance model, and the MOS transistor model to obtain the pixel cell model, the method further comprises:
acquiring first delay parameter information of the doped region, wherein the first delay parameter information comprises any one or a combination of the following items: the doping concentration of the doping region, the shape of the first doping region, the contact area between the first doping region and the transmission gate and the thickness of the epitaxial layer;
determining a first delay model according to the first delay parameter information;
acquiring second delay parameter information of the doped region, wherein the second delay parameter information comprises any one or a combination of the following items: a voltage difference between the first doped region and the output region, an initial number of electrons inside the first doped region, a length of the first doped region, and a voltage of the transfer gate;
determining a second delay model according to the second delay parameter information;
the building the current source model, the first capacitance model, the second capacitance model and the MOS transistor model to obtain a pixel unit model includes:
and building the current source model, the first capacitance model, the second capacitance model, the first delay model, the second delay model and the MOS tube model to obtain a pixel unit model.
3. The method of modeling a pixel cell according to claim 1, wherein the MOS transistor model comprises:
the MOS transistor comprises a first MOS transistor model formed by the transmission gate and the clamping layer and a second MOS transistor model formed by the transmission gate and the isolation region.
4. The method of modeling a pixel cell of claim 3, wherein the MOS transistor model further comprises:
and D, directly connecting the drain electrode of the first MOS tube model with the source electrode of the second MOS tube model, wherein the drain electrode capacitance of the first MOS tube model is set to be 0, and the source electrode capacitance of the second MOS tube model is set to be 0.
5. The method for modeling a pixel unit according to claim 4, wherein the step of directly connecting the drain of the first MOS transistor model with the source of the second MOS transistor model, the drain capacitance of the first MOS transistor model being set to 0, and the source capacitance of the second MOS transistor model being set to 0 comprises:
setting a source-drain junction capacitance per unit area of the first MOS transistor model to be 0, setting a source-drain side wall junction capacitance per unit length of the first MOS transistor model to be 0, setting a gate-drain overlap capacitance per unit width of the first MOS transistor model to be 0, and setting a gate-source overlap capacitance of the first MOS transistor model to be 0;
setting the unit area source-drain junction capacitance of the second MOS tube model to be 0, setting the unit length source-drain side wall junction capacitance of the second MOS tube model to be 0, setting the unit width gate-drain overlap capacitance of the second MOS tube model to be 0, and setting the gate-source overlap capacitance of the second MOS tube model to be 0.
6. The method for modeling a pixel cell according to any of claims 1-5, wherein said photoelectric conversion data comprises a difference between a first current and a leakage current, said first current comprising a current formed by said pixel cell photoelectrically converting an entire received light wave, said leakage current comprising a current flowing in a reverse direction of a PN junction, said PN junction comprising a space charge region formed between said first doped region and said epitaxial layer.
7. An apparatus for modeling a pixel unit, comprising:
a first obtaining module, configured to obtain photoelectric conversion data of a doped region, where the doped region includes: the semiconductor device comprises a clamping layer, a first doping region and an epitaxial layer, wherein a first type of material doped in the first doping region is different from a semiconductor material type of a second type of material doped in the clamping layer and the epitaxial layer;
the first processing module is used for determining a current source model according to the photoelectric conversion data;
the second acquisition module is used for acquiring first capacitance data of a capacitor formed by the doped region;
the second processing module is used for determining a first capacitance model according to the first capacitance data;
the third acquisition module is used for acquiring second capacitance data of a capacitor formed by the output region and the isolation region;
the third processing module is used for determining a second capacitance model according to the second capacitance data;
the fourth acquisition module is used for acquiring the electrical data of the MOS tube formed by the transmission gate, the clamping layer and the isolation region;
the fourth processing module is used for determining the MOS tube model according to the electrical data;
and the building module is used for building the current source model, the first capacitance model, the second capacitance model and the MOS tube model to obtain a pixel unit model.
8. The modeling apparatus of a pixel unit according to claim 7, further comprising: a fifth obtaining module, configured to obtain first delay parameter information of the doped region, where the first delay parameter information includes any one of or a combination of the following: the doping concentration of the doping region, the shape of the first doping region, the contact area between the first doping region and the transmission gate and the thickness of the epitaxial layer;
a fifth processing module, configured to determine a first delay model according to the first delay parameter information;
a sixth obtaining module, configured to obtain second delay parameter information of the doped region, where the second delay parameter information includes any one of or a combination of the following: a voltage difference between the first doped region and the output region, an initial number of electrons inside the first doped region, a length of the first doped region, and a voltage of the transfer gate;
a sixth processing module, configured to determine a second delay model according to the second delay parameter information;
the building module is configured to build the current source model, the first capacitance model, the second capacitance model, the first delay model, the second delay model, and the MOS transistor model to obtain a pixel unit model.
9. The modeling apparatus of a pixel cell according to claim 8, wherein the MOS transistor model comprises: the MOS transistor comprises a first MOS transistor model formed by the transmission gate and the clamping layer and a second MOS transistor model formed by the transmission gate and the isolation region.
10. The modeling apparatus of a pixel cell according to claim 9, wherein the MOS transistor model further comprises:
and D, directly connecting the drain electrode of the first MOS tube model with the source electrode of the second MOS tube model, wherein the drain electrode capacitance of the first MOS tube model is set to be 0, and the source electrode capacitance of the second MOS tube model is set to be 0.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101677106A (en) * | 2008-09-17 | 2010-03-24 | 三星电子株式会社 | Pixel cell, image sensor including a pixel cell, system having the same, and method of forming a pixel cell |
| JP2011091337A (en) * | 2009-10-26 | 2011-05-06 | Fujifilm Corp | Mos image sensor, method of driving mos image sensor, and imaging device |
| US20150249101A1 (en) * | 2012-10-19 | 2015-09-03 | Byd Company Limited | Pixel cell, method for manufacturing the same and image sensor comprising the same |
-
2019
- 2019-08-06 CN CN201910719622.2A patent/CN112347725B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101677106A (en) * | 2008-09-17 | 2010-03-24 | 三星电子株式会社 | Pixel cell, image sensor including a pixel cell, system having the same, and method of forming a pixel cell |
| JP2011091337A (en) * | 2009-10-26 | 2011-05-06 | Fujifilm Corp | Mos image sensor, method of driving mos image sensor, and imaging device |
| US20150249101A1 (en) * | 2012-10-19 | 2015-09-03 | Byd Company Limited | Pixel cell, method for manufacturing the same and image sensor comprising the same |
Non-Patent Citations (1)
| Title |
|---|
| 刘静: "PPD CMOS图像传感器像素单元的总剂量效应仿真模拟研究", 《中国优秀博硕士学位论文全文数据库(硕士) 工程科技Ⅱ辑》 * |
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Denomination of invention: A Modeling Method and Device for Pixel Units Effective date of registration: 20230714 Granted publication date: 20220823 Pledgee: Zhejiang Tailong Commercial Bank Co.,Ltd. Ningbo Fenghua sub branch Pledgor: XI'AN ABAX SENSING Co.,Ltd. Registration number: Y2023980048497 |