CN112334071A

CN112334071A - Device comprising a capacitive micromachined ultrasonic transducer directly coupled to an analog-to-digital converter

Info

Publication number: CN112334071A
Application number: CN201980041159.9A
Authority: CN
Inventors: 陈超; 陈凯亮; 赵良健; 鞠润宰; 基思·G·菲费
Original assignee: Butterfly Network Inc
Current assignee: Butterfly Network Inc
Priority date: 2018-06-19
Filing date: 2019-06-18
Publication date: 2021-02-05
Also published as: EP3809973A4; JP2021527361A; WO2019246010A8; TW202017534A; CA3103940A1; WO2019246010A1; EP3809973A1; AU2019288152A1; KR20210021531A

Abstract

Aspects of the technology described herein relate to an ultrasound device including a Capacitive Micromachined Ultrasonic Transducer (CMUT) directly electrically coupled to a delta-sigma analog-to-digital converter (ADC). The apparatus may be devoid of amplifiers or multiplexers between each CMUT and the delta-sigma ADC. The apparatus may include 100 to 20,000 CMUTs each of which is directly electrically coupled to one of the delta-sigma ADCs, and 100 to 20,000 delta-sigma ADCs. The CMUT and the delta-sigma ADC may be monolithically integrated on a single substrate. The delta-sigma ADC may not have a different integrator than the CMUT. The internal capacitance of the CMUT may act as an integrator for the delta-sigma ADC.

Description

Device comprising a capacitive micromachined ultrasonic transducer directly coupled to an analog-to-digital converter

Cross Reference to Related Applications

This application is a continuation-IN-part application claiming benefit of U.S. application serial No. 16/192,603, entitled "expedited applications AND METHODS FOR breaking available DEVICES", filed 11/15.2018, according to 35u.s.c. § 120, claiming benefit of U.S. application serial No. B1348.70065US01, entitled "expedited applications AND METHODS FOR using" united states application serial No. 62/586,716, entitled "METHODS AND APPARATUS FOR IMPLEMENTING INTEGRATED TRANSMIT AND RECEIVE circulating IN AN available DEVICES", filed 11/15.2017, B1348.70065US00, each of which is hereby incorporated by reference IN its entirety.

This application is also a benefit application of U.S. provisional application serial No. 62/687,189 entitled "apparatus systems application program TO AN ANALOG-TO-DIGITAL CONVERTER", filed 35u.s.c. § 119(e) on attorney docket No. B1348.70083US00 and entitled "apparatus systems application program A CAPACITIVE microprocessor ultra CONVERTER", filed 2018, 19.6.19.8, the entire contents of which are hereby incorporated by reference in their entirety.

Technical Field

In general, aspects of the technology described herein relate to ultrasound devices. Some aspects relate to an ultrasound apparatus including a Capacitive Micromachined Ultrasonic Transducer (CMUT) directly coupled to a delta-sigma analog-to-digital converter (ADC).

Background

Ultrasound devices may be used to perform diagnostic imaging and/or therapy using sound waves having high frequencies (relative to frequencies audible to humans). Ultrasound imaging may be used to view internal soft tissue volume structures, for example, to locate the source of a disease or to exclude any pathology (pathology). When a pulse of ultrasound is transmitted into tissue (e.g., by using a probe), the acoustic wave is reflected off the tissue, with different tissues reflecting different degrees of sound. These reflected acoustic waves can then be recorded and displayed to the operator as ultrasound images. The strength (amplitude) of the acoustic signal and the time it takes for the wave to travel in the body provide information for producing an ultrasound image. Many different types of images can be formed using ultrasound equipment, including real-time images. For example, an image may be generated showing a two-dimensional cross-section of tissue, blood flow, motion of tissue over time, location of blood, presence of specific molecules, stiffness of tissue, or anatomy of a three-dimensional region.

Disclosure of Invention

According to one aspect, an apparatus includes a Capacitive Micromachined Ultrasonic Transducer (CMUT) directly electrically coupled to a delta-sigma analog-to-digital converter (ADC). According to another aspect, an apparatus includes a Capacitive Micromachined Ultrasonic Transducer (CMUT) electrically coupled to a delta-sigma analog-to-digital converter (ADC), wherein the apparatus is free of a (lack) amplifier or multiplexer (multiplexer) between the CMUT and the delta-sigma ADC.

In some implementations of these aspects, the apparatus includes 100 to 1,000 CMUTs each of which is directly electrically coupled to one of the delta-sigma ADCs, and 100 to 1,000 delta-sigma ADCs. In some implementations of these aspects, the apparatus includes 1,000 to 10,000 CMUTs each of which is directly electrically coupled to one of the delta-sigma ADCs, and 1,000 to 10,000 delta-sigma ADCs. In some implementations of these aspects, the apparatus includes 10,000 to 20,000 CMUTs each of which is directly electrically coupled to one of the delta-sigma ADCs, and 10,000 to 20,000 delta-sigma ADCs. In some implementations of these aspects, the CMUT and the delta-sigma ADC are monolithically integrated on a single substrate. In some implementations of these aspects, the delta-sigma ADC does not have a different integrator than the CMUT. In some implementations of these aspects, the internal capacitance of the CMUT acts as an integrator for the delta-sigma ADC.

According to another aspect, an apparatus includes 100 to 20,000 CMUTs and one ADC dedicated to each of the CMUTs.

In some embodiments, the apparatus comprises 100 to 1,000 CMUTs. In some embodiments, the apparatus comprises 1,000 to 10,000 CMUTs. In some embodiments, the apparatus comprises 10,000 to 20,000 CMUTs. In some embodiments, the CMUT and the ADC are monolithically integrated on a single substrate.

According to another aspect, an apparatus comprises: a CMUT having an output terminal; a quantizer having an input terminal and an output terminal; and a current digital-to-analog converter (DAC) having an input terminal and an output terminal; wherein an output terminal of the CMUT is electrically coupled to an input terminal of the quantizer; an output terminal of the quantizer is electrically coupled to an input terminal of the current DAC; and an output terminal of the current DAC is electrically coupled to an input terminal of the quantizer.

In some embodiments, the quantizer is a 1.5 bit quantizer. In some embodiments, the output terminal of the CMUT is directly electrically coupled to the input terminal of the quantizer. In some embodiments, the apparatus is without an integrator between the output terminal of the CMUT and the input terminal of the quantizer. In some embodiments, the apparatus does not have an integrator between the output terminal of the current DAC and the input terminal of the quantizer.

According to another aspect, an apparatus comprises: a CMUT having an output terminal; a transconductance amplifier having an input terminal and an output terminal; a capacitor; a quantizer having an input terminal and an output terminal; a first current digital-to-analog converter (DAC) having an input terminal and an output terminal; and a second current digital-to-analog converter (DAC) having an input terminal and an output terminal; wherein an output terminal of the CMUT is electrically coupled to an input terminal of the transconductance amplifier; an output terminal of the transconductance amplifier is electrically coupled to an input terminal of the quantizer; an output terminal of the quantizer is electrically coupled to an input terminal of the first current DAC and an input terminal of the second current DAC; an output terminal of the first current DAC is electrically coupled to an input terminal of the transconductance amplifier; an output terminal of the second current DAC is electrically coupled to an output terminal of the transconductance amplifier; and the capacitor is electrically coupled between the output terminal of the transconductance amplifier and the DC voltage.

In some embodiments, the quantizer is a 1.5 bit quantizer. In some embodiments, the output terminal of the CMUT is directly electrically coupled to the input terminal of the quantizer. In some embodiments, the apparatus is without an integrator between the output terminal of the CMUT and the input terminal of the quantizer. In some embodiments, the apparatus is free of an integrator between the output terminal of the first current DAC and the input terminal of the quantizer.

According to another aspect, an apparatus comprises: a CMUT having an output terminal; a transconductance amplifier having an input terminal and an output terminal; a capacitor; a quantizer having an input terminal and an output terminal; a current digital-to-analog converter (DAC) having an input terminal and an output terminal; a voltage buffer having an input terminal and an output terminal; and a voltage adder having a first input terminal, a second input terminal, and an output terminal; wherein an output terminal of the CMUT is electrically coupled to an input terminal of the transconductance amplifier; an output terminal of the transconductance amplifier is electrically coupled to a first input terminal of the voltage adder; an input terminal of the voltage buffer is electrically coupled to an input terminal of the transconductance amplifier; an output terminal of the voltage buffer is electrically coupled to the second input terminal of the voltage adder; an output terminal of the voltage adder is electrically coupled to an input terminal of the quantizer; an output terminal of the quantizer is electrically coupled to an input terminal of the first current DAC; an output terminal of the current DAC is electrically coupled to an input terminal of the transconductance amplifier; and the capacitor is electrically coupled between the output terminal of the transconductance amplifier and the DC voltage.

Drawings

Various aspects and embodiments will be described with reference to the following exemplary and non-limiting figures. It should be understood that the drawings are not necessarily drawn to scale. Items appearing in multiple figures are indicated by the same or similar reference numbers in all of the figures in which they appear.

Fig. 1 shows an example circuit model of a Capacitive Micromachined Ultrasonic Transducer (CMUT);

figure 2 shows a diagram of a CMUT electrically coupled to a delta-sigma analog-to-digital converter (ADC);

figure 3 illustrates a diagram of a CMUT electrically coupled to another delta-sigma ADC according to some embodiments;

figure 4 shows a diagram of a CMUT electrically coupled to another delta-sigma ADC according to some embodiments;

figure 5 shows a diagram of a CMUT electrically coupled to another delta-sigma ADC according to some embodiments;

figure 6 shows a diagram of a CMUT electrically coupled to another delta-sigma ADC according to some embodiments;

figure 7 shows a diagram of a CMUT electrically coupled to another delta-sigma ADC according to some embodiments;

figure 8 shows a diagram of a CMUT electrically coupled to another delta-sigma ADC and a delta-sigma ADC electrically coupled to a filter and a jitter generator according to some embodiments;

FIG. 9 shows a diagram of the first current digital-to-analog converter (DAC) of FIG. 8 and its coupling to the transconductance amplifier of FIG. 8;

FIG. 10 illustrates a diagram of the second current DAC of FIG. 8 and its coupling to the transconductance amplifier and capacitor of FIG. 8, in accordance with certain embodiments;

FIG. 11 illustrates an example circuit implementation of the current source of FIG. 10 according to some embodiments;

FIG. 12 illustrates an example circuit implementation of the other current source of FIG. 10, in accordance with certain embodiments;

FIG. 13 illustrates an exemplary diagram of the jitter generator of FIG. 8 according to some embodiments; and

figure 14 illustrates an example diagram of an ultrasound system including CMUTs, ADCs, filters, and a digital beamformer, according to some embodiments.

Detailed Description

Conventional ultrasound systems are large, complex and expensive systems, typically purchased only by large medical institutions with a large amount of financial resources. Recently, cheaper and less complex ultrasound imaging devices have been introduced. Such an imaging device may include a Capacitive Micromachined Ultrasonic Transducer (CMUT) monolithically integrated onto a single semiconductor die to form a monolithic ultrasound device. Aspects of such on-chip ULTRASOUND devices are described in U.S. patent application No. 15/415,434 entitled "UNIVERSAL ULTRASOUND DEVICE AND RELATED APPARATUS AND METHODS," filed on 25/1/2017, the entire contents of which are incorporated herein by reference in their entirety.

In some ultrasound systems, the ultrasound signal received from a single ultrasound transducer element is typically an analog current signal that is converted to an analog voltage signal by a transimpedance amplifier of each element (where each element means one for each ultrasound transducer element in the ultrasound system). The analog voltage signal is then further processed by a time gain compensation amplifier for each element, which compensates for the attenuation of the ultrasound signal in the tissue of the imaged object. Transimpedance amplifiers and time gain compensation amplifiers that are analog amplifiers may consume a significant amount of power. After this analog amplification, it may not be practical to implement an analog-to-digital converter (ADC) for each element, as this, in combination with the power consumed by the analog amplifier, may exceed the power budget. Thus, to reduce the number of separate analog signals that must be digitized, analog beamforming is performed on the analog signals of each element. The analog output of the analog beamformer, which is fewer in number than the number of ultrasound transducer elements, is then digitized by the ADC. However, analog beamforming suffers from the following: low signal-to-noise ratio (SNR), low sampling resolution, inflexibility in delay patterns achieved by analog beamformers, and inflexibility in grouping ultrasound transducers for analog beamformer processing.

Digital beamforming, which performs beamforming on the digital signal of each element, may provide: higher SNR, higher sampling resolution, greater flexibility in delay patterns achieved by the digital beamformer, and greater flexibility in grouping ultrasound transducers for processing by the digital beamformer. However, digital beamforming requires: the analog ultrasound signals received from each ultrasound transducer element are individually digitized by the ADC of each element. Implementing and operating an ADC for each element presents the following challenges: the challenges include the power consumption of the ADC and the area in the integrated circuit required for the ADC per element.

The inventors have recognized that delta-sigma ADCs (also sometimes referred to as sigma-delta ADCs) may enable digitization of each element while not being impractical in power and area. In particular, in some embodiments, each CMUT of the ultrasound system is electrically coupled directly to the delta-sigma ADC of each element. Directly electrically coupling the CMUT to the delta-sigma ADC may mean that there is no amplifier or multiplexer between the CMUT and the delta-sigma ADC. The inventors have also recognized that the parasitic capacitance inherent to the CMUT may provide the delta-sigma ADC with the integration capability typically provided by a separate integrator component. Eliminating the need for a separate integrator component can further reduce power consumption and area.

The direct electrical coupling of the CMUT to the delta-sigma ADC should not be understood as: the exclusion CMUT is electrically coupled to the delta-sigma ADC through a switch electrically coupled between the CMUT and the delta-sigma ADC. More generally, not electrically coupling two components together and directly electrically coupling two components together is understood to mean: excluding a switch electrically coupled between the two components.

According to aspects of the present application, an ultrasonic transducer configured to generate an analog output signal is coupled to downstream processing circuitry that operates only in the digital domain. For example, in some embodiments, the ultrasound transducer is coupled to the ADC without the intervention of analog signal processing circuitry (including analog signal conditioning circuitry). In some implementations, the ultrasound transducer is coupled to the ADC without the intervention of an analog amplifier, multiplexer, filter, or other signal conditioning circuitry. The switch may couple the ultrasound transducer to the ADC, but the switch itself may not perform signal processing or conditioning. In some embodiments, the ultrasound transducer is coupled to the ADC without active circuitry intervening or without active circuitry other than a switch for coupling the ultrasound transducer to the ADC. In some embodiments, the ultrasound transducer is coupled to the ADC without the intervention of active analog circuitry. In some embodiments, the ADC is directly digitally coupled to the output of the ultrasound transducer without the intervention of analog signal processing or conditioning circuitry. In some embodiments, an ultrasound transducer may be said to be directly digitally coupled when its output is coupled to digital processing circuitry without the intervention of analog processing circuitry.

Fig. 1 shows an example circuit model of a Capacitive Micromachined Ultrasonic Transducer (CMUT) 100. The model of CMUT 100 includes current source 102, resistor 104, capacitor 106, inductor 108, capacitor 110, node 112, output terminal 114, and ground 116. Current source 102 is electrically coupled between node 112 and ground 116. Resistor 104 is electrically coupled between node 112 and ground 116. Capacitor 106 and inductor 108 are electrically coupled in series and electrically coupled between node 112 and output terminal 114. The capacitor 110 is electrically coupled between the output terminal 114 and ground 116. The current source 102 may model the current signal generated by the CMUT 100 in response to the ultrasonic waves. The resistor 104, the capacitor 106 and the inductor 108 may model the resonance characteristics of the CMUT 100. The capacitor 110 may model the parasitic capacitance of the CMUT 100. The current difference I between the current entering the output terminal 114 and the current leaving the output terminal 114 through the capacitor 110_CMUTCan be considered as the output current of CMUT 100.

Composed of a resistor 104 and a capacitor106 and the inductor 108 may be considered a low Q resonator because the Q of the resonator may be less than 0.5. The resistance of the resistor 104 may be significantly greater than 1/(ω C)_p) Where ω is the current signal I_CMUTFrequency of (C) and_pis the capacitance of capacitor 110. In some embodiments, C_pMay be on the order of a few tenths of a femto-farad (femtofarad) to tens of millifarads. In some embodiments, I_CMUTMay be on the order of tens of picoamperes to hundreds of microamperes, including any value in those ranges.

In some embodiments, the capacitance of the capacitor 110 dominates the behavior of the CMUT 100. Furthermore, as will be described below, the capacitor 110 may be used to provide an integration function for a delta-sigma ADC electrically coupled with the CMUT 100. This may eliminate the need for a separate integrator in the delta-sigma ADC. In contrast, in a circuit model of the piezoelectric ultrasonic transducer, an element forming a resonator in the piezoelectric ultrasonic transducer may dominate a parasitic capacitance element. Thus, parasitic capacitances within the piezoelectric ultrasound transducer may not be available for the integration function in the delta-sigma ADC. Furthermore, the resonant elements in piezoelectric ultrasound transducers may be undesirable and require the implementation of additional circuit elements for compensating the resonant behavior.

Fig. 2 illustrates a diagram of a CMUT 100 (as represented by the circuit model of the CMUT 100 described with reference to fig. 1) electrically coupled to a delta-sigma analog-to-digital converter (ADC)200 according to some embodiments. Fig. 2 also shows a pulse generator 124 and a switch 120. The delta-sigma ADC 200 includes a current integrator 218, a voltage quantizer 220, and a current digital-to-analog converter (current DAC or I)_DAC)222. The current integrator 218 includes an input terminal 226 and an output terminal 230. The voltage quantizer 220 includes an input terminal 228 and an output terminal 232. Current DAC 222 includes an input terminal 234 and an output terminal 236. Switch 120 includes an input terminal 118 and an output terminal 122. The pulse generator 124 includes an output terminal 126. (an input terminal (not shown in fig. 2) of pulse generator 124 may be electrically coupled to other circuitry.) output terminal 126 of pulse generator 124 is electrically coupled to output terminal 114 of CMUT 100. Input terminal 118 of switch 120 is electrically coupled to output terminal 114 of CMUT 100. Current DAC 2Output terminal 236 of 22 is electrically coupled to output terminal 122 of switch 120. Input terminal 226 of current integrator 218 is electrically coupled to output terminal 122 of switch 120. The output terminal 230 of the current integrator 218 is electrically coupled to the input terminal 228 of the quantizer. Output terminal 232 of voltage quantizer 220 is electrically coupled to input terminal 234 of current DAC 222. Output terminal 236 of current DAC 222 is electrically coupled to output terminal 122 of switch 100.

In operation, in a transmit mode, the switch 120 may be configured to be open (i.e., the input terminal 118 of the switch 120 is electrically disconnected from the output terminal 122 of the switch 120), thus the CMUT 100 is disconnected from the delta-sigma ADC 200. The pulse generator 124 may be configured to output a drive signal to the CMUT 100 for generating an ultrasonic signal based on the drive signal and transmitting the ultrasonic signal. Because the CMUT 100 is disconnected from the delta-sigma ADC 200, the delta-sigma ADC 200 may not interfere with the driving signal. In the receive mode, the switch 120 may be configured to be closed (i.e., the input terminal 118 of the switch 120 may be electrically connected to the output terminal 122 of the switch 120), thus connecting the CMUT 100 to the delta-sigma ADC 200. Fig. 2 shows the switch 120 in a receive mode. In this mode, the current I_CMUTMay flow from the output terminal 114 of the CMUT 100, through the closed switch 120 and into the input terminal 226 of the quantizer 218, and the current I_CMUTMay be considered as an input to the delta-sigma ADC 200. In other words, the current I_CMUTMay be a signal that the delta-sigma ADC 200 converts from analog to digital. Voltage D at output terminal 232 of voltage quantizer 220_OUTMay be considered the Output (OUT) of the delta-sigma ADC 200 and may be the analog signal I_CMUTIs shown in (a).

The delta-sigma ADC 200 includes a feedback loop in which the current integrator 218 and the voltage quantizer 220 are in a forward path of the feedback loop and the current DAC 222 is in a feedback path of the feedback loop. In operation, the current integrator 218 may be configured to couple I_CMUTIntegration is performed to generate an output voltage. Quantizer 220 may be configured to accept the output voltage as an input and output a digital logic level depending on whether the voltage is less than or greater than a threshold voltage. Over time, the digital logic level mayTo be the output D of the delta-sigma ADC_OUT. The current DAC 222 may be configured to accept digital logic levels as inputs and output a corresponding analog current I_feedback. By means of a feedback loop, I_feedbackMay be coupled to I at the output terminal 122 of the switch 120_CMUTAnd (4) adding. This feedback loop may provide negative feedback because, in response to the positive input signal of quantizer 220, quantizer 220 may output a digital logic level that is converted to a negative I by current DAC 222_feedback(ii) a And vice versa. D_OUTMay be a pulse stream in which the frequency of the pulses may be correlated with the input to the delta-sigma ADC 200 (i.e., the analog current signal I)_CMUT) And (4) in proportion. This frequency may be enforced by the feedback loop of the delta-sigma ADC 200 (effort). As will be further described, the delta-sigma ADC 200 may pair the processed input current signal I (e.g., at the quantizer 220)_CMUTOversampling is performed and a filter may decimate the sampled signal in order to improve the signal quantization to noise ratio (SQNR) of the delta-sigma ADC 200.

In some embodiments, the pulse generator 124 may be absent. Such an embodiment may be configured only for receiving ultrasound signals and not for transmitting ultrasound signals. The switch 120 may also be absent, as there may be no need to select between a transmit mode and a receive mode.

Fig. 3 illustrates a diagram of a CMUT 100 (as represented by the circuit model of the CMUT 100 described with reference to fig. 1) electrically coupled to a delta-sigma ADC 300 according to some embodiments. The delta-sigma ADC 300 differs from the delta-sigma ADC 200 in that the delta-sigma ADC 300 does not include the current integrator 218. In other words, the output terminal 114 of the CMUT 100 is electrically coupled directly (through the switch 120) to the input terminal 228 of the quantizer 220. Electrically coupling the output terminal 114 of the CMUT 100 directly to the input terminal 228 of the quantizer 220 may mean: there is no integrator between the output terminal 114 of the CMUT 100 and the input terminal 228 of the quantizer 220 that is different from the CMUT 100. The capacitor 110 of the CMUT 100 may operate as a current integrator and may replace the current integrator 218. In other words, the CMUT 100 may include an internal current integrator (capacitor 110), and coupling the CMUT 100 to the delta-sigma ADC 300 may enable the capacitor 110 to act as the current integrator of the delta-sigma ADC 300, and eliminate the need for another (i.e., different) current integrator between the CMUT 100 and the voltage quantizer 220. It should be noted that the capacitor 110 of the CMUT 100 may be considered to be in the feedback loop of the delta-sigma ADC 300.

Fig. 4 illustrates a diagram of a CMUT 100 (as represented by the circuit model of the CMUT 100 described with reference to fig. 1) electrically coupled to a delta-sigma ADC 400 according to some embodiments. The delta-sigma ADC 400 differs from the delta-sigma ADC 300 in that: the delta-sigma ADC 400 includes a voltage adder 438, a voltage integrator 450, and a voltage DAC (V)_DAC). The voltage adder 438 includes a first input terminal 440, a second input terminal 456, and an output terminal 442. The voltage integrator 450 includes an input terminal 452 and an output terminal 454. Voltage DAC 444 includes an input terminal 446 and an output terminal 448. A first input terminal 440 of the voltage adder 438 is electrically coupled to the output terminal 122 of the switch 120. The second input terminal 456 of the voltage adder 438 is electrically coupled to the output terminal 448 of the voltage DAC 444. The output terminal 442 of the voltage adder 438 is electrically coupled to the input terminal 452 of the voltage integrator 450. The output terminal 454 of the voltage integrator 450 is electrically coupled to the input terminal 228 of the voltage quantizer 220. Output terminal 232 of voltage quantizer 220 is electrically coupled to input terminal 446 of voltage DAC 444.

The delta-sigma ADC 400 includes two feedback loops. Capacitor 110, voltage adder 438, voltage integrator 450, and voltage quantizer 220 are in the forward path of the first feedback loop, and current DAC 222 is in the feedback path of the first feedback loop. The voltage adder 438, the voltage integrator 450, and the voltage quantizer 220 are in the forward path of the second feedback loop, and the voltage DAC 444 is in the feedback path of the second feedback loop. The presence of two feedback loops in the delta-sigma ADC 400 may be referred to as distributed feedback. The delta-sigma ADC 400 may be considered a second order delta-sigma ADC in that the delta-sigma ADC 400 includes two integrators (capacitor 110 and voltage integrator 450) and two feedback loops. In contrast, the delta-sigma ADC 200 and the delta-sigma ADC 300 may be considered first order delta-sigma ADCs because they include one integrator (including the current integrator 218 in the delta-sigma ADC 200 and the capacitor 110 in the delta-sigma ADC 300) and one feedback loop. A second order delta-sigma ADC may provide a higher signal to quantization noise ratio (SQNR) than a first order delta-sigma ADC operating at the same oversampling frequency. A second order delta-sigma ADC may provide the same signal to quantization noise ratio (SQNR) as a first order delta-sigma ADC when operated at a lower oversampling frequency than the first order delta-sigma ADC.

In operation, the voltage integrator 450 may be configured to integrate the voltage across the capacitor 110. The integrated output of the voltage integrator 450 may be converted to a digital value by the voltage quantizer 220 depending on whether the integrated output is greater than or less than a threshold value. The voltage DAC 444 may be configured to convert the digital output of the voltage quantizer 220 to an analog voltage, and the voltage adder 438 may be configured to add the analog voltage as negative feedback to the voltage of the capacitor 110.

The delta-sigma ADC 400 may need to add currents and add voltages (via the voltage adder 438) at the same node, i.e., at the output terminal 122 of the switch 120. This may make the delta-sigma ADC 400 shown in fig. 4 practically impractical.

Fig. 5 illustrates a diagram of a CMUT 100 (as represented by the circuit model of the CMUT 100 described with reference to fig. 1) electrically coupled to a delta-sigma ADC 500 according to some embodiments. The delta-sigma ADC 500 differs from the delta-sigma ADC 400 in that: the delta-sigma ADC 500 includes a first voltage integrator 558 and a second voltage integrator 562. The first voltage integrator 558 includes an input terminal 564 and an output terminal 566. Second voltage integrator 562 includes an input terminal 570 and an output terminal 568. Input terminal 564 of first voltage integrator 558 is electrically coupled to output terminal 122 of switch 120. The output terminal 566 of the first voltage integrator 558 is electrically coupled to the first input terminal 440 of the voltage adder 438. Input terminal 570 of second voltage integrator 562 is electrically coupled to output terminal 448 of voltage DAC 444. An output terminal 568 of the second voltage integrator 562 is electrically coupled to the second input terminal 456 of the voltage adder 438. As described above, in the delta-sigma ADC 400, the voltage adder 438 may be configured to add together the voltage on the capacitor 110 and the voltage from the voltage DAC 444, and the voltage integrator 450 may be configured to integrate the sum of the voltages from the voltage adder 438. In contrast, in the delta-sigma ADC 500, the first voltage integrator 558 integrates the voltage across the capacitor 110 and the second voltage integrator 562 integrates the voltage from the voltage DAC 444. The voltage adder 438 adds the output from the first voltage integrator 558 and the output from the second voltage integrator 562. Thus, the output from the voltage adder 438 in the delta-sigma ADC 500 may be equivalent to the output from the voltage integrator 450 in the delta-sigma ADC 400, and thus the input to the quantizer 220 in both the delta-sigma ADC 400 and the delta-sigma ADC 500 may be the same. However, because the delta-sigma ADC 500 does not require adding currents and adding voltages at the same node, the delta-sigma ADC 500 may be practically implemented.

Fig. 6 illustrates a diagram of a CMUT 100 (as represented by the circuit model of the CMUT 100 described with reference to fig. 1) electrically coupled to a delta-sigma ADC 600 according to some embodiments. The delta-sigma ADC 600 differs from the delta-sigma ADC 500 in that: the delta-sigma ADC 600 includes the second current DAC 686, the transconductance amplifier 680, and the capacitor 692, and does not include the first voltage integrator 558, the second voltage integrator 562, the voltage DAC 444, and the voltage adder 438. The second current DAC 686 includes an input terminal 688 and an output terminal 690. Transconductance amplifier 680 includes an input terminal 682 and an output terminal 684. Input terminal 682 of transconductance amplifier 680 is electrically coupled to output terminal 122 of switch 120. Output terminal 684 of transconductance amplifier 680 is electrically coupled to input terminal 228 of voltage quantizer 220. Capacitor 692 is electrically coupled between output terminal 684 of transconductance amplifier 680 and ground 116. The input terminal 688 of the second current DAC 686 is electrically coupled to the output terminal 232 of the voltage quantizer 220. Output terminal 690 of second current DAC 686 is electrically coupled to input terminal 228 of voltage quantizer 220.

In operation, transconductance amplifier 680 may be configured to convert the voltage of capacitor 110 into a current. This current output of the transconductance amplifier 680 may be summed with the current output of the second current DAC 686 due to a feedback loop. Capacitor 692 may integrate the sum of these currents. Thus, the transconductance amplifier 680 and the capacitor 692 may replace the first voltage integrator 558 in the delta-sigma ADC 500 because of the crossThe transconductance amplifier 680 and the capacitor 692 may integrate the voltage of the capacitor 110, the integration of the voltage of the capacitor 110 previously performed by the first voltage integrator 558. The second current DAC 686 and the capacitor 692 may replace the second voltage integrator 562 in the delta-sigma ADC 500. In particular, the current second current DAC 686 may be configured to convert D to_outConverted to an analog current signal and capacitor 692 may integrate the current. This is in contrast to the delta-sigma ADC 500, in which the voltage DAC 400 converts D into D in the delta-sigma ADC 500_outConverted to an analog voltage signal and the second voltage integrator 562 integrates the voltage. However, in the delta-sigma ADC 600, the second feedback loop (including the capacitor 692, the quantizer 220, the second current DAC 686) performs the same general function as the function of the second feedback loop (including the voltage adder 438, the quantizer 220, the voltage DAC 444, and the voltage integrator 562). That is, the function of these feedback loops may be to convert the digital output of the quantizer 220 to an analog signal (whether current or voltage) and then integrate the analog signal.

Fig. 7 illustrates a diagram of a CMUT 100 (as represented by the circuit model of the CMUT 100 described with reference to fig. 1) electrically coupled to a delta-sigma ADC 700 according to some embodiments. The delta-sigma ADC 700 differs from the delta-sigma ADC 500 in that: the delta-sigma ADC 700 includes a voltage buffer 794 and a voltage adder 701 and does not include a second current DAC 686. The voltage buffer 794 includes an input terminal 796 and an output terminal 798. The voltage adder 701 includes a first input terminal 703, a second input terminal 705, and an output terminal 707. The input terminal 796 of the voltage buffer 794 is electrically coupled to the output terminal 122 of the switch 120. The output terminal 798 of the voltage buffer 794 is electrically coupled to the first input terminal 703 of the voltage adder 701. An output terminal 684 of transconductance amplifier 680 is electrically coupled to a second input terminal 705 of voltage summer 701. An output terminal 707 of the voltage adder 701 is electrically coupled to the input terminal 228 of the voltage quantizer 220. The delta-sigma ADC 700 generally does not include the second feedback loop in the delta-sigma ADC 600 that includes the second current DAC 686, but as will be described below, the delta-sigma ADC 700 includes a feed-forward loop that the delta-sigma ADC 600 does not include.

The delta-sigma ADC 700 includes a feedback loop and a feed-forward loop. Capacitor 110, transconductance amplifier 680, capacitor 692, voltage adder 701, and voltage quantizer 220 are in the forward path of the feedback loop, and current DAC 222 is in the feedback path of the feedback loop. Capacitor 110, transconductance amplifier 680, capacitor 692, and voltage adder 701 are in the forward path of the feed forward loop. The voltage buffer 794 and the voltage adder 701 are in the feed-forward path of the feed-forward loop.

In operation, the voltage buffer 794 receives and buffers the voltage of the capacitor 110, and the voltage adder 701 adds the voltage of the capacitor 110 to the voltage of the capacitor 692. The feed-forward path may help improve the stability of the delta-sigma ADC 700. For example, the large voltage signal at the wait capacitor 110 may travel through the feed-forward path faster and contribute to the stability of the delta-sigma ADC 700 than if the large voltage signal traveled through the transconductance amplifier 680 and the capacitor 692. The feed forward loop may also help reduce the voltage swing at the capacitor 110. For example, a large voltage at the capacitor 110 may be fed to the voltage adder 701 through a feed forward loop, and the output of the voltage adder 701 (once processed by the voltage quantizer 220) may travel through a feedback loop, and the voltage at the capacitor 110 may be reduced by negative feedback at the output terminal 122 of the switch 120. Reducing the voltage swing may improve the linearity of the delta-sigma ADC 700.

It should be understood that in fig. 2-7, although capacitor 110 is shown near the delta-sigma ADC, capacitor 110 is physically part of CMUT 100, and functionally capacitor 110 may contribute to the operation of the delta-sigma ADC as an integrator.

Fig. 8 illustrates a diagram of the CMUT 100 electrically coupled to the delta-sigma ADC 800 and the delta-sigma ADC 800 electrically coupled to the filter 869 and the jitter generator 827, according to some embodiments. The delta-sigma ADC 800 includes a transconductance amplifier 809, a capacitor 816, a capacitor 819, a switch 821, a voltage quantizer 877, a first current DAC857, and a second current DAC 845. Transconductance amplifier 809 includes a positive input terminal 811, a negative input terminal 813, a positive output terminal 815, and a negative output terminal 817. Quantizer 877 includes a positive input terminal 833, a negative input terminal 835, a first reference voltage input terminal 831, a second reference voltage input terminal 837, a p output terminal 839, a z output terminal 841, and an n output terminal 843. The first current DAC857 includes a p-input terminal 863, a z-input terminal 865, an n-input terminal 867, a dither input terminal 861, and an output terminal 859. The second current DAC 845 includes a p-input terminal 855, a z-input terminal 853, an n-input terminal 851, a positive output terminal 849, and a negative output terminal 847. The filter 869 includes a p-input terminal 871, a z-input terminal 872, an n-input terminal 873, and an output terminal 879. The jitter generator 827 includes a jitter output terminal 875 and a z-input terminal 876.

Output terminal 122 of switch 120 is electrically coupled to a positive input terminal 811 of transconductance amplifier 809. The negative terminal 813 of transconductance amplifier 809 may be electrically coupled to a common mode voltage. The positive output terminal 815 of the transconductance amplifier 809 is electrically coupled to the positive input terminal 833 of the voltage quantizer 877. The negative output terminal 817 of the transconductance amplifier 809 is electrically coupled to the negative input terminal 835 of the transconductance amplifier 809. The capacitor 816 is electrically coupled between the positive output terminal 815 of the transconductance amplifier 809 and ground 116. Capacitor 819 is electrically coupled between the negative output terminal 817 of transconductance amplifier 809 and ground 116. Switch 821 is electrically coupled between positive output terminal 815 and negative output terminal 817 of transconductance amplifier 809.

The p-output terminal 839 of the voltage quantizer 877 is electrically coupled to the p-input terminal 863 of the first current DAC857, the p-input terminal 855 of the second current DAC 845, and the p-input terminal 871 of the filter 869. Z output terminal 841 of voltage quantizer 877 is electrically coupled to z input terminal 865 of first current DAC857 and z input terminal 853 of second current DAC 845. The n output terminal 843 of the voltage quantizer 877 is electrically coupled to the n input terminal 867 of the first current DAC857, the n input terminal 851 of the second current DAC 845, and the n input terminal 873 of the filter 869. The jitter output terminal 875 of the jitter generator 827 is electrically coupled to the jitter input terminal 861 of the first current DAC 857. The z input terminal 876 of the dither generator 827 is electrically coupled to the z output terminal 841 of the quantizer 877. An output terminal 859 of the first current DAC857 is electrically coupled to the output terminal 122 of the switch 120. The positive output terminal 849 of the second current DAC 845 is electrically coupled to the positive output terminal 815 of the transconductance amplifier 809. The negative output terminal 847 of the second current DAC 845 is electrically coupled to the negative output terminal 817 of the transconductance amplifier 809.

The overall architecture and operation of the delta-sigma ADC 800 may be similar to that of the delta-sigma ADC 600. Like the delta-sigma ADC 600, the delta-sigma ADC 800 is a second order delta-sigma ADC. Certain circuit elements of the delta-sigma ADC 800 may correspond to certain circuit elements of the delta-sigma ADC 600 because their overall circuit connectivity and operation may be similar to one another. Transconductance amplifier 809 may correspond to transconductance amplifier 680. The capacitor 816 and the capacitor 819 may correspond to the capacitor 692. The voltage quantizer 877 may correspond to the voltage quantizer 220. The first current DAC857 may correspond to the current DAC 222. Second current DAC 845 may correspond to second current DAC 686. The following description will describe the differences between the delta-sigma ADC 800 and the delta-sigma ADC 600.

The transconductance amplifier 809 is differential-ended and therefore has a positive output terminal 815 and a negative output terminal 817 in the delta-sigma ADC 800, while the transconductance amplifier 680 is single-ended and therefore has a single output terminal 684 in the delta-sigma ADC 600. In the delta-sigma ADC 600, a single capacitor 692 is electrically coupled to the output terminal 684 of the single-ended transconductance amplifier 680, whereas in the delta-sigma ADC 800, one capacitor 816 is electrically coupled to the positive output terminal 815 of the transconductance amplifier 809 and the other capacitor 819 is electrically coupled to the negative output terminal 817 of the transconductance amplifier. In the delta-sigma ADC 600, the single output terminal 690 of the second current DAC 686 is electrically coupled to the output terminal 684 of the single-ended transconductance amplifier 680, whereas in the delta-sigma ADC 800, the second current DAC 845 has two output terminals. Positive output terminal 849 of second current DAC 845 is electrically coupled to positive output terminal 815 of transconductance amplifier 809, and negative output terminal 847 of second current DAC 845 is electrically coupled to negative output terminal 817 of transconductance amplifier. When switch 821 is closed, switch 821 may cause the differential voltage across capacitor 816 and capacitor 819 to be zero by electrically shorting the voltages across

output terminals

815 and 817.

The voltage quantizer 220 of the delta-sigma ADC 600 may be configured to output one of two logic levels ("1" or "0") depending on whether the input voltage of the voltage quantizer 220 is higher or lower than a reference voltage, while the voltage quantizer 877 of the delta-sigma ADC 800 may be configured to output 1.5 bits. This means that the voltage quantizer 877 can be configured to output one of three logic levels. To output a logic level, referred to herein as p, voltage quantizer 877 may be configured to output a "1" on p output terminal 839 and a "0" on z output terminal 841 and n output terminal 843. To output a logic level, referred to herein as z, voltage quantizer 877 may be configured to output a "1" on z output terminal 841 and a "0" on p output terminal 839 and n output terminal 843. To output a logic level referred to herein as n, voltage quantizer 877 may be configured to output a "1" on n output terminal 843 and a "0" on p output terminal 839 and z output terminal 841. Thus, voltage quantizer 877 may output a "1" at a single time on only one of p-output terminal 839, z-output terminal 841, and n-output terminal 843. The voltage quantizer 877 may be configured to output a logic level p if the input voltage to the voltage quantizer 877 (i.e., the voltage between the positive input terminal 833 and the negative input terminal 835) is higher than the second reference voltage. The voltage quantizer 877 may be configured to output the logic level n if the input voltage to the voltage quantizer 877 is lower than a first reference voltage (where the first reference voltage is lower than a second reference voltage). The voltage quantizer 877 may be configured to output the logic level z if the input voltage to the voltage quantizer 877 is between the first reference voltage and the second reference voltage. The first reference voltage may be lower than a common mode voltage at the positive output terminal 815 and the negative output terminal 817 of the transconductance amplifier 809, and the second reference voltage may be higher than the common mode voltage. The current DAC 222 and the second current DAC 686 in the delta-sigma 600 may be configured to output one of two analog currents based on whether the output of the voltage quantizer 220 is "0" or "1", while the first current DAC857 and the second current DAC 845 in the delta-sigma 800 may be configured to output one of three analog currents based on which of the three logic levels the voltage quantizer 877 outputs. Using a 1.5-bit voltage quantizer 877 may help improve the signal-to-noise ratio of the delta-sigma ADC 800 and improve the noise performance of the delta-sigma ADC 800. In some embodiments, instead of using the 1.5 bit voltage quantizer 877, the first current DAC857, and the second current DAC 845, other quantizer resolutions (e.g., 1 bit, 2 bit, 3 bit, 4 bit, 5 bit, 6 bit, or 7 bit) may be used. Higher quantizer resolution may achieve a higher overall SQNR at the same oversampling frequency, or may achieve a lower oversampling frequency to achieve the same SQNR. The first reference voltage and the second reference voltage may be input to the first reference voltage input terminal 831 and the second reference voltage input terminal 837 of the voltage quantizer 877, respectively, for determining which logic level to output. The first reference voltage and the second reference voltage may be generated by, for example, a voltage regulator.

In operation, the filter 869 may be configured to decimate the digital output of the delta-sigma ADC 800 (i.e., the signals on the p-input terminal 871, the z-input terminal 872, and the n-input terminal 873) and output the decimated digital output on the output terminal 879. In practice, output terminal 879 may include three terminals, one for each of the p, z and n logic levels. In some implementations, the delta-sigma ADC 800 may apply (e.g., at the quantizer 877) the processed input current signal I_CMUTOversampling is performed and the filter 869 may decimate the sampled signal in order to improve the signal-to-noise ratio of the delta-sigma ADC 800. Oversampling can be performed at, for example, 400 MHz. The decimation performed by the filter 869 may be, for example, a quad decimation. In some embodiments, the filter 869 may be a cascaded integrator-comb filter (CIC). In some embodiments, the filter 869 may include only two of the p-input terminal 871, the z-input terminal 872, and the n-input terminal 873. Since only one of the signals on these terminals may be a "1" at a time, the signal on the third terminal may be determined from the signals on the other two terminals. Similarly, the output terminal 879 may actually include only two terminals.

The first current DAC857 may receive a dither signal from the dither generator 827 on a dither input terminal 861. The current generated by the CMUT is typically a DC current with occasional pulses. When signals, such as substantially constant signals, are input to the delta-sigma ADC 800, the signals may cause the filter 869 to lock to a fixed frequency (which may also be referred to as a "limit cycle"). The dither signal (i.e., the noise signal purposefully introduced into the input of the delta-sigma ADC) may help randomize the quantization error to prevent the filter 869 from being locked to a fixed frequency.

Although various circuit elements (e.g., capacitor 692, capacitor 816, and capacitor 819) are shown herein as being coupled to ground 116, in some implementations, these circuit elements may instead be coupled to another DC voltage.

Fig. 9 illustrates a diagram of a first current DAC857 and its coupling to a transconductance amplifier 809 according to some embodiments. The first current DAC857 includes a positive voltage rail 825, ground 116, a current source 983, a current source 904, a node 985, a node 993, a node 902, an output terminal 859, a first n-switch 987, a second n-switch 999, a first z-switch 989, a second z-switch 997, a first p-switch 991, a second p-switch 995, and a buffer 906. The buffer 906 may be considered a weak buffer because the current driving the buffer 906 may be much smaller (e.g., four times smaller) than the current driving the transconductance amplifier 809. Buffer 906 includes a negative input terminal 908, a positive input terminal 910, and an output terminal 912. The negative input terminal 908 is electrically coupled to the output terminal 912 of the buffer 906 to form a negative feedback loop. The output terminal 912 of the buffer 906 is electrically coupled to the node 993 of the first DAC 857. The positive input terminal 910 may be coupled to a reference voltage (e.g., half of the supply voltage of the buffer 906). A current source 983 is electrically coupled between the positive voltage rail 825 and a node 985. The current flowing from current source 983 and into node 985 will be referred to as I₁. Current source 904 is electrically coupled between node 902 and ground 116. The current flowing from node 902 into current source 904 is I₁. A first n-switch 987 is electrically coupled between node 985 and output terminal 859. Second n-switch 999 is electrically coupled between node 993 and node 902. First z-switch 989 is electrically coupled between node 985 and node 993. Second z-switch 997 is electrically coupled between node 993 and node 902. First p-switch 991 is electrically coupled between node 985 and node 993. The second p-switch 995 is electrically coupled between the output terminal 859 and the node 902. Node 993 is electrically coupled to the output of buffer 906. Output terminal 859 is electrically coupled to the positive input terminal 811 of transconductance amplifier 809. Flows out of an output terminal 859 of the first current DAC857 and entersThe current into the positive input terminal 811 of the transconductance amplifier 809 will be referred to as I_OUT1。

As described above, in operation, the voltage quantizer 877 may output a "1" at a single time to only one of the p-input terminal 863, the z-input terminal 865, and the n-input terminal 867 (not shown in fig. 9) of the first current DAC 857. A "1" on the p-input terminal 863 and a "0" on the z-input terminal 865 and the n-input terminal 867 may cause the first and second p-

switches

991 and 995 to close and the remaining switches to open. Current I₁May flow from the positive input terminal 811 of transconductance amplifier 809 into output terminal 859, through node 902, through current source 904, and to ground 116. Thus, I_OUT1May be-I₁. Current I₁Can flow from the positive voltage rail 825 through the current source 983, through the node 985, through the node 993, and into the output of the buffer 906.

A "1" on the z-input terminal 865 and a "0" on the p-input terminal 863 and the n-input terminal 867 can cause the first z-switch 989 and the second z-switch 997 to close and the remaining switches to open. Current I₁Can flow from the positive voltage rail 825 through current source 983, through node 985, through node 902, through current source 904, and to ground 116. The mismatch between the currents supplied by current source 983 and current source 904 may be pulled (sourced) or sunk (sink) through buffer 906. Output terminal 859 may be disconnected from current source 983 and current source 904. Thus, I_OUT1May be 0.

A "1" on the n-input terminal 867 and a "0" on the p-input terminal 863 and the z-input terminal 865 can close the first n-switch 987 and the second n-switch 999 and open the remaining switches. Current I₁Can flow from the positive voltage rail 825, through the current source 983, through the node 985, and out the output terminal 859. Thus, I_OUT1May be I₁. Current I₁May flow from the output of buffer 906, through node 993, through node 902, through current source 904, and to ground 116.

In summary, when the voltage quantizer 877 outputs the p-state to the first current DAC, I_OUT1May be-I₁. When the voltage quantizer 877 is turned toWhen the first current DAC outputs z-state, I_OUT1May be 0. When the voltage quantizer 877 outputs the n-state to the first current DAC, I_OUT1May be I₁. Thus, the first current DAC857 may output different analog currents I according to the digital input to the first current DAC857_OUT1. In some embodiments, I₁May be programmable so that it may be compatible with I_CMUTThe ranges of (a) and (b) match. In some embodiments, I₁May be on the order of a few tenths of a microampere to microampere (e.g., when I_CMUTBetween 4nA and 7uA, I₁Can be programmed to 0.5uA to 8 uA).

Fig. 10 illustrates a diagram of a second current DAC 845 and its coupling to a transconductance amplifier 809, a capacitor 816, and a capacitor 819, according to some embodiments. The second current DAC 845 includes a positive voltage rail 825, a ground 116, a current source 1083, a current source 1004, a node 1085, a node 1012, a node 1002, a positive output terminal 849, a negative output terminal 847, a first n-switch 1087, a second n-switch 1099, a first z-switch 1089, a second z-switch 1097, a first p-switch 1091, a second p-switch 1095, and a buffer 1006. The buffer 1006 may be considered a weak buffer because the current driving the buffer 1006 may be much smaller (e.g., four times smaller) than the current driving the transconductance amplifier 809. The buffer 1006 includes a negative input terminal 1008, a positive input terminal 1010, and an output terminal 1013. The negative input terminal 1008 is electrically coupled to the output terminal 1013 of the buffer 1006 to form a negative feedback loop. Output terminal 1003 of buffer 1006 is electrically coupled to node 1012 of second current DAC 845. The positive input terminal 1010 may be coupled to a reference voltage (e.g., half of the supply voltage of the buffer 1006). A current source 1083 is electrically coupled between the positive voltage rail 825 and the node 1085. The current flowing from current source 1083 and into node 1085 will be referred to as I₂. Current source 1004 is electrically coupled between node 1002 and ground 116. The current flowing from node 1002 into current source 1004 is I₂. First n-switch 1087 is electrically coupled between node 1085 and positive output terminal 849. The second n-switch 1099 is electrically coupled between the negative output terminal 847 and the node 1002. The first z-switch 1089 is electrically coupled between node 1085 and node 1012. The second z-switch 1097 is electrically coupled to the nodePoint 1012 and node 1002. The first p-switch 1091 is electrically coupled between the node 1085 and the negative output terminal 847. The second p-switch is electrically coupled between the positive output terminal 849 and the node 1002. Node 1012 is electrically coupled to the output of buffer 1006. The positive output terminal 849 of the second current DAC 845 is electrically coupled to the positive output terminal 815 of the transconductance amplifier 809. The current flowing out of the positive output terminal 849 of the second current DAC 845 to the positive output terminal 815 of the transconductance amplifier 809 will be referred to as I_OUT2P. The negative output terminal 847 of the second current DAC 845 is electrically coupled to the negative output terminal 817 of the transconductance amplifier 809. The current flowing out of the negative output terminal 847 of the second current DAC 845 to the negative output terminal 817 of the transconductance amplifier 809 will be referred to as I_OUT2N。

As described above, in operation, the voltage quantizer 877 may output a "1" on only one of the p, z, and

n output terminals

839, 841, and 843 of the voltage quantizer 877 to the p, z, and

n input terminals

855, 853, and 851, respectively (not shown in fig. 10), of the second current DAC857 at a single time. A "1" on the p-input terminal 855 and a "0" on the z-input terminal 853 and the n-input terminal 851 may close the first p-switch 1091 and the second p-switch 1095 and open the remaining switches. Current I₂Can flow from the positive voltage rail 825, through the current source 1083, through the node 1085, and out the negative output terminal 847. Thus, I_OUT2NMay be I₂. Current I₂Can flow from the positive output terminal 815 of the transconductance amplifier 809 into the positive output terminal 849 of the second current DAC 845, through the node 1002, through the current source 1004, and to ground. Thus, I_OUT2pMay be-I₂。

A "1" on the z-input terminal 865 and a "0" on the p-input terminal 863 and the n-input terminal 867 can cause the first z-switch 1089 and the second z-switch 1097 to close and the remaining switches to open. Current I₂Can flow from the positive voltage rail 825 through the current source 1083, through the node 1012, through the node 1002, through the current source 1004, and to ground 116. The current mismatch between current source 1083 and current source 1004 may be pulled (sourced) or sunk (sink) through buffer 1006. The positive output terminal 849 and the negative output terminal 847 mayDisconnected from current source 1083 and current source 1004. Thus, I_OUT2NAnd I_OUT2PMay be 0.

A "1" on the n-input terminal 867 and a "0" on the p-input terminal 863 and the z-input terminal 865 can close the first n-switch 1087 and the second n-switch 1099 and open the remaining switches. Current I₂Can flow from the positive voltage rail 825, through the current source 1083, through the node 1085, and out the positive output terminal 849. Thus, I_OUT2PMay be I₂. Current I₂May flow from the negative output terminal 817 of the transconductance amplifier 809 and/or from ground 116, through capacitor 819, into the negative output terminal 847 of the second current DAC 845, through node 1002, through current source 1004, and to ground 116. Thus, I_OUT2NMay be-I₂。

In summary, when the voltage quantizer 877 outputs the p-state to the second current DAC 845, I_OUT2PMay be-I₂And I_OUT2NMay be I₂. When the voltage quantizer 877 outputs the z-state to the second current DAC 845, I_OUT2PAnd I_OUT2NMay be 0. When the voltage quantizer 877 outputs the n-state to the second current DAC 845, I_OUT2PMay be I₂And I_OUT2NMay be-I₂. Thus, the second current DAC 845 may output an analog current I according to a digital input to the second current DAC 845_OUT2PAnd I_OUT2NDifferent combinations of (a). In some embodiments, I₂May be programmable so that it can match the output current range of transconductance amplifier 809. In some embodiments, I₂May be on the order of a microampere to tens of microamperes (e.g., transconductance, I, of 2mS to 8mS for transconductance amplifier 809₂Can be programmed to 1.5 mua to 24 mua).

Fig. 10 also shows a Common Mode Feedback (CMFB)1014 that accepts as inputs the voltages of the positive output terminal 815 and the negative output terminal 817 of the transconductance amplifier 809 and outputs a common mode feedback signal to the common mode feedback terminal 1014 of the transconductance amplifier 809. The common mode feedback signal can help stabilize the output common mode level in the transconductance amplifier 809. Because transconductance amplifier 809 is an open-loop differential amplifier, the output common-mode level may not be well defined without common-mode feedback.

FIG. 11 illustrates an example circuit implementation of a current source 1083 according to some embodiments. The implementation includes: a first p-channel metal oxide semiconductor field effect transistor (pMOS)1114 and a second pMOS 1116 coupled between a positive voltage rail 825 and a node 1085 in a cascode configuration. In addition to node 1085 being node 985, the implementation of fig. 11 may also be used for current source 983.

Fig. 12 illustrates an example circuit implementation of a current source 1004 according to some embodiments. The implementation includes a first n-channel metal oxide semiconductor field effect transistor (nMOS)1214 and a second nMOS 1216 extending in a cascode configuration between node 1002 and ground 116. The implementation of fig. 12 may also be used for current source 904, in addition to node 1002 being node 902.

FIG. 13 illustrates an example diagram of a jitter generator 827 according to some embodiments. The jitter generator 827 includes a pseudo-random bit stream generator 1318, an and gate 1324, an and gate 1326, a switch 1328, a switch 1330, a current source 1332, a current source 1334, a positive voltage rail 825, a ground 116, a z-input terminal 876, and an output jitter terminal 875. The pseudorandom bit stream generator 1318 may be configured to generate pseudorandom bit streams having varying degrees of dither noise density. The pseudo-random bit stream generator 1318 may include a Linear Feedback Shift Register (LFSR) and a sequence of logic gates. The LFSR may be configured to generate pseudo-random bits. The pseudo-random bit sequence may be an input to a sequence of logic gates, which may be configured to process individual bits of the pseudo-random bit sequence over time to generate pairs of pseudo-random bit streams having different degrees of dither noise density (e.g., different densities of "1"). A control signal (not shown in the figure) may select a bit stream pair having a particular dither noise density and output the bit stream pair at the "up" and "down" terminals of the pseudo-random bit stream generator 1318. The pair of pseudo-random bit streams output by the pseudo-random bit stream generator 1318 are input to the and gate 1324 and the and gate 1326. The and gate 1324 and the and gate 1326 may be configured to be at the current of the input pseudo random bit streamWhere the bit is "1" and the quantizer 877 outputs the z logic state (i.e., the signal at the z input terminal 876 is "1"), a "1" is output (and, as will be described below, causes a dither current to be generated). When the current generated by CMUT 100 is close to 0 (which is the case where dithering may be required), quantizer 877 is likely to output a z logic state. When the and gate 1324 outputs "1", the switch 1328 is closed, and when the and gate 1326 outputs "1", the switch 1330 is closed. When switch 1328 is closed, current I₃Can flow from the positive voltage rail 825, through the current source 1332, and into the output dither terminal 875. When switch 1330 is closed, current I₃May flow from the output dither terminal 875 through the current source 1334 and to ground 116. Thus, the current I flowing out of the output jitter (diter) terminal 875_DITHERMay be I₃0, or-I₃This ultimately depends on the pseudo-random bit stream generated by the pseudo-random bit stream generator 1318. Thus, I_DITHERMay be similar to noise. I is₃May be on the order of a few hundredths of microamps (e.g., 0.05 uA).

Figure 14 illustrates an example diagram of an ultrasound device including CMUTs 1402, switches 1404, ADCs 1405, filters 1406, and digital beamformer 1408 according to some embodiments. Each of the CMUTs 1402 (which may each correspond to a CMUT 100) is directly coupled to one of the ADCs 1406 (which may each correspond to any of the delta-sigma ADCs described herein) through one of the switches 1404 (each of which may correspond to a switch 120). Each of the ADCs 1406 is electrically coupled to one of the filters 1406 (each of which may correspond to the filter 869). The output of the filter 1406 is input to a digital beamformer 1408 for beamforming. The filter 1406 may be a cascaded integrator-comb (CIC) filter. Figure 14 shows the digitization of each element, as each CMUT in CMUTs 1402 is electrically coupled to a dedicated ADC in ADCs 1406 (i.e., an ADC that is not electrically coupled (by one of switches 1404) to any other CMUT in CMUTs 1402). As described above, digital beamforming may be enabled by the digitization of each element, and may provide higher SNR, higher sampling resolution, greater flexibility in the delay patterns achieved by the digital beamformer 1408, and greater flexibility in grouping the ultrasound transducers for processing by the digital beamformer 1408 than analog beamforming may provide. All or part of the ultrasound system shown in figure 14 may be monolithically integrated on a single substrate. A single substrate may include 100 to 20,000 CMUTs (e.g., 100 to 1,000 CMUTs 1402, 1,000 to 10,000 CMUTs 1402, or 10,000 to 20,000 CMUTs 1402), each electrically coupled to a dedicated one of the ADCs 1406. The number of CMUTs used may depend on the imaging mode and image quality requirements of the ultrasound device.

Various aspects of the present disclosure may be used alone, in combination, or in a variety of arrangements not specifically discussed in the embodiments described in the foregoing and is therefore not limited in its application to the details and arrangement of components set forth in the foregoing description or illustrated in the drawings. For example, aspects described in one embodiment may be combined in any manner with aspects described in other embodiments.

The indefinite articles "a" and "an" as used herein in the specification and in the claims are to be understood as meaning "at least one" unless clearly indicated to the contrary.

The phrase "and/or" as used herein in the specification and in the claims should be understood to mean "either or both" of the elements so combined, i.e., elements that are present in combination in some cases and separately in other cases. Multiple elements listed with "and/or" should be interpreted in the same manner, i.e., "one or more" of the elements so combined. In addition to the elements specifically identified by the "and/or" clause, there may optionally be other elements, whether related or unrelated to those specifically identified elements. Thus, as a non-limiting example, when used in conjunction with open-ended language such as "including," reference to "a and/or B" may be: in one embodiment, reference is made to a only (optionally including elements other than B); in another embodiment, reference is made to B only (optionally including elements other than a); in yet another embodiment, reference is made to both a and B (optionally including other elements); and the like.

As used herein in the specification and in the claims, the phrase "at least one" referring to a list of one or more elements should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each element specifically listed in the list of elements, and not excluding any combination of elements in the list of elements. This definition also allows: elements other than the elements specifically identified within the list of elements referred to by the phrase "at least one" may optionally be present, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, "at least one of a and B" (or, equivalently, "at least one of a or B," or, equivalently, "at least one of a and/or B") may refer, in one embodiment, to at least one a (optionally including more than one a) without B (and optionally including elements other than B); in another embodiment, at least one B (optionally including more than one B) may be referred to without a (and optionally including elements other than a); in yet another embodiment, at least one a (optionally including more than one a) and at least one B (optionally including more than one B) (and optionally including other elements) may be referred to; and the like.

Use of ordinal terms such as "first," "second," "third," etc., in the claims to modify a claim element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a certain name from another element having a same name (but for use of the ordinal term) to distinguish the claim elements.

In some embodiments, the terms "about" and "approximately" may be used to mean within ± 20% of a target value; in some embodiments, the terms "about" and "approximately" may be used to mean within ± 10% of a target value; in some embodiments, the terms "about" and "approximately" may be used to mean within ± 5% of a target value; however, in some embodiments, the terms "about" and "approximately" may be used to mean within ± 2% of the target value. The terms "about" and "approximately" may include the target value.

Also, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of "including," "comprising," or "having," "containing," "involving," and variations thereof herein, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items.

Having thus described several aspects of at least one embodiment, it is to be appreciated various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be objects of the present disclosure. Accordingly, the foregoing description and drawings are by way of example only.

Claims

1. An apparatus, comprising:

a Capacitive Micromachined Ultrasonic Transducer (CMUT) electrically coupled directly to a delta-sigma analog-to-digital converter (ADC).

2. The apparatus of claim 1, wherein the apparatus comprises 100 to 1,000 CMUTs and 100 to 1,000 delta-sigma ADCs, each of the CMUTs being electrically coupled directly to one of the delta-sigma ADCs.

3. The apparatus of claim 1, wherein the apparatus comprises 1,000 to 10,000 CMUTs and 1,000 to 10,000 delta-sigma ADCs, each of the CMUTs being electrically coupled directly to one of the delta-sigma ADCs.

4. The apparatus of claim 1, wherein the apparatus comprises 10,000 to 20,000 CMUTs and 10,000 to 20,000 delta-sigma ADCs, each of the CMUTs being electrically coupled directly to one of the delta-sigma ADCs.

5. The apparatus of claim 1, wherein the CMUT and the delta-sigma ADC are monolithically integrated on a single substrate.

6. The apparatus of claim 5, further comprising a filter and a jitter generator electrically coupled to the CMUT and monolithically integrated on the single substrate, wherein the jitter generator is configured to output a jitter output having a selectable jitter noise density.

7. The apparatus of claim 1, wherein the delta-sigma ADC does not have a different integrator than the CMUT.

8. The apparatus of claim 1, wherein an internal capacitance of the CMUT acts as an integrator for the delta-sigma ADC.

9. An apparatus, comprising:

a Capacitive Micromachined Ultrasonic Transducer (CMUT) electrically coupled to a delta-sigma analog-to-digital converter (ADC), wherein the apparatus is free of an amplifier or multiplexer between the CMUT and the delta-sigma ADC.

10. The apparatus of claim 9, wherein the apparatus comprises 100 to 1,000 CMUTs and 100 to 1,000 delta-sigma ADCs, each of the CMUTs being electrically coupled directly to one of the delta-sigma ADCs.

11. The apparatus of claim 9, wherein the apparatus comprises 1,000 to 10,000 CMUTs and 1,000 to 10,000 delta-sigma ADCs, each of the CMUTs being electrically coupled directly to one of the delta-sigma ADCs.

12. The apparatus of claim 9, wherein the apparatus comprises 10,000 to 20,000 CMUTs and 10,000 to 20,000 delta-sigma ADCs, each of the CMUTs being electrically coupled directly to one of the delta-sigma ADCs.

13. The apparatus of claim 9, wherein the CMUT and the sigma-delta ADC are monolithically integrated on a single substrate.

14. The apparatus of claim 9, wherein the delta-sigma ADC does not have a different integrator than the CMUT.

15. The apparatus of claim 9, wherein an internal capacitance of the CMUT acts as an integrator for the delta-sigma ADC.

16. An apparatus, comprising:

100 to 20,000 Capacitive Micromachined Ultrasonic Transducers (CMUTs); and

one analog-to-digital converter (ADC) dedicated to each of the CMUTs.

17. The apparatus of claim 16, wherein the apparatus comprises 100 to 1,000 CMUTs.

18. The apparatus of claim 16, wherein the apparatus comprises 1,000 to 10,000 CMUTs.

19. The apparatus of claim 16, wherein the apparatus comprises 10,000 to 20,000 CMUTs.

20. The apparatus of claim 16, wherein the CMUT and the ADC are monolithically integrated on a single substrate.