CN112331116A - Liquid crystal panel and liquid crystal panel array substrate row driving circuit detection method - Google Patents
Liquid crystal panel and liquid crystal panel array substrate row driving circuit detection method Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 123
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 59
- 238000001514 detection method Methods 0.000 title abstract description 18
- 230000005669 field effect Effects 0.000 claims description 68
- 238000012360 testing method Methods 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 6
- 239000010408 film Substances 0.000 description 8
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0281—Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure
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Abstract
The application discloses LCD panel and LCD panel array substrate line drive circuit detection method, this LCD panel have effective display area and first array substrate line drive circuit and second array substrate line drive circuit, and effective display area is provided with many scanning lines, and first array substrate line drive circuit corresponds many the scanning line is equipped with a plurality of first outputs, and second array substrate line drive circuit corresponds many the scanning line is equipped with a plurality of second outputs, and LCD panel still includes: the first switch devices are correspondingly and electrically connected between the first output end and the scanning line; the second switching devices are correspondingly and electrically connected between the second output ends and the scanning lines; and a conduction control module. The array substrate row driving circuit in the liquid crystal panel driven by the double-end array substrate row driving circuit is used for detecting the fault of the array substrate row driving circuit, so that the array substrate row driving circuit with the fault can be timely detected, replaced or maintained.
Description
Technical Field
The application relates to the field of displays, in particular to a liquid crystal panel and a detection method for a liquid crystal panel array substrate row driving circuit.
Background
The current technology architecture of the liquid crystal panel is divided into two types, namely, SOC (System on chip), driving scan line and array substrate line driving (Gate driver). In view of product requirements, the smaller frame is desirable, so that compared with the SOC design, the array substrate row driving has a smaller boundary width, so that the gate driver chip can be omitted, and the cost can be reduced.
The prior liquid crystal panel driven by the double-end array substrate row driving circuit. If the array substrate row driving circuit on one side has a problem, the array substrate row driving circuit on the other side can continuously output voltage to the scanning lines of the liquid crystal panel so as to drive the thin film transistors in the liquid crystal panel to be switched on or switched off. Therefore, when the row driving circuit of the array substrate on one side of the liquid crystal panel fails, we do not know which row driving circuit of the array substrate on the other side fails. Therefore, even if the row driving circuit of the array substrate on one side breaks down, the failure cannot be detected and replaced or maintained in time.
Disclosure of Invention
The main purpose of the present application is to provide a liquid crystal panel and a method for detecting a row driving circuit of an array substrate of a liquid crystal panel, which aim to detect a fault of the row driving circuit of the array substrate in the liquid crystal panel driven by the row driving circuit of the double-ended array substrate, so as to realize timely detection, replacement or maintenance of the faulty row driving circuit of the array substrate.
In order to achieve the above object, the present application provides a liquid crystal display panel, its characterized in that, this liquid crystal display panel has the effective display area and locates respectively the first array base plate row drive circuit and the second array base plate row drive circuit of effective display area both sides, the effective display area is provided with many scanning lines, first array base plate row drive circuit corresponds many the scanning line is equipped with a plurality of first outputs, second array base plate row drive circuit corresponds many the scanning line is equipped with a plurality of second outputs, liquid crystal display panel still includes:
a plurality of first switching devices, each of which is electrically connected between the first output terminal and the scan line;
a plurality of second switching devices, each of which is electrically connected between the second output terminal and the scan line; and
and the conduction control module is provided with a first enabling end and a second enabling end which enable the first array substrate row driving circuit and the second array substrate row driving circuit to be alternately and electrically conducted with the scanning lines.
In some embodiments, the first enable terminal is connected to the control terminals of the first switching devices, the second enable terminal is connected to the control terminals of the second switching devices, and the output levels of the first enable terminal and the second enable terminal are opposite.
In some embodiments, the first switching device is a first field effect transistor, the control terminal of the first switching device is the gate of the first field effect transistor, the source of the first field effect transistor is connected to the first output terminal, and the drain of the first field effect transistor is connected to the scan line;
the second switching device is a second field effect transistor, the control end of the second switching device is a grid electrode of the second field effect transistor, the source electrode of the second field effect transistor is connected with the second output end, and the drain electrode of the second field effect transistor is connected with the scanning line.
In some embodiments, the first switching device is a first triode, the control terminal of the first switching device is the base of the first triode, the emitter of the first triode is connected to the first output terminal, and the collector of the first triode is connected to the scan line;
the second switching device is a second triode, the control end of the second switching device is a grid electrode of the second triode, the emitting electrode of the second triode is connected with the second output end, and the collecting electrode of the second triode is connected with the scanning line.
In some embodiments, the conduction control module is a chip on film, and the first enable terminal and the second enable terminal are output terminals of the chip on film.
In some embodiments, the conduction control module includes a signal source and an inverter circuit, the inverter circuit having an input terminal and a third output terminal, the signal source being connected to the first enable terminal and the input terminal, respectively, and the third output terminal being connected to the second enable terminal.
In some embodiments, the inverter circuit includes an N-channel fet, a P-channel fet, and a voltage source, a gate of the N-channel fet is connected to a gate of the P-channel fet to form the input terminal, a source of the N-channel fet is connected to a source of the P-channel fet to form the third output terminal, a drain of the N-channel fet is grounded, and a drain of the P-channel fet is connected to the voltage source.
In some embodiments, each of the first switching devices and each of the second switching devices are respectively connected with a voltage test pin.
This application still provides a liquid crystal display panel, and this liquid crystal display panel has the effective display area and locates respectively the first array base plate row drive circuit and the second array base plate row drive circuit of effective display area both sides, the effective display area is provided with many scanning lines, first array base plate row drive circuit corresponds many the scanning line is equipped with a plurality of first outputs, second array base plate row drive circuit corresponds many the scanning line is equipped with a plurality of second outputs, liquid crystal display panel still includes:
a plurality of first switching devices, each of which is electrically connected between the first output terminal and the scan line;
a plurality of second switching devices, each of which is electrically connected between the second output terminal and the scan line; and
the conduction control module is provided with a first enabling end and a second enabling end which enable the first array substrate row driving circuit and the second array substrate row driving circuit to be alternately and electrically conducted with the scanning lines;
the first enabling end is connected with the control ends of the first switching devices respectively, the second enabling end is connected with the control ends of the second switching devices respectively, and the output levels of the first enabling end and the second enabling end are opposite;
the first switching device is a first field effect transistor, the control end of the first switching device is the grid electrode of the first field effect transistor, the source electrode of the first field effect transistor is connected with the first output end, and the drain electrode of the first field effect transistor is connected with the scanning line;
the second switching device is a second field effect transistor, the control end of the second switching device is a grid electrode of the second field effect transistor, the source electrode of the second field effect transistor is connected with the second output end, and the drain electrode of the second field effect transistor is connected with the scanning line;
the conduction control module is made of a chip on film, and the first enabling end and the second enabling end are output ends of the chip on film.
The application also provides a detection method of the liquid crystal panel array substrate row driving circuit, which is suitable for the liquid crystal panel, and the detection method of the liquid crystal panel array substrate row driving circuit comprises the following steps:
the first enabling end outputs high level, the second enabling end outputs low level, and whether the first array substrate row driving circuit works normally is tested;
the first enabling end outputs low level, the second enabling end outputs high level, and whether the second array substrate row driving circuit works normally or not is tested.
This application is through setting up first enable end and second enable end make first array base plate row drive circuit with second array base plate row drive circuit in turn with the scanning line electrical property switches on, for example works as first array base plate row drive circuit with the scanning line electrical property switches on, and first array base plate row drive circuit with when the scanning line electrical property is turn off, detect whether first array base plate row drive circuit normally works in order to drive effective display area normal display to detect array base plate row drive circuit's among the double-ended array base plate row drive circuit driven liquid crystal display panel trouble, in time detect and change or maintain with the array base plate row drive circuit who realizes the trouble.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a schematic diagram of a typical LCD panel driven by a conventional double-ended array substrate row driving circuit;
FIG. 2 is a schematic structural diagram of an embodiment of a liquid crystal panel of the present application;
fig. 3 is a schematic structural diagram of an embodiment of a conduction control module according to the present application;
fig. 4 is a flowchart illustrating an embodiment of a method for detecting a row driving circuit of an array substrate of a liquid crystal panel according to the present invention.
The reference numbers illustrate:
the implementation, functional features and advantages of the objectives of the present application will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that all the directional indications (such as up, down, left, right, front, and rear … …) in the embodiment of the present application are only used to explain the relative position relationship between the components, the movement situation, and the like in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indication is changed accordingly.
In this application, unless expressly stated or limited otherwise, the terms "connected," "secured," and the like are to be construed broadly, and for example, "secured" may be a fixed connection, a removable connection, or an integral part; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In addition, descriptions in this application as to "first", "second", etc. are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit to the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present application.
Referring to fig. 1, fig. 1 shows a typical liquid crystal panel 101 driven by a conventional two-terminal array substrate row driving circuit. The left array substrate row driver circuit (i.e., the left GOA circuit in fig. 1) and the right array substrate row driver circuit (i.e., the right GOA circuit in fig. 1) simultaneously drive the thin film transistors connected by the scan lines in the active display area. The left array substrate row driving circuit and the right array substrate row driving circuit simultaneously drive the row driving circuit of the single-side array substrate, and the driving effect is better than that of the row driving circuit of the single-side array substrate. However, it is rare to perfect, and the liquid crystal panel driven by the double-end array substrate row driving circuit brings new problems. If the array substrate row driving circuit on one side has a problem, the array substrate row driving circuit on the other side can continuously output voltage to the scanning lines of the liquid crystal panel so as to drive the thin film transistors in the liquid crystal panel to be switched on or switched off. Therefore, when the row driving circuit of the array substrate on one side of the liquid crystal panel fails, we do not know which row driving circuit of the array substrate on the other side fails. Therefore, even if the row driving circuit of the array substrate on one side breaks down, the failure cannot be detected and replaced or maintained in time.
Therefore, the detection of the fault of the array substrate row driving circuit in the liquid crystal panel driven by the double-end array substrate row driving circuit is needed to realize the timely detection, replacement or maintenance of the faulty array substrate row driving circuit. In view of this, the present application is illustrated below by means of several examples.
Example 1
Referring to fig. 2, in an embodiment of the present application, a liquid crystal panel 100 includes an effective display area 10, and a first array substrate row driving circuit 20 (shown as a first GOA circuit 20 in fig. 2) and a second array substrate row driving circuit 30 (shown as a second GOA circuit 30 in fig. 2) respectively disposed at two sides of the effective display area 10, where the effective display area 10 is provided with a plurality of scanning lines 12 (shown as g1, g2, g........, gn-1, gn in fig. 2), the first array substrate row driving circuit 20 is provided with a plurality of first output ends corresponding to the plurality of scanning lines 12, and the second array substrate row driving circuit 30 is provided with a plurality of second output ends corresponding to the plurality of scanning lines 12.
The first array substrate row driving circuit 20 is provided with a plurality of first output ends corresponding to the plurality of scanning lines 12, that is, the first array substrate row driving circuit 20 has the first output ends with the same number as the scanning lines 12, so that the voltage output by the first output ends passes through the scanning lines 12 to turn on or off the thin film transistors in the effective display area 10; similarly, the second array substrate row driving circuit 30 is provided with a plurality of second output ends corresponding to the plurality of scanning lines 12, that is, the second array substrate row driving circuit 30 has the second output ends with the same number as the scanning lines 12, so that the voltage output by the second output ends passes through the scanning lines 12 to turn on or off the thin film transistors in the effective display area 10.
The liquid crystal panel further includes: a plurality of first switching devices 40, a plurality of second switching devices 50, and a conduction control module 60.
Each of the first switch devices 40 is correspondingly electrically connected between the first output terminal and the scan line 12. As can be seen from the foregoing description, the first output terminals correspond to the scan lines 12 one to one. Therefore, each of the first switching devices 40 is electrically connected between the first output terminal and the scan line 12 correspondingly, which means that the number of the first switching devices 40 is equal to the number of the first output terminals and the number of the scan lines 12 correspondingly, and the first switching devices are used for connecting the first output terminals and the scan lines 12 in a one-to-one correspondence.
Each of the second switch devices 50 is correspondingly electrically connected between the second output terminal and the scan line 12. Similarly, as can be seen from the foregoing description, the first output terminals correspond to the scan lines 12 in a one-to-one relationship. Therefore, each of the second switching devices 50 is electrically connected between the second output terminal and the scan line 12 correspondingly, which means that the number of the second switching devices 50 is equal to the number of the second output terminals and the scan line 12 correspondingly, and the second switching devices are used for connecting the one-to-one corresponding second output terminals and the scan lines 12.
A conduction control module 60, wherein the conduction control module 60 has a first enable terminal 61 and a second enable terminal 62 for making the first array substrate row driving circuit 20 and the second array substrate row driving circuit 30 alternately electrically conducted with the scan line 12.
By arranging the first enable terminal 61 and the second enable terminal 62, the first array substrate row driving circuit 20 and the second array substrate row driving circuit 30 are alternately electrically conducted with the scanning line 12, for example, when the first array substrate row driving circuit 20 is electrically conducted with the scanning line 12, and the first array substrate row driving circuit 20 is electrically disconnected with the scanning line 12, it is detected whether the first array substrate row driving circuit 20 normally works to drive the effective display area 10 to normally display, so as to detect a fault of the array substrate row driving circuit in the liquid crystal panel driven by the double-end array substrate row driving circuit, so as to implement timely detection, replacement or maintenance of the faulty array substrate row driving circuit.
Specifically, in some embodiments, the first enable terminal 61 is connected to the control terminals of the first switching devices 40, the second enable terminal 62 is connected to the control terminals of the second switching devices 50, and the output levels of the first enable terminal 61 and the second enable terminal 62 are opposite. The on-off states of the first switching device 40 and the second switching device 50 are affected by the level states of the corresponding control terminals, and by setting the output levels of the first enable terminal 61 and the second enable terminal 62 to be opposite, the on-off states of the first switching device 40 and the second switching device 50 are opposite.
For example, when the first enable terminal 61 is at a high level and the second enable terminal 62 is at a low level, the first switching device 40 on the side of the effective display area 10 is turned on, and each first output terminal of the first array substrate row driving circuit 20 outputs a voltage to the thin film transistor connected to the scan line 12, so that the effective display area 10 displays normally; and the first switching device 40 on the other side of the effective display area 10 is turned off, so that each second output terminal of the second array substrate row driving circuit 30 cannot output a voltage to the thin film transistor connected to the scan line 12. At this time, whether the first array substrate row driving circuit 20 malfunctions or not can be tested by detecting whether the effective display area 10 displays normally or not. On the contrary, when the first enable terminal 61 is at a low level and the second enable terminal 62 is at a high level, the second switching device 50 located at the other side of the effective display area 10 is turned on, and at this time, whether the second array substrate row driving circuit 30 fails or not can be tested by detecting whether the effective display area 10 displays normally or not.
By setting the output levels of the first enable end 61 and the second enable end 62 to be opposite, only one side of the first array substrate row driving circuit 20 or the second array substrate row driving circuit 30 is electrically communicated with the scanning line 12 at the same time, and at this time, the detection of the first array substrate row driving circuit 20 or the second array substrate row driving circuit 30 which is conducted on one side is realized; when the output levels of the first enabling end 61 and the second enabling end 62 are turned over again, the first array substrate row driving circuit 20 or the second array substrate row driving circuit 30 on the other side are detected, and through the detection of the first array substrate row driving circuit 20 or the second array substrate row driving circuit 30 on one side respectively, the fault of the array substrate row driving circuit in the liquid crystal panel driven by the double-end array substrate row driving circuit can be detected, so that the array substrate row driving circuit with the fault can be timely detected, replaced or maintained, and the fault detection efficiency is improved.
Further, the first switching device 40 may be configured as a first field effect transistor, a control terminal of the first switching device 40 is a gate of the first field effect transistor, a source of the first field effect transistor is connected to the first output terminal, and a drain of the first field effect transistor is connected to the scan line 12;
the second switching device 50 may be a second field effect transistor, a control terminal of the second switching device 50 is a gate of the second field effect transistor, a source of the second field effect transistor is connected to the second output terminal, and a drain of the second field effect transistor is connected to the scan line 12.
It should be noted that, the first fet and the second fet may be N-channel enhancement fets. When the first field effect transistor and the second field effect transistor input high level, the first field effect transistor and the second field effect transistor are turned on, and the first array substrate row driving circuit 20 and the second array substrate row driving circuit 30 are respectively electrically connected to the scanning line 12. When the gates of the first field effect transistor and the second field effect transistor input a low level, the first field effect transistor and the second field effect transistor are turned off, and the first array substrate row driving circuit 20 and the second array substrate row driving circuit 30 are electrically isolated from the scan line 12, respectively. Of course, the first fet and the second fet may also be P communication enhancement fets. At the moment, the conducting voltage level of the grid electrodes of the first field effect transistor and the second field effect transistor is opposite to that of the N communication enhanced field effect transistor.
It is understood that the first switching device 40 and the second switching device 50 may be provided as other devices. For example, in some embodiments, the first switching device 40 may be configured as a first transistor, the control terminal of the first switching device 40 is a base of the first transistor, an emitter of the first transistor is connected to the first output terminal, and a collector of the first transistor is connected to the scan line 12; the second switching device 50 may be configured as a second triode, a control terminal of the second switching device 50 is a gate of the second triode, an emitter of the second triode is connected to the second output terminal, and a collector of the second triode is connected to the scan line 12. It should be noted that the first transistor and the second transistor may be NPN transistors. Of course, the first triode and the second triode can also be provided as PNP tubes. At the moment, the conducting voltage level of the base electrodes of the first triode and the second triode is opposite to that of the N communication enhanced field effect transistor.
In this embodiment, the conduction control module is a Chip On Film (Chip On Film), and the first enable terminal and the second enable terminal are output terminals of the Chip On Film. The flip chip film is in first enabling end 61 with second enabling end 62 output opposite level, make first array base plate row drive circuit 20 with second array base plate row drive circuit 30 alternate with scanning line 12 electrical property switches on, through right first array base plate row drive circuit 20 or second array base plate row drive circuit 30 carries out the unilateral respectively and detects, and the trouble of array base plate row drive circuit in the liquid crystal display panel of this application detectable double-ended array base plate row drive circuit drive is in order to realize that the array base plate row drive circuit of trouble detects in time and changes or maintains, improves the detection efficiency of trouble.
The first array substrate row driving circuit 20 and the second array substrate row driving circuit 30 each include a plurality of cascaded array substrate row driving units, and the first output end are output ends of each array substrate row driving unit. After the row driving circuit of the array substrate on the side where the fault is detected, in order to further accurately find that a specific row driving unit of the array substrate in the row driving circuit of the array substrate has the fault, as shown in fig. 2, each of the first switching devices 40 and each of the second switching devices 50 are respectively connected to a voltage test pin 70. Whether the array substrate row driving unit breaks down or not can be detected by detecting the output voltage of the array substrate row driving unit from the voltage testing pin, so that a specific fault position is found out. For example, when it is detected that the first array substrate row driving circuit 20 has a fault, each voltage test pin of the first switching device 40 is tested, so as to find out a fault position of the fault on the first array substrate row driving circuit 20, which is convenient for a maintenance worker to replace and repair, and improves the fault detection efficiency.
Example 2
This embodiment is based on embodiment 1, and only the differences between this embodiment and embodiment 1 will be described below, and the same parts as embodiment 1 will be omitted or abbreviated.
Referring to fig. 3, in the present embodiment, the conduction control module 60 includes a signal source 65 and an inverter circuit 66, the inverter circuit 66 has an input terminal 661 and a third output terminal 662, the signal source 65 is connected to the first enable terminal 61 and the input terminal 661, respectively, and the third output terminal 662 is connected to the second enable terminal 62. It is understood that the signal source 65 can also be connected to the second enable terminal 62 and the input terminal 661, respectively, and the third output terminal 662 can be connected to the first enable terminal 61. The signal source 65 may be selected from a variety of power sources that provide a regulated voltage.
Specifically, the inverter circuit includes an N-channel field effect transistor 663, a P-channel field effect transistor 664 and a voltage source 665, a gate of the N-channel field effect transistor 663 is connected to a gate of the P-channel field effect transistor 664 to form the input terminal, a source of the N-channel field effect transistor 663 is connected to a source of the P-channel field effect transistor 664 to form the third output terminal, a drain of the N-channel field effect transistor 663 is grounded, and a drain of the P-channel field effect transistor 664 is connected to the voltage source 665. The voltage source 665 is a variety of power sources that can be selected to provide a regulated voltage.
When the signal source outputs a high level, the first enable terminal 61 outputs a high level, and the first switching device 40 located at one side of the effective display area 10 is turned on; and the signal source outputs a high level through the inverter circuit and then outputs a low level at the third output terminal, so that the second enable terminal 62 outputs a low level, and the second switching device 50 located at the other side of the effective display area 10 is turned off, and at this time, whether the first array substrate row driving circuit 20 fails or not can be tested by detecting whether the effective display area 10 displays normally or not. On the contrary, when the signal source outputs a low level, the first enable terminal 61 outputs a low level, and the first switching device 40 located at one side of the effective display area 10 is turned off; and the signal source outputs a low level through the inverter circuit and then outputs a high level at the third output terminal, so that the second enable terminal 62 outputs a high level, and the second switching device 50 located at the other side of the effective display area 10 is turned on, and at this time, whether the second array substrate row driving circuit 30 fails or not can be tested by detecting whether the effective display area 10 displays normally or not.
Through setting up first enable end 61 with the output level of second enable end 62 is opposite, only has one side at the same moment first array base plate row drive circuit 20 or second array base plate row drive circuit 30 with scanning line 12 electric communication, through right first array base plate row drive circuit 20 or second array base plate row drive circuit 30 carries out the unilateral respectively and detects, the trouble of array base plate row drive circuit among the detectable double-ended array base plate row drive circuit driven liquid crystal display panel of this application to the array base plate row drive circuit who realizes the trouble detects in time and changes or maintains, improves the detection efficiency of trouble.
The inverter is a CMOS (Complementary Metal oxide semiconductor) inverter. In other arrangements, the inverter circuit may be another circuit having an inverter function, such as a Transistor-Transistor Logic (TTL) inverter.
Example 3
Referring to fig. 4, the present application further provides a method for detecting a line driving circuit of an array substrate of a liquid crystal panel, which is applicable to the liquid crystal panel, and the method for detecting a line driving circuit of an array substrate of a liquid crystal panel includes:
s10, the first enable terminal 61 outputs a high level, the second enable terminal 62 outputs a low level, and the first array substrate row driving circuit 20 is tested to determine whether it is working normally;
when the first enable terminal 61 is at a high level and the second enable terminal 62 is at a low level, the first switching device 40 located at one side of the active display area 10 is turned on; and the first switching device 40 on the other side of the effective display area 10 is turned off, and at this time, whether the first array substrate row driving circuit 20 has a fault can be tested by detecting whether the effective display area 10 displays normally.
S20, the first enable terminal 61 outputs a low level, the second enable terminal 62 outputs a high level, and the second array substrate row driving circuit 30 is tested to determine whether it is working normally.
On the contrary, when the first enable terminal 61 is at a low level and the second enable terminal 62 is at a high level, the second switching device 50 located at the other side of the effective display area 10 is turned on, and at this time, whether the second array substrate row driving circuit 30 fails or not can be tested by detecting whether the effective display area 10 displays normally or not.
S30, the voltage of the voltage test pin 70 on the side where the fault occurs is detected.
Whether the array substrate row driving unit breaks down or not can be detected by detecting the output voltage of the array substrate row driving unit from the voltage testing pin, so that a specific fault position is found out.
By setting the output levels of the first enable terminal 61 and the second enable terminal 62 to be opposite, the first array substrate row driving circuit 20 or the second array substrate row driving circuit 30 on only one side at the same time is electrically communicated with the scanning line 12, and by respectively performing single-side detection on the first array substrate row driving circuit 20 or the second array substrate row driving circuit 30 and detecting the output voltage of the array substrate row driving unit from the voltage test pin, whether the array substrate row driving unit fails or not can be detected, so that a specific failure position can be found out. The array substrate row driving circuit in the liquid crystal panel driven by the double-end array substrate row driving circuit can be detected, maintenance personnel can replace and repair the liquid crystal panel conveniently, and the detection efficiency of faults is improved.
The above description is only a preferred embodiment of the present application, and not intended to limit the scope of the present application, and all modifications and equivalents of the technical solutions that can be directly or indirectly applied to other related fields without departing from the spirit of the present application are intended to be included in the scope of the present application.
Claims (10)
1. The utility model provides a liquid crystal display panel, its characterized in that, this liquid crystal display panel have the effective display area and locate respectively the first array base plate row driver circuit and the second array base plate row driver circuit of effective display area both sides, the effective display area is provided with many scanning lines, first array base plate row driver circuit corresponds many the scanning line is equipped with a plurality of first outputs, second array base plate row driver circuit corresponds many the scanning line is equipped with a plurality of second outputs, liquid crystal display panel still includes:
a plurality of first switching devices, each of which is electrically connected between the first output terminal and the scan line;
a plurality of second switching devices, each of which is electrically connected between the second output terminal and the scan line; and
and the conduction control module is provided with a first enabling end and a second enabling end which enable the first array substrate row driving circuit and the second array substrate row driving circuit to be alternately and electrically conducted with the scanning lines.
2. The liquid crystal panel according to claim 1, wherein the first enable terminal is connected to control terminals of a plurality of the first switching devices, respectively, the second enable terminal is connected to control terminals of a plurality of the second switching devices, respectively, and output levels of the first enable terminal and the second enable terminal are opposite.
3. The liquid crystal panel according to claim 2, wherein the first switching device is a first field effect transistor, the control terminal of the first switching device is a gate of the first field effect transistor, a source of the first field effect transistor is connected to the first output terminal, and a drain of the first field effect transistor is connected to the scan line;
the second switching device is a second field effect transistor, the control end of the second switching device is a grid electrode of the second field effect transistor, the source electrode of the second field effect transistor is connected with the second output end, and the drain electrode of the second field effect transistor is connected with the scanning line.
4. The liquid crystal panel according to claim 2, wherein the first switching device is a first transistor, a control terminal of the first switching device is a base of the first transistor, an emitter of the first transistor is connected to the first output terminal, and a collector of the first transistor is connected to the scan line;
the second switching device is a second triode, the control end of the second switching device is a grid electrode of the second triode, the emitting electrode of the second triode is connected with the second output end, and the collecting electrode of the second triode is connected with the scanning line.
5. The liquid crystal panel according to any of claims 1 to 4, wherein the conduction control module is a chip on film, and the first and second enable terminals are output terminals of the chip on film.
6. The liquid crystal panel according to any one of claims 1 to 4, wherein the conduction control block includes a signal source and an inverter circuit, the inverter circuit having an input terminal and a third output terminal, the signal source being connected to the first enable terminal and the input terminal, respectively, and the third output terminal being connected to the second enable terminal.
7. The liquid crystal panel according to claim 6, wherein the inverter circuit includes an N-channel field effect transistor, a P-channel field effect transistor, and a voltage source, a gate of the N-channel field effect transistor is connected to a gate of the P-channel field effect transistor to form the input terminal, a source of the N-channel field effect transistor is connected to a source of the P-channel field effect transistor to form the third output terminal, a drain of the N-channel field effect transistor is grounded, and a drain of the P-channel field effect transistor is connected to the voltage source.
8. The liquid crystal panel according to any one of claims 1 to 4, wherein each of the first switching devices and each of the second switching devices are respectively connected with a voltage test pin.
9. The utility model provides a liquid crystal display panel, its characterized in that, this liquid crystal display panel have the effective display area and locate respectively the first array base plate row driver circuit and the second array base plate row driver circuit of effective display area both sides, the effective display area is provided with many scanning lines, first array base plate row driver circuit corresponds many the scanning line is equipped with a plurality of first outputs, second array base plate row driver circuit corresponds many the scanning line is equipped with a plurality of second outputs, liquid crystal display panel still includes:
a plurality of first switching devices, each of which is electrically connected between the first output terminal and the scan line;
a plurality of second switching devices, each of which is electrically connected between the second output terminal and the scan line; and
the conduction control module is provided with a first enabling end and a second enabling end which enable the first array substrate row driving circuit and the second array substrate row driving circuit to be alternately and electrically conducted with the scanning lines;
the first enabling end is connected with the control ends of the first switching devices respectively, the second enabling end is connected with the control ends of the second switching devices respectively, and the output levels of the first enabling end and the second enabling end are opposite;
the first switching device is a first field effect transistor, the control end of the first switching device is the grid electrode of the first field effect transistor, the source electrode of the first field effect transistor is connected with the first output end, and the drain electrode of the first field effect transistor is connected with the scanning line;
the second switching device is a second field effect transistor, the control end of the second switching device is a grid electrode of the second field effect transistor, the source electrode of the second field effect transistor is connected with the second output end, and the drain electrode of the second field effect transistor is connected with the scanning line;
the conduction control module is made of a chip on film, and the first enabling end and the second enabling end are output ends of the chip on film.
10. A method for detecting a line driving circuit of an array substrate of a liquid crystal panel, which is applied to the liquid crystal panel of any one of claims 1 to 9, the method comprising:
the first enabling end outputs high level, the second enabling end outputs low level, and whether the first array substrate row driving circuit works normally is tested;
the first enabling end outputs low level, the second enabling end outputs high level, and whether the second array substrate row driving circuit works normally or not is tested.
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Application publication date: 20210205 |