CN112328517B - Memory data communication device and method based on three-dimensional chip and related equipment - Google Patents
Memory data communication device and method based on three-dimensional chip and related equipment Download PDFInfo
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Abstract
The embodiment of the application solves the problems of high manufacturing cost, high difficulty, high operation risk and poor stability caused by using a through silicon via technology to realize high bandwidth by providing the memory data communication device, the method and the related equipment based on the three-dimensional chip. The memory data communication device may include: the memory unit comprises a memory unit side port, a memory controller, a serial protocol conversion circuit and a processor side port, wherein the memory unit port is used for being connected with the memory unit in a wire bonding mode so that each memory unit can independently perform data communication with the communication device; the memory controller is connected with the side port of the storage unit and is used for processing and access control of memory data; the serial protocol conversion circuit is connected with the memory controller and is used for carrying out serial protocol conversion processing on the data processed by the memory controller; and the processor side port is connected with the serial protocol conversion circuit and is used for communicating the data after serial protocol conversion processing with the processor.
Description
Technical Field
The embodiment of the invention relates to the technical field of memories, in particular to a memory data communication device and method based on a three-dimensional chip and related equipment.
Background
Along with the application of ASIC chips in the fields of AI artificial intelligence, big data centers, automatic driving and the like, a large amount of data needs to be processed, the demand for calculation force is correspondingly increased, and the demand for bandwidth of the device is also increased. There has been a bottleneck to the development of the prior art for video memories, and there has been no significant space for providing a larger video memory bit width by frequency boosting.
Currently, due to the 3DS (3-Dimensional Stack, three-dimensional stacking) technology, three-dimensional chips are gradually and widely used, so that the three-dimensional chips can be understood as a technology for stacking common two-dimensional chips, more common mode is that each memory cell is connected based on a Through-Silicon-Vi (Through-Silicon-Vi) technology, each memory layer can be stacked Through the TSV technology, and metal layers are equally spaced between the layers. The most typical examples are HBM (High Bandwidth Memory ) and HMC (Hybrid Memory Cube, hybrid cubic memory). However, from the viewpoint of manufacturing, it is very difficult to realize a 3D stacked structure of several tens of layers, and the manufacturing difficulty is high, and there are problems of high operation risk, poor stability, and the like due to the immaturity of technology. Further, both HBM and HMC use silicon intermediaries, and therefore are costly and have very limited output.
Disclosure of Invention
In the summary, a series of concepts in a simplified form are introduced, which will be further described in detail in the detailed description. The summary of the embodiments of the present application is not intended to define the key features and essential features of the claimed subject matter, but is not intended to define the scope of the claimed subject matter.
The embodiment of the application solves the problems of high manufacturing cost, high difficulty, high operation risk and poor stability caused by using a through silicon via technology to realize high bandwidth by providing the memory data communication device, the method and the related equipment based on the three-dimensional chip.
To at least partially solve the above problems, in a first aspect, an embodiment of the present application provides a memory data communication device, which may include:
a storage unit side port, a memory controller, a serial protocol conversion circuit and a processor side port,
wherein,
the storage unit port is used for being connected with the storage unit through wire bonding, so that each storage unit can independently perform data communication with the communication device;
the memory controller is connected with the storage unit side port and is used for processing and access control of stored data;
the serial protocol conversion circuit is connected with the memory controller and is used for carrying out serial protocol conversion processing on the data processed by the memory controller;
the processor side port is connected with the serial protocol conversion circuit and is used for communicating the data after serial protocol conversion processing with a processor.
In a first possible implementation manner of the first aspect, the memory data communication device may further include:
and the deserializing circuit is connected with the serial protocol conversion circuit and is used for deserializing the data after the serial protocol conversion.
In a second possible implementation manner of the first aspect, the processor-side port is a parallel port array.
In a third possible implementation manner of the first aspect, the memory data communication device may further include:
and the multi-path data bridge is connected with the memory controller and is used for bridging the data signals transmitted by the plurality of storage units.
In a fourth possible implementation manner of the first aspect, the memory data communication device may further include:
and the phase-locked loop is connected with the memory controller and is used for synchronizing data signals transmitted by a plurality of storage units.
In a fifth possible implementation manner of the first aspect, the memory data communication device may further include:
and the self-test circuit is connected with the memory controller and is used for self-testing the device and the function conditions of all functional units in the device.
In a second aspect, an embodiment of the present application provides a memory data communication method, which may be used in the memory data communication device described above, and may include:
the storage data of each storage unit are respectively obtained through the storage unit ports;
acquiring the stored data through the memory controller, processing the stored data, and sending the processed data to the serial protocol conversion circuit;
and the serial protocol conversion circuit performs serial protocol conversion on the data processed by the memory controller, and the processor side port performs data communication with the processor.
In a first possible implementation manner of the second aspect, before the step of communicating data with the processor by the processor-side port, the method may further include:
and the data after the serial protocol conversion processing is subjected to deserializing processing through a deserializing circuit.
In a second possible implementation manner of the second aspect, the processor-side port is a parallel port array.
In a third possible implementation manner of the second aspect, before the step of sending the processed data to the serial protocol conversion circuit, the method may further include:
and receiving the data processed by the memory controller through a multi-path data bridge, and bridging the data processed by the memory controller.
In a fourth possible implementation manner of the second aspect, before the step of sending the processed data to the serial protocol conversion circuit, the method further includes:
and receiving the data processed by the memory controller through a phase-locked loop, and synchronizing the data processed by the memory controller.
In a fifth possible implementation manner of the second aspect, the method may further include:
and detecting the functional condition of each functional unit in the device through a self-test circuit.
In a third aspect, embodiments of the present application provide a memory, which may include:
two or more memory units and the memory data communication device, wherein,
each storage unit of the two or more storage units is connected with the memory data communication device in a wire bonding mode, so that each storage unit can independently perform data communication with the memory data communication device.
In a first possible implementation manner of the third aspect, the two or more memory cells may be stacked to form a memory cell group, and the memory includes one or more memory cell groups that are tiled.
In a second possible implementation manner of the third aspect, the memory cell is a double rate synchronous dynamic random access memory cell.
In a fourth aspect, an embodiment of the present application provides an electronic device, which may include:
a processor and the above-mentioned memory, wherein,
the processor is connected with the memory and is used for reading data from the memory through the memory data communication device or writing data into the memory through the memory data communication device.
Compared with the prior art, the memory data communication device provided by the embodiment of the invention at least has the following beneficial effects:
the memory data communication device provided by the embodiment of the invention comprises: the memory unit side port, the memory controller, the serial protocol conversion circuit and the processor side port make full use of the wire bonding technology, so that each memory unit can independently perform data communication with the communication device. And the serial protocol conversion circuit is combined to process the data signals independently transmitted by the storage units into high-speed serial signals, so that the number of channels required by the transmission of the data signals in the communication device is greatly reduced, the crosstalk problem possibly occurring when multipath signals are transmitted in the communication device is avoided, the realization cost of a memory and related equipment is greatly reduced on the basis of ensuring high-bandwidth communication, and the efficiency and the stability of data communication are improved.
Correspondingly, the memory and the electronic equipment provided by the embodiment of the invention also have the technical effects.
Drawings
For a clearer description of the technical solutions in the embodiments of the present application, the following description of the embodiments will be given with reference to the accompanying drawings, which are used in the description of the embodiments, and it is obvious that, for a person skilled in the art, without any inventive effort, other drawings can be obtained from these drawings:
FIG. 1 is a schematic block diagram of a memory data communication device according to an embodiment of the present invention;
FIG. 2 is a schematic block diagram of another memory data communication device according to an embodiment of the present invention;
FIG. 3 is a schematic block diagram of a further memory data communications device provided in accordance with an embodiment of the present invention;
FIG. 4 is a schematic flow chart of a memory data communication method according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a memory according to an embodiment of the present invention;
FIG. 6 is a schematic block diagram of a memory according to an embodiment of the present invention;
fig. 7 is a schematic block diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
The present invention is described in further detail below with reference to the drawings and examples to enable those skilled in the art to practice the invention by referring to the description.
It will be understood that terms, such as "having," "including," and "comprising," as used herein, do not preclude the presence or addition of one or more other elements or groups thereof.
In addition, it should be noted that the terms "disposed," "connected," and "connected" are to be construed broadly, unless otherwise specifically indicated and defined. For example, the connection can be fixed connection or detachable connection; can be directly connected or indirectly connected through an intermediate medium; may be integrally connected, or may be communication between two members. Or the two elements can be in signal transmission and data communication. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.
Currently, in order to obtain higher bandwidths, 3DS technology is generally used by stacking individual storage layers. For example, the HBM chip and the HMC chip of each memory cell are communicated based on TSV technology. The HBM chip stacks a plurality of DDR double rate synchronous dynamic random memory unit chips and a PLD (Programmable Logic Device ) and encapsulates the chips with the GPU, and the chip-to-chip connection is realized by utilizing the joint of the through silicon vias and the micro bumps, so that the DDR combined array with high capacity and high bit width is realized. While HMC chips are stacked with multiple DRAM layers on one basic logic layer, the best combination of logic and DRAM processes is achieved in one heterogeneous package. The DRAM layer processes only data, while the logic layer processes all control functions in the HMC.
However, it is very difficult to realize a stack structure of several tens of layers, and there are problems of high operation risk, poor stability, etc. due to the immaturity of the technology. Further, both HBM and HMC use silicon intermediaries, and therefore are costly and have very limited output. In addition, since there are a large number of DRAM stacks and GPUs packaged together, the heat dissipation performance thereof is also seriously affected.
Aiming at the problems, the embodiment of the application provides a memory data communication device, a memory data communication method and related equipment based on a three-dimensional chip, which solve the problems of high manufacturing cost, high difficulty, high operation risk and poor stability caused by using a silicon through hole technology for realizing high bandwidth.
Fig. 1 is a schematic block diagram of a memory data communication device according to an embodiment of the present invention, and as shown in fig. 1, the memory data communication device 100 may include: a storage unit side port 110, a memory controller 120, a serial protocol conversion circuit 130, and a processor side port 140. The memory data communication device 100 may be configured to interconnect a plurality of memory units and enable the memory units to communicate data with a processor. Accordingly, the memory unit side 110 is a side to be connected to a memory unit, and the processor side port 140 is a side to be connected to a processor, and the ports may be represented by PHY (Port Physical Layer ). The memory cells may also be referred to as memory granules or memory cells or Die semiconductor Die, each for storing instruction or data information.
Wherein,
the memory cell side port 110 may be used for wire bonding connection with memory cells so that each memory cell can independently perform data communication with the communication device 100;
it should be noted that, by way of example, the wire bonding technique is a process technique in which a semiconductor die is connected to an I/O lead of a microelectronic package or a metal wire Pad on a substrate with metal filaments, enabling rapid interconnection between chips. May include: wire bonding types such as thermocompression bonding, ultrasonic bonding, and thermosonic bonding. The wire bonding technology can lead the metal of the welding area to generate plastic deformation, so that the lead is tightly contacted with the welded surface of the bare chip or the microelectronic, the interatomic attraction range is reached, and the interatomic diffusion is caused to form welding points, thereby realizing the transmission of data signals.
In some examples, the memory cell side port 110 may enable each memory cell to communicate data independently of the communication device 100 after wire bonding with a plurality of memory cells. The problems of high cost and heat dissipation caused by the need of using a silicon interposer when the TSVs are used for communicating the storage units during data communication and the problem of signal crosstalk easily generated by the communication of the storage units through the TSVs are avoided.
In addition, since there are a large number of stacks of DRAMs (Dynamic Random Access Memory, memory) and GPUs (Graphics Processing Unit, graphics processors) packaged together, heat dissipation is also severely affected. And because the wire bonding technology is utilized, each storage unit can independently communicate data with the communication device, and compared with a storage unit stacking scheme which adopts a silicon medium layer, the heat dissipation performance is better.
The memory controller 120 is connected to the storage unit side port 110, and is used for processing and access control of stored data; it should be noted that, the memory controller 120 is an important component for controlling the memory inside the module with the computing function and exchanging data between the memory and the processor through the memory controller. Can be used for access control of addresses, conversion of protocols and integration of data.
In some examples, the memory unit may be integrated by the memory controller 120 through converting the memory unit side port 110 into an internal signal, and the memory controller 120 converts the protocol and the instruction into a standard protocol for subsequent data communication.
The serial protocol conversion circuit 130 is connected to the memory controller 120, and is configured to perform serial protocol conversion processing on data processed by the memory controller 120;
in some examples, serial protocol conversion circuit 130 may be a SERializer that serializes data into high-speed serial data for subsequent data communications, not only greatly reducing the number of channels required for transmission of data signals in the communication device, but also avoiding cross-talk problems that may occur when multiple signals are transmitted in the communication device.
The processor-side port 140 is connected to the serial protocol conversion circuit 130, and is configured to communicate data after serial protocol conversion processing with a processor.
In some examples, the data processed by the serial protocol conversion circuit 130 may be communicated to a processor through the processor-side port 140 described above.
The memory data communication device 100 according to the embodiment of the present invention makes each memory unit capable of independently performing data communication with the communication device by fully using the wire bonding technology. And the serial protocol conversion circuit is combined to process the data signals independently transmitted by the storage units into high-speed serial signals, so that the number of channels required by the transmission of the data signals in the communication device is greatly reduced, the crosstalk problem possibly occurring when multipath signals are transmitted in the communication device is avoided, the realization cost of a memory and related equipment is greatly reduced on the basis of ensuring high-bandwidth communication, and the efficiency and the stability of data communication are improved.
According to some embodiments, the memory data communication device may further include: and the deserializing circuit can be connected with the serial protocol conversion circuit and is used for deserializing the data after the serial protocol conversion. The serial protocol conversion circuit after adding the DESerializer may be referred to as a SERDES serial-parallel conversion circuit.
The memory unit side port serializes the low-speed parallel data to be transmitted into high-speed serial data by using a serial protocol conversion circuit, then transmits the serial data to the data receiving end, and then deserializes the received high-speed serial data into multiple paths of low-speed parallel data by using a deserializing circuit at the other end, thereby completing the whole transmission process of the data in the communication device. In the subsequent transmission process of the de-serialized multipath low-speed parallel data, the method has the advantages of lower hardware implementation cost and better reliability.
To satisfy the above-described multiple low-speed parallel data communication with the processor, the above-described processor-side port may be a parallel port array.
According to some embodiments, the memory data communication device may further include:
and the multi-path data bridge can be connected with the memory controller and used for bridging data signals transmitted by a plurality of storage units so as to carry out subsequent data serialization processing.
According to some embodiments, the memory data communication device may further include:
and the phase-locked loop is connected with the memory controller and is used for synchronizing data signals transmitted by a plurality of storage units. The phase-locked loop can be used for unifying and integrating clock signals so as to achieve the aim of synchronizing internal signals, so that the memory controller can accurately access data information.
According to some embodiments, the memory data communication device may further include:
and the self-test circuit is connected with the memory controller and is used for self-testing the device and the function conditions of all functional units in the device. The self-test circuit can be used for providing a self-test function of the communication device and ensuring the reliability of the communication device.
The specific use scenario illustrated in fig. 2 and 3 will be described in detail below, where the processor reads the data stored in the memory unit through the DRAM PHY on the memory unit side of the memory data communication device, converts the protocol and the command into the standard protocol through the memory controller, then sends the read data to the multiple data bridge, and then sends the data to the processor side port SERDES PHY of the memory data communication device through the serial protocol conversion circuit through the multiple data bridge, and the processor can also write the data into the memory unit through the processor side port SERDES PHY of the memory data communication device.
Fig. 2 is a schematic block diagram of another memory data communication device according to an embodiment of the present invention, where, as shown in fig. 2, the memory data communication device may include: a memory unit side port DRAM PHY, a memory controller, a phase locked loop, a multiple data bridge, a serial protocol conversion circuit, and two processor side ports SERDES PHY. The input end of the DRAM PHY is connected with the storage unit to obtain the instruction or data information sent by the storage unit, and the output end of the SERDES PHY is connected with the processor to send the instruction or data of the storage unit to the processor through the communication device.
Specifically, referring to fig. 2, the command or data information transmitted by the plurality of memory units may be converted into an internal signal of the memory data communication device through the DRAM PHY at the memory unit side of the memory data communication device, and integrated by the memory controller, where the memory controller converts the protocol and the command into a standard protocol and then bridges the standard protocol and the standard protocol by the multi-path data bridge. The phase-locked loop is used for integrating and controlling the clock signals of the internal signals of the memory data communication device uniformly, so that the aim of synchronizing the internal signals is achieved, and the memory can accurately access data. The self-test circuit can be a built-in self-test circuit for providing a test function for the communication device itself, for example, the self-test circuit can detect the functional conditions of the internal interface, the memory controller and other elements to ensure the reliability of the communication device or the memory unit in communication with the communication device. In the example shown in fig. 2, the self-test circuit uses the JTAG test protocol to detect the function of the communication device itself. The serial data obtained by the preliminary processing is processed by the serial protocol conversion circuit to obtain high-speed serial data, and as shown in fig. 2, the serial communication can perform data interaction with the processor through the two processor side ports SERDES PHY of the memory data communication device after the protocol circuit is reconverted.
More specifically, taking an LPDDR4 memory cell as an example, the capacity of a single LPDDR4 memory cell is 1GB, the bit width is 16 bits, 4 LPDDR4 memory cells can be stacked together into one group, 2 groups are tiled, the bit width is 128 bits altogether, the total bandwidth=frequency x bit width/8=4266 x16x 8/8=68 GBps, and the total capacity of 2 groups of 8 LPDDR4 memory cells is 8GB, and the total bandwidth is 68GBps. After the 8 LPDDR4 memory cells are respectively connected with the memory data communication device through a wire bonding technology, each LPDDR4 memory cell can independently perform data communication with the communication device. The data of the 8 LPDDR4 memory units are integrated through the DRAM PHY and the memory controller at the memory unit side and then are bridged to the data bridge, and then are converted into high-speed serial data by the serial protocol conversion circuit and are transmitted to the 2 processor side ports SERDES PHY, so that the data interaction between the memory units and the processor is realized. It should be noted that, since the serial protocol conversion circuit generally has a certain loss when performing protocol conversion on data, the data bit width can be 8 bits and the transmission rate can be 40Gbps on each processor side port SERDES PHY.
Fig. 3 is a schematic block diagram of another memory data communication device according to an embodiment of the present invention, where, as shown in fig. 3, the memory data communication device may include: a memory unit side port DRAM PHY, a memory controller, a phase locked loop, a multi-way data bridge, a serial to parallel circuit, and a low speed interface PHY array as a processor side port. The input end of the DRAM PHY is connected with the storage unit to obtain the instruction or data information sent by the storage unit, and the output end of the low-speed interface PHY array is connected with the processor and used for sending the instruction or data stored by the storage unit to the processor through the communication device.
Specifically, referring to fig. 3, the command or data information transmitted by the plurality of memory units may be converted into an internal signal of the memory data communication device through the DRAM PHY at the memory unit side of the memory data communication device, and integrated by the memory controller, where the memory controller converts the protocol and the command into a standard protocol and then bridges the standard protocol and the standard protocol by the multi-path data bridge. The phase-locked loop is used for integrating and controlling the clock signals of the internal signals of the memory data communication device uniformly, so that the aim of synchronizing the internal signals is achieved, and the memory can accurately access data. The self-test circuit can be a built-in self-test circuit and can be used for providing a test function for the communication device, for example, the self-test circuit can be used for detecting the functional conditions of the internal interfaces, the memory controller and other elements so as to ensure the reliability of the communication device or a storage unit communicated with the communication device. In the example shown in fig. 3, the self-test circuit uses the JTAG test protocol to detect the function of the communication device itself. The data processed by the multi-path data bridge is converted by a serial-to-parallel conversion circuit, and the serial-to-parallel conversion circuit comprises a deserializing circuit besides the serial protocol conversion circuit, and the deserializing circuit can be connected with the serial protocol conversion circuit and is used for deserializing the data processed by the serial protocol conversion circuit. The serial protocol conversion circuit after adding the DESerializer may be referred to as a SERDES serial-parallel conversion circuit. The specific process of data signal transmission is that the low-speed parallel data transmitted by a plurality of memory units to be transmitted are serialized into high-speed serial data, then the serial data are transmitted to the receiving end of the deserializing circuit, then the received high-speed serial data are deserialized into multiple paths of low-speed parallel data by the deserializing circuit, and the multiple paths of low-speed parallel data are transmitted to a processor through the low-speed interface PHY array serving as a port of the processor side, so that the whole transmission process is completed. Correspondingly, the processor can write data into the memory unit through the low-speed interface PHY array of the memory data communication device.
In some examples, based on the memory data communication device shown in fig. 3, the single LPDDR4 memory cells have a capacity of 1GB and a bit width of 16 bits, and 4 LPDDR4 memory cells are stacked together into one group and tiled into 2 groups, so that there are 8 memory cells in total, the bit width of which is 128 bits, the total bandwidth is 68GBps, and the total capacity is 8GB. After the 8 LPDDR4 memory cells are respectively connected with the memory data communication device through a wire bonding technology, each LPDDR4 memory cell can independently perform data communication with the communication device. The data of 8 LPDDR4 memory units are integrated by the DRAM PHY and the memory controller at the ports of the memory units and then bridged to a multi-path data bridge, then the low-speed parallel data transmitted by the memory units to be sent by the serial-parallel circuit are serialized into high-speed serial data, then the serial data are transmitted to the receiving end of the deserializing circuit, and then the received high-speed serial data are deserialized into multi-path low-speed parallel data by the deserializing circuit, and are transmitted to the processor through the PHY array of the low-speed interface serving as the ports of the processor. The bit width of the transmission data on this port is 1024 bits, and the transmission rate is 533Mbps.
Based on the memory data communication device, the embodiment of the invention further provides a memory, which may include:
two or more memory units and the memory data communication device, wherein,
each of the two or more memory cells is connected to the memory data communication device by wire bonding, so that each memory cell can independently communicate data with the memory data communication device.
Accordingly, the memory provided by the embodiment of the invention enables each memory unit to independently communicate data with the communication device in the memory by fully utilizing the wire bonding technology. And the serial protocol conversion circuit is combined to process the data signals independently transmitted by the storage units into high-speed serial signals, so that the number of channels required by the transmission of the data signals in the communication device is greatly reduced, the crosstalk problem possibly occurring when multipath signals are transmitted in the communication device is avoided, the realization cost of a memory and related equipment is greatly reduced on the basis of ensuring high-bandwidth communication, and the efficiency and the stability of data communication are improved.
In some examples, the two or more memory cells may be stacked to form a memory cell group, and the memory may include one or more of the memory cell groups tiled. Further, the bandwidth of the memory is further improved, and quick interconnection between chips is realized.
In some examples, the memory unit may be a double data rate synchronous dynamic random access memory unit, for example, a double data rate synchronous dynamic random access memory conforming to a JEDEC solid state technology association standard, and specifically may be any one of a JEDEC DDR2, a JEDEC DDR3, a JEDEC DDR4, a JEDEC DDR5, a JEDEC GDDR6, a JEDEC LPDDR3, a JEDEC LPDDR4, and a JEDEC LPDDR 5.
The memory data communication device according to the embodiment of the present invention is described in detail above with reference to fig. 1 to 3, and the memory data communication method for the memory data communication device according to the embodiment of the present invention will be described in detail below with reference to fig. 4.
According to some embodiments, as shown in fig. 4, the memory data communication method may be used in the memory data communication apparatus, and may include: s110 to S130.
S110, respectively acquiring storage data of each storage unit through the storage unit port;
s120, the memory controller can acquire the stored data and process the stored data, and the processed data is sent to the serial protocol conversion circuit;
s130, the serial protocol conversion circuit can perform serial protocol conversion on the data processed by the memory controller, and the processor side port is used for data communication with the processor.
It should be noted that, the specific implementation means and technical effects of the memory data communication method have been described in detail in the working process and technical effects of the memory data communication device, and are not described herein again.
According to some embodiments, before the step of communicating data with the processor by the processor-side port, the method may further include:
and the data after the serial protocol conversion processing is subjected to deserializing processing through a deserializing circuit.
According to some embodiments, the processor-side ports may be an array of parallel ports.
According to some embodiments, before the step of sending the processed data to the serial protocol conversion circuit, the method may further include:
and receiving the data processed by the memory controller through a multi-path data bridge, and bridging the data processed by the memory controller.
According to some embodiments, before the step of sending the processed data to the serial protocol conversion circuit, the method further includes:
and receiving the data processed by the memory controller through a phase-locked loop, and synchronizing the data processed by the memory controller.
According to some embodiments, the above method may further comprise:
and detecting the functional condition of each functional unit in the device through a self-test circuit.
A memory according to an embodiment of the present invention will be described in detail with reference to fig. 5 and 6.
Fig. 5 is a schematic structural diagram of a memory according to an embodiment of the present invention, where, as shown in fig. 5, the memory includes a memory data communication device 100 and 8 memory cells 420, for example, a single memory cell has a capacity of 1GB, a bit width of 16 bits, 4 memory cells are stacked together to form a memory cell group, and 2 memory cell groups are tiled on two sides of the memory data communication device 100, and then the 2 memory cell groups have 8 memory cells in total, and the bit width of the memory data communication device has 128 bits, a total bandwidth of 68GBps, and a total capacity of 8GB.
In one example, each of the 8 memory cells is capable of independently communicating data with the communication device after being connected to the memory data communication device via a wire bonding technique. The data of 8 storage units are integrated by the DRAM PHY and the memory controller at the side of the storage unit and then bridged to a multi-path data bridge, then the low-speed parallel data transmitted by the storage units to be sent by the serial-parallel circuit are serialized into high-speed serial data, then the serial data are transmitted to the receiving end of the deserializing circuit, and then the received high-speed serial data are deserialized into multi-path low-speed parallel data by the deserializing circuit, and are transmitted to the processor through the low-speed interface PHY array serving as the port at the side of the processor. The bit width of the transmission data on this port is 1024 bits, and the transmission rate is 533Mbps.
In another example, the 8 LPDDR4 memory cells are each capable of independently communicating data with the memory data communication device after being connected to the communication device via wire bonding techniques. The data of the 8 LPDDR4 memory units are integrated through the DRAM PHY and the memory controller at the memory unit side and then are bridged to the data bridge, and then are converted into high-speed serial data by the serial protocol conversion circuit and are transmitted to the 2 processor side ports SERDES PHY, so that the data interaction between the memory units and the processor is realized. The data bit width may be 8 bits and the transmission rate may be 40Gbps on each processor side port SERDES PHY.
To further expand the above memory, the embodiment of the present invention further provides a memory 500, as shown in fig. 6, including the memory data communication device 100 and 4 memory cell groups 510. For example, a single LPDDR4 memory cell has a capacity of 1GB and a bit width of 16 bits, and 4 memory cells are stacked together into one group and tiled across 4 groups of memory cells, for a total of 16 memory cells. Taking LPDDR4 as an example, memory 500 may be expanded to 256 bits wide, with a total bandwidth of 128GBps and a total capacity of 16GB.
An electronic device according to an embodiment of the present invention will be described in detail below with reference to fig. 7. Fig. 7 is a schematic block diagram of an electronic device according to an embodiment of the present invention.
As shown in fig. 7, the electronic device 600 may include:
a processor 610 and the memory 500 described above, wherein,
the processor 610 is connected to the memory 500, and is configured to read data from the memory 500 by the memory data communication device 100 or write data to the memory 500 by the memory data communication device 100.
Accordingly, by fully utilizing the wire bonding technology, each storage unit of the electronic equipment provided by the embodiment of the invention can independently perform data communication with the communication device in the electronic equipment. And the serial protocol conversion circuit is combined to process the data signals independently transmitted by the storage units into high-speed serial signals, so that the number of channels required by the transmission of the data signals in the communication device is greatly reduced, the crosstalk problem possibly occurring when multipath signals are transmitted in the communication device is avoided, the realization cost of a memory and related equipment is greatly reduced on the basis of ensuring high-bandwidth communication, and the efficiency and the stability of data communication are improved.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
Although embodiments of the present invention have been disclosed above, it is not limited to the details and embodiments shown and described, it is well suited to various fields of use for which the invention would be readily apparent to those skilled in the art, and accordingly, the invention is not limited to the specific details and illustrations shown and described herein, without departing from the general concepts defined in the claims and their equivalents.
Claims (14)
1. A memory, comprising:
two or more memory cells and a three-dimensional chip based memory data communication device, wherein,
each storage unit in the two or more storage units is connected with the memory data communication device in a wire bonding mode, so that each storage unit can independently perform data communication with the memory data communication device;
the two or more than three memory units can be stacked to form a memory unit group, and the memory comprises one or more than two memory unit groups which are tiled;
the memory data communication device based on the three-dimensional chip comprises:
a storage unit side port, a memory controller, a serial protocol conversion circuit and a processor side port,
wherein,
the storage unit port is used for being connected with the storage units in a wire bonding mode so that each storage unit can independently perform data communication with the communication device;
the memory controller is connected with the storage unit side port and is used for processing and access control of stored data;
the serial protocol conversion circuit is connected with the memory controller and is used for carrying out serial protocol conversion processing on the data processed by the memory controller;
the processor side port is connected with the serial protocol conversion circuit and is used for communicating the data after serial protocol conversion processing with a processor.
2. The memory of claim 1, further comprising:
and the deserializing circuit is connected with the serial protocol conversion circuit and is used for deserializing the data after the serial protocol conversion.
3. The memory of claim 2, wherein the processor-side ports are parallel port arrays.
4. The memory of claim 1, further comprising:
and the multi-path data bridge is respectively connected with the memory controller and the serial protocol conversion circuit and is used for bridging the data signals transmitted by the storage units.
5. The memory of claim 1, further comprising:
and the phase-locked loop is connected with the memory controller and is used for synchronizing data signals transmitted by a plurality of storage units.
6. The memory of claim 1, further comprising:
and the self-test circuit is connected with the memory controller and is used for self-testing the device and the function conditions of all functional units in the device.
7. The memory of claim 1, wherein the memory cells are double rate synchronous dynamic random access memory cells.
8. A memory data communication method for a memory according to any one of claims 1 to 7, comprising:
the storage data of each storage unit are respectively obtained through the storage unit ports;
the memory controller acquires the stored data, processes the stored data and sends the processed data to the serial protocol conversion circuit;
and carrying out serial protocol conversion on the data processed by the memory controller through the serial protocol conversion circuit, and carrying out data communication with the processor through the port of the processor side.
9. The method of claim 8, wherein prior to the step of communicating data with the processor by the processor-side port, the method further comprises:
and the data after the serial protocol conversion processing is subjected to deserializing processing through a deserializing circuit.
10. The method of claim 9, wherein the processor-side port is an array of parallel ports.
11. The method of claim 8, wherein prior to the step of sending the processed data to the serial protocol conversion circuit, the method further comprises:
and receiving the data processed by the memory controller through a multi-path data bridge, and bridging the data processed by the memory controller.
12. The method of claim 8, wherein prior to the step of sending the processed data to the serial protocol conversion circuit, the method further comprises:
and receiving the data processed by the memory controller through a phase-locked loop, and synchronizing the data processed by the memory controller.
13. The method of claim 8, wherein the method further comprises:
and detecting the functional condition of each functional unit in the device through a self-test circuit.
14. An electronic device, comprising: a processor and a memory as claimed in any one of claims 1-7, wherein,
the processor is connected with the memory and is used for reading data from the memory through the memory data communication device or writing data into the memory through the memory data communication device.
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