CN112310041B

CN112310041B - Electronic device and method for manufacturing the same

Info

Publication number: CN112310041B
Application number: CN202010411348.5A
Authority: CN
Inventors: 洪堂钦; 丁景隆; 韦忠光; 高克毅; 王东荣; 谢志勇; 黄浩榕; 李宜音; 何家齐; 林宜宏; 周政旭; 曾嘉平
Original assignee: Innolux Display Corp
Current assignee: Innolux Corp
Priority date: 2019-07-29
Filing date: 2020-05-15
Publication date: 2023-04-18
Anticipated expiration: 2040-05-15
Also published as: CN112310041A

Abstract

The present disclosure provides an electronic device and a method for manufacturing the same. The electronic device comprises a first insulating layer, a first metal layer, a second metal layer and an electronic component. The first insulating layer includes a first surface and a second surface opposite to the first surface. The first metal layer has an opening and is formed on the first surface. The second metal layer is formed on the second surface, and a projection of the opening on the second surface may overlap a projection of the second metal layer on the second surface. The electronic component is electrically connected with the first metal layer and the second metal layer.

Description

Electronic device and method for manufacturing the same

Technical Field

The present disclosure relates to electronic devices, and particularly to an electronic device and a method for manufacturing the same.

Background

As electronic devices become more and more sophisticated, it is more difficult to directly fabricate active devices on substrates, films or glasses. Further, due to the limitations of line width and line spacing in the semiconductor manufacturing process, a multi-layer wiring structure must be formed on the circuit substrate to dispose the active device on the circuit substrate, which results in an increase in the size of the electronic device and the manufacturing cost. In view of this, several embodiments of solutions are presented below.

Disclosure of Invention

The present disclosure is directed to an electronic device and a method of manufacturing the same, which may provide or manufacture an electronic device including a transistor circuit and an electronic structure of a single-sided or double-sided Redistribution Layer (RDL) wiring.

According to an embodiment of the present disclosure, an electronic device includes a first insulating layer, a first metal layer, a second metal layer, and an electronic component. The first insulating layer includes a first surface and a second surface opposite to the first surface. The first metal layer has an opening and is formed on the first surface. The second metal layer is formed on the second surface, and a projection of the opening on the second surface overlaps a projection of the second metal layer on the second surface. The electronic component is electrically connected with the first metal layer and the second metal layer.

According to an embodiment of the present disclosure, an electronic device includes a first insulating layer, a first metal layer, a second metal layer, a PN junction element, and a transistor circuit. The first insulating layer includes a first surface and a second surface opposite to the first surface. The first metal layer is formed over the second surface. The second metal layer is formed on the second surface. The PN junction element is disposed on the first surface and electrically connects the first metal layer and the second metal layer. The PN junction element includes an adjustable capacitance. The transistor circuit is electrically connected with the second metal layer.

According to an embodiment of the present disclosure, a method for manufacturing an electronic device includes the following steps: providing a bearing substrate; forming a first metal layer with an opening on the bearing substrate; forming a first insulating layer on the first metal layer so that a first surface of the first insulating layer is in contact with the first metal layer; and forming a second metal layer on the first insulating layer so that a second surface of the first insulating layer is in contact with the second metal layer, wherein the first surface is opposite to the second surface, and a projection of the opening on the second surface is overlapped with a projection of the second metal layer on the second surface.

According to an embodiment of the present disclosure, a method for manufacturing an electronic device includes the following steps: providing a bearing substrate; forming a first insulating layer on the bearing substrate so that a first surface of the first insulating layer contacts the bearing substrate; forming a first metal layer and a second metal layer on the first insulating layer so that a second surface of the first insulating layer is in contact with the first metal layer and the second metal layer, wherein the first surface is opposite to the second surface; electrically connecting a transistor circuit to the second metal layer; removing the bearing substrate; and disposing a PN junction device having an adjustable capacitance on the first insulating layer, and electrically connecting the PN junction device to the first metal layer and the second metal layer.

Based on the above, the electronic device and the manufacturing method thereof of the present disclosure can realize an electronic device with an electronic structure having a smaller size and a lower manufacturing cost by using a smaller number of redistribution process wirings and a transistor circuit.

The present disclosure may be understood by reference to the following detailed description taken in conjunction with the accompanying drawings, it being noted that, for the sake of clarity and conciseness of the drawings, the various drawings in the present disclosure depict only a portion of a display device and certain components in the drawings are not necessarily drawn to scale. In addition, the number and size of the components in the figures are merely illustrative and are not intended to limit the scope of the present disclosure.

Drawings

The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

Fig. 1 is a schematic cross-sectional view illustrating a structure of an electronic device according to a first embodiment of the disclosure;

fig. 2A and 2B are flow charts of a method for manufacturing an electronic device according to a first embodiment of the disclosure;

FIGS. 3A-3D are schematic cross-sectional views of the structure at various stages during the fabrication method of FIGS. 2A and 2B;

FIG. 4 is a schematic cross-sectional view illustrating a structure of an electronic device according to a second embodiment of the disclosure;

fig. 5A and 5B are flow charts of a method for manufacturing an electronic device according to a second embodiment of the disclosure;

FIGS. 6A-6D are schematic cross-sectional views of structures at various stages during the fabrication method of FIGS. 5A and 5B;

FIG. 7 is a schematic cross-sectional view illustrating a structure of an electronic device according to a third embodiment of the disclosure;

FIG. 8 is a flowchart illustrating a method of manufacturing an electronic device according to a third embodiment of the present disclosure;

FIGS. 9A-9D are schematic cross-sectional views of structures at various stages during the fabrication method of FIG. 8;

FIG. 10 is a schematic cross-sectional view illustrating a structure of an electronic device according to a fourth embodiment of the disclosure;

FIG. 11 is a flowchart illustrating a method of manufacturing an electronic device according to a fourth embodiment of the present disclosure;

FIGS. 12A-12D are schematic cross-sectional views of structures at various stages during the fabrication method of FIG. 11;

FIG. 13 is a schematic cross-sectional view illustrating a structure of an electronic device according to a fifth embodiment of the disclosure;

FIG. 14 is a schematic cross-sectional view illustrating a structure of an electronic device according to a sixth embodiment of the disclosure;

fig. 15 is a schematic cross-sectional view illustrating a structure of an electronic device according to a seventh embodiment of the disclosure.

Description of the reference numerals

100. 400, 700, 1000, 1300, 1400, 1500 electronic device;

110. 310, 410, 610, 710, 910, 1010, 1210, 1310, 1410, 1510 a first metal layer;

111. 311, 411, 611, 1311, 1411, 1511: opening;

120. 320, 420, 620, 720, 920, 1020, 1220, 1320, 1420, 1520 a first insulating layer;

130. 330, 430, 630, 730, 930, 1030, 1230, 1330, 1430, 1530 a second metal layer;

140. 340, 440, 640, 740, 940, 1040, 1240, 1340, 1440, 1540 wiring layers;

150. 350, 450, 650, 750, 950, 1050, 1250, 1350, 1450, 1550 transistor circuitry;

160. 360, 460, 660, 760, 960, 1060, 1260, 1360, 1460, 1560 a second insulating layer;

170. 370, 370', 470, 670', 770, 970, 1070, 1270, 1370, 1470, 1570: electronic components;

171. 172, 371, 372, 471, 472, 671, 672, 771, 772, 971, 972, 1071, 1072, 1251, 1271, 1272, 1351, 1371, 1372, 1452, 1471, 1472, 1553, 1571, 1572: conductive elements;

180. 380, 480, 680, 780, 980, 1080, 1280, 1380, 1480 and 1580 of a control circuit;

181. 381, 481, 681, 781, 981, 1081, 1281, 1381, 1481, 1581: carrier plate;

182. 382, 482, 682, 782, 982, 1082, 1282, 1382, 1482, 1582: electrically conductive material;

301. 303, 601, 603, 901, 903, 1203, a carrier substrate;

302. 602, 902, 1202, a connection layer;

312 to 316 and 612 to 616 electrodes

690. 390, passive components;

s1, a first surface;

s2, a second surface;

s201 to S213, S501 to S513, S801 to S811, and S1101 to S1111;

d1, a first direction;

d2, a second direction;

and D3, a third direction.

Detailed Description

Certain terms are used throughout the description and following claims to refer to particular components. Those skilled in the art will appreciate that display device manufacturers may refer to the same components by different names. This document does not intend to distinguish between components that differ in function but not name. In the following specification and claims, the words "comprise", "comprising", "includes" and "including" are open-ended words, and thus should be interpreted to mean "including, but not limited to, ...".

In some embodiments of the present disclosure, terms such as "connected," "interconnected," and the like, with respect to bonding, connecting, and the like, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, unless otherwise specified, with respect to the structure between which they are disposed. And the terms coupled and connected should also be construed to include both structures being movable or both structures being fixed. Furthermore, the term "coupled" includes any direct and indirect electrical connection.

When a first material layer is disposed on or over a second material layer, the first material layer and the second material layer are in direct contact. Alternatively, one or more layers of other materials may be present, in which case there may not be direct contact between the first and second layers of material. In some embodiments of the present disclosure, terms such as "connected," "interconnected," and the like, with respect to bonding, connecting, and the like, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, unless otherwise specified, with respect to the structure between which they are disposed. And the terms coupled and connected should also be construed to include both structures being movable or both structures being fixed.

As used herein, the term "about," "approximately," "substantially" generally means within 15%, such as within 10%, within 5%, within 3%, within 2%, within 1%, or within 0.5% of a given value or range. The amounts given herein are approximate amounts, that is, the meanings of "about", "approximately" and "substantially" may be implied without specifically reciting "about", "approximately" and "substantially".

Although terms such as "first," "second," "third," etc. may be used to describe or name various elements, these elements are not limited by these terms. These terms are only used to distinguish one element from another element in the specification, regardless of the order in which the elements are manufactured. The claims may use different terminology and may be replaced by "first", "second", "third", etc. in the order in which the elements in the claims are announced. Accordingly, in the following description, a first member may be a second member in the claims. In the present disclosure, unless otherwise specified, components with the same name (e.g., the transistor circuit 150 and the transistor circuit 350.) may have the same or similar properties in different embodiments or drawings, and therefore, for brevity, the description may not be repeated.

It is to be understood that the following illustrative embodiments may be implemented by replacing, recombining, and mixing features of several different embodiments without departing from the spirit of the present disclosure.

Fig. 1 is a schematic cross-sectional view illustrating a structure of an electronic device according to a first embodiment of the disclosure. Referring to fig. 1, the electronic device 100 may include an electronic structure having a double-sided redistribution process wiring such that related electronic or circuit units may be disposed on both sides of a substrate, but is not limited thereto. Specifically, the electronic device 100 may include a first metal layer 110, a first insulating layer 120, a second metal layer 130, a wiring layer 140, a transistor circuit 150, a second insulating layer 160, an electronic component 170, and a control circuit 180. The Transistor circuit 150 may, for example, include one or more transistors, such as Thin-Film transistors (TFTs), and the types of the plurality of transistors may, for example, be Bottom gate (Bottom gate) transistors, top gate (Top gate) transistors, or Double gate (Double gate) transistors. The transistor circuit 150 may be electrically connected to the first metal layer 110 and/or the electronic component 170, but is not limited thereto. In the present embodiment, the first insulating layer 120 includes a first surface S1 and a second surface S2, wherein the first surface S1 is opposite to the second surface S2. The first surface S1 and the second surface S2 may be substantially parallel to a plane formed by the first direction D1 and the second direction D2. The first surface S1 faces a direction opposite to the third direction D3, and the second surface S2 faces the third direction D3. The first direction D1, the second direction D2, and the third direction D3 are substantially perpendicular to each other. In the present embodiment, the first insulating layer 120 may be a soft material, such as Polyimide (PI), but the disclosure is not limited thereto. In some embodiments, the first insulating layer 120 may also include a hard material (e.g., glass, ceramic, sapphire, or other suitable materials), a flexible material (e.g., polymer or other suitable materials), or a plastic circuit board, for example.

In the present embodiment, the first metal layer 110 has an opening 111, and is formed on the first surface S1 of the first insulating layer 120. The opening 111 may extend in the second direction D2 and be a slot structure. The second metal layer 130 is formed on the second surface S2 of the first insulating layer 120. In the present embodiment, a projection of the opening 111 projected on the second surface S2 toward the third direction D3 overlaps a projection of the second metal layer 130 projected on the second surface S2 opposite to the third direction D3. It is noted that the first metal layer 110 may include a circuit component or a metal component structure of at least one of an electrode pad, a Bonding pad, a Routing wire or a Heat sink, and the second metal layer 130 may also include a circuit component or a metal component structure of at least one of an electrode pad, a Bonding pad or a Routing wire. In the present embodiment, a wiring layer 140 and a transistor circuit 150 may be further formed on the second surface S2 of the first insulating layer 120, wherein the wiring layer 140 may include a plurality of circuit traces. The transistor circuit 150 is electrically connected to the wiring layer 140. In some embodiments, the second metal layer 130, the wiring layer 140 and the transistor circuit 150 may be formed on the same layer on the second surface S2 of the first insulating layer 120, or formed between another plurality of insulating layers on the second surface S2 of the first insulating layer 120, so as to have different distances from the second surface S2 of the first insulating layer 120.

In the present embodiment, a second insulating layer 160 covering the second metal layer 130, the wiring layer 140, and the transistor circuit 150 is also formed on the second surface S2 of the first insulating layer 120. An electronic component 170 may be disposed on the second insulating layer 160. The electronic component 170 may be electrically connected to the first metal layer 110 and the second metal layer 130 through the conductive element 171 and the conductive element 172, but is not limited thereto. The conductive element 171 may be in the form of a Via (Via) penetrating through the first insulating layer 120 and the second insulating layer 160, and the conductive element 172 may be in the form of a Via penetrating through the second insulating layer 160, wherein the material of the

conductive elements

171, 172 may include a metal conductive material, such as tin-lead alloy. In the present embodiment, the electronic component 170 may include a PN junction (PN junction) component, a Solar cell (Solar cell), an Integrated Circuit (IC), a Light-Emitting Diode (LED) component, a Sensor (Sensor), or the like, but the disclosure is not limited thereto. In some embodiments, the PN junction element includes a tunable capacitor (varactor), such as a varactor, but not limited thereto. In some embodiments, the first metal layer 110 on the first surface S1 of the first insulating layer 120 may further be disposed or electrically connected to a passive device, a Thin film battery (Thin film battery), a sensor, or a light emitting diode, for example, but the disclosure is not limited thereto. In the present embodiment, the control circuit 180 may be disposed on the carrier 181 and electrically connected to the wiring layer 140 through the conductive material 182, so as to be electrically connected to the transistor circuit 150 through the wiring layer 140, but is not limited thereto. The Conductive material 182 may be Anisotropic Conductive Film (Anisotropic Conductive Film) or other suitable Conductive material, but is not limited thereto. In the present embodiment, the control circuit 180 is configured to provide electrical signals, such as related control signals, driving signals, etc., to the electronic component 170 through the transistor circuit 150 to control or drive the electronic component 170. Therefore, the electronic device 100 of the present embodiment may have a double-sided redistribution process layout and a structure provided with the transistor circuit 150, and the electronic component 170 disposed on the substrate may be controlled or driven by the transistor circuit 150. In an embodiment, the carrier 181 may include a Flexible Printed Circuit (FPC) or other suitable circuit board, but is not limited thereto. In other embodiments, the control circuit 180 may be electrically connected to the transistor circuit 150, but need not pass through the carrier board 181 and/or the conductive material 182.

In the embodiment, the electronic apparatus 100 may include a display device, an electromagnetic wave adjusting device, a sensing device, or a splicing device, but is not limited thereto. The electronic device 100 may be a bendable or flexible electronic device. The electronic device 100 may include a liquid crystal (liquid crystal) Light Emitting Diode (LED), and the LED may include an inorganic LED, an Organic Light Emitting Diode (OLED), a sub-millimeter light emitting diode (mini LED), a micro LED, or a quantum dot light emitting diode (QD, which may be, for example, QLED, QDLED), a fluorescent (fluorescent), a phosphorescent (phosphor), or other suitable material, and the materials may be arranged in any combination, but not limited thereto. The electromagnetic wave adjusting device can be used for receiving or transmitting electromagnetic waves, but not limited thereto. The splicing device may be, for example, a display splicing device or an electromagnetic wave adjusting device, but is not limited thereto. It should be noted that the electronic device 100 can be any permutation and combination of the foregoing, but is not limited thereto.

Fig. 2A and 2B are flow charts of a method for manufacturing an electronic device according to a first embodiment of the disclosure. Fig. 3A-3D are schematic cross-sectional views of structures at various stages during the fabrication method of fig. 2A and 2B. The following steps of the present embodiment can be implemented by corresponding one or combination of various semiconductor process means, and the structures of fig. 3A to 3D formed by the following intermediate steps can be implemented as certain specific electronic devices independently, and are not limited to the electronic devices implemented to the final steps. Referring to fig. 2A and 3A, the method of fig. 2A may result in an electronic device having an electronic structure with double-sided redistribution process routing. In step S201, a carrier substrate 301 is provided, and the carrier substrate 301 may be a hard board or a soft board, for example, but the disclosure is not limited thereto. In step S202, a first metal layer 310 having an opening 311 is formed on the carrier substrate 301. The opening 311 may be formed by a semiconductor etching process, and the first metal layer 310 may be further formed by a semiconductor etching process to form metal or circuit components such as the electrode 312, the electrode 313, the electrode 314, the electrode 315, and the electrode 316 shown in fig. 3A. In an embodiment, one or more of the

electrodes

312, 313, 314, 315, and 316 may be omitted, but is not limited thereto. In step S203, a first insulating layer 320 may be formed on the first metal layer 310 such that the first surface S1 of the first insulating layer 320 is in contact with the first metal layer 310. In step S204, a second metal layer 330 is formed on the first insulating layer 320 such that the second surface S2 of the first insulating layer 320 is in contact with the second metal layer 330. The first surface S1 is opposite to the second surface S2. It is noted that the projection of the opening 311 on the second surface S2 may overlap with the projection of the second metal layer 330 on the second surface S2. In the present disclosure, "overlap" may include complete overlap and partial overlap, if not specifically stated. In step S205, the transistor circuit 350 may be formed on the first insulating layer 320. In step S206, the wiring layer 340 may be formed on the first insulating layer 320, and the wiring layer 340 may be electrically connected to the transistor circuit 350. In step S207, a second insulating layer 360 covering the second metal layer 330, the wiring layer 340, and the transistor circuit 350 is formed on the first insulating layer 320.

Referring to fig. 2A and 3B, in step S208, the electronic component 370 is disposed on the second insulating layer 360, and the electronic component 370 is electrically connected to the transistor circuit 350, the first metal layer 310 and the second metal layer 330. The electronic component 370 may be electrically connected to the first metal layer 310 and the second metal layer 330 through the

conductive elements

371 and 372 by using a Surface Mount Technology (SMT) process, and electrically connected to the transistor circuit 350 through additional traces. The conductive element 371 may be a via penetrating through the first insulating layer 320 and the second insulating layer 360, and the conductive element 372 may also be a via penetrating through the second insulating layer 360. In step S209, the control circuit 380 is electrically connected to the wiring layer 340. The control circuit 380 may be fabricated on the carrier 381 by using a Chip On Film (COF) packaging technology or a Chip On Glass (COG) packaging technology, wherein the carrier 381 may be a Film or a Glass. The wiring layer 340 may include Fan-out wiring (Fan-out routing), and a via or an opening corresponding to the second insulating layer 360 may be formed over the wiring layer 340, but is not limited thereto. In the embodiment, the control Chip formed by the control circuit 380 and the carrier 381 may be placed on the wiring layer 340 in a Chip surface down (Chip surface down) manner, and may be electrically connected to the wiring layer 340 by using a surface soldering technique or by using an Anisotropic Conductive Film (ACF) for adhesion, but is not limited thereto. For example, the control circuit 380 can be electrically connected to the wiring layer 340 through the circuit on the carrier 381 and the conductive material 382, and electrically connected to the transistor circuit 350 through the wiring layer 340. The control circuit 380 may control or drive the electronic component 370 through the transistor circuit 350.

For example, the electronic component 370 may include an adjustable capacitor, and the control circuit 380 may adjust the capacitance value of the adjustable capacitor through the transistor circuit 350, so that the capacitance value between the first metal layer 310 and the second metal layer 330 may be adjusted correspondingly. Therefore, an electromagnetic wave Radiation element or an electromagnetic wave Radiation modulator (Radiation modulator) may be formed between the opening 311 of the first metal layer 310 and the second metal layer 330, but is not limited thereto.

However, referring to fig. 3C, in some embodiments, the step S208 may further include further disposing another electronic component 370 'on the second insulating layer 360, and the electronic component 370' may be electrically connected to the second metal layer 330. Referring to fig. 2B and 3C, in step S210, a connection layer 302 covering the electronic components 370, 370' and the control circuit 380 is formed on the second insulating layer 360, and another carrier substrate 303 is disposed on the connection layer 302. The carrier substrate 303 may be a hard or soft board, and the material of the connection layer 302 may, for example, comprise a temporary connection material. In step S211, the carrier substrate 301 is removed. The carrier substrate 301 may be removed by laser, heat or light, for example, but the disclosure is not limited thereto. In contrast, since the material of the first insulating layer 320 may include a flexible circuit board material, in order to reduce the damage to the structure and components on both sides of the first insulating layer 320 when the carrier substrate 301 is removed, the other carrier substrate 303 and the connecting layer 302 are formed on the second insulating layer 360 before the carrier substrate 301 is removed. Referring to fig. 2B and 3D, in step S212, the passive element 390 may be disposed under the first metal layer 310 and electrically connect the passive element 390 to the first metal layer 310. In step S213, the connection layer 302 and the carrier substrate 303 are removed. The connection layer 302 may be removed, for example, by laser, heat, or light, so that the carrier substrate 303 may be separated from the second insulating layer 360. In addition, steps S210 to S213 of fig. 2B can also be implemented in the structure of fig. 3B to effectively remove the carrier substrate 301 of fig. 3B.

For example, the electronic component 370 may comprise an integrated circuit, and the further electronic component 370' may comprise a solar cell. The integrated circuit may, for example, include associated modulation circuitry, such as a rectifier. The passive component 390 may be a thin film battery. Therefore, the solar cell may provide electric energy to the integrated circuit through the first metal layer 310, and provide the modulated electric energy to the second metal layer 330 after voltage or current modulation, so as to store the thin film battery, but the disclosure is not limited thereto.

Fig. 4 is a schematic cross-sectional view illustrating a structure of an electronic device according to a second embodiment of the disclosure. Fig. 4 is a schematic cross-sectional view illustrating a structure of an electronic device according to a second embodiment of the disclosure. The electronic device 400 may be an electronic structure with double-sided redistribution process wiring such that associated electronic or circuit units may be disposed on both sides of the substrate. Specifically, the electronic device 400 includes a first metal layer 410, a first insulating layer 420, a second metal layer 430, a wiring layer 440, a transistor circuit 450, a second insulating layer 460, an electronic component 470, and a control circuit 480. The transistor circuit 450 may, for example, comprise one or more transistors, and the types of the plurality of transistors may, for example, be bottom-gate transistors, top-gate transistors, or double-gate transistors. In the present embodiment, the first insulating layer 420 includes a first surface S1 and a second surface S2, wherein the first surface S1 is opposite to the second surface S2. In the present embodiment, the first insulating layer 420 may be a flexible circuit board material, but the disclosure is not limited thereto. In some embodiments, the material of the first insulating layer 420 may also be, for example, the above-mentioned rigid material, flexible material or plastic circuit board, which are not described herein again. It is noted that the transistor circuit 450 of the present embodiment may be a Die (Die) having a plurality of transistor circuits, so that the transistor circuit 450 is electrically connected to the wiring layer 440 by electrically connecting the transistor circuit 450 integrated on the Die to the wiring layer 440. For example, the transistor circuit 450 may include a substrate (not shown) and at least one transistor, the material of the substrate may include glass or other suitable materials, the at least one transistor is disposed on the substrate, and the transistor circuit 450 is electrically connected to the wiring layer 440.

In the present embodiment, the first metal layer 410 may have an opening 411, and the first metal layer 410 is formed on the first surface S1 of the first insulating layer 420. For example, the opening 411 may extend in the second direction D2, and may be a slot structure, but is not limited thereto. The second metal layer 430 may be formed on the second surface S2 of the first insulating layer 420. In the present embodiment, a projection of the opening 411 projected onto the second surface S2 in the third direction D3 may overlap a projection of the second metal layer 430 projected onto the second surface S2 in the opposite direction to the third direction D3. It is noted that the first metal layer 410 may include a circuit component or a metal component structure of at least one of an electrode pad, a wire, or a heat sink, and the second metal layer 430 may also include a circuit component or a metal component structure of at least one of an electrode pad, a pad, or a wire, but is not limited thereto. In this embodiment, a wiring layer 440 may be further formed on the second surface S2 of the first insulating layer 420, wherein the wiring layer 440 may include a plurality of circuit traces. In some embodiments, the second metal layer 430 and the wiring layer 440 may be formed on the same layer on the second surface S2 of the first insulating layer 420. In other embodiments, the second metal layer 430 and/or the wiring layer 440 may have different distances from the second surface S2 of the first insulating layer 420, respectively, and at least one insulating layer may be disposed between the second metal layer 430 and the wiring layer 440, but is not limited thereto.

In the present embodiment, a second insulating layer 460 covering the second metal layer 430 and the wiring layer 440 is further formed on the second surface S2 of the first insulating layer 420. The transistor circuit 450 and the electronic component 470 are disposed on the second insulating layer 460. The transistor circuit 450 may be electrically connected to the wiring layer 440 via the conductive member 451. The electronic component 470 can be electrically connected to the first metal layer 410 and the second metal layer 430 through the

conductors

471 and 472. The

conductive elements

451, 471 can be through holes penetrating at least a portion of the first insulating layer 420 and/or at least a portion of the second insulating layer 460, and the conductive element 472 can be through holes penetrating the second insulating layer 460, wherein the

conductive elements

451, 471, 472 can be a metal conductive material, such as tin-lead alloy. In the present embodiment, the electronic device 470 may include a PN junction device, a solar cell, an integrated circuit, a light emitting diode device, a sensor, other suitable electronic devices, or a combination thereof, but the disclosure is not limited thereto. In some embodiments, the PN junction device includes an adjustable capacitor. In addition, in some embodiments, the first metal layer 410 on the first surface S1 of the first insulating layer 420 may be further disposed or electrically connected to a passive component, a thin film battery, a sensor, a light emitting diode, or the like, but the disclosure is not limited thereto. In this embodiment, the control circuit 480 may be disposed on the carrier plate 481 and electrically connected to the wiring layer 440 via the conductive material 482 so as to be electrically connected to the transistor circuit 450 through the wiring layer 440. In the present embodiment, the control circuit 480 is used for providing electrical signals, such as related control signals, driving signals, etc., to the electronic component 470 via the transistor circuit 450 to control or drive the electronic component 470. The transistor circuit 450 may be electrically connected to the first metal layer 410 and the electronic component 470, but is not limited thereto. Therefore, the electronic device 400 of the present embodiment may have a double-sided redistribution process layout and a structure provided with the transistor circuit 450, and the electronic component 470 disposed on the substrate may be controlled or driven by the transistor circuit 450.

Fig. 5A and 5B are flowcharts illustrating a method for manufacturing an electronic device according to a second embodiment of the disclosure. Fig. 6A-6D are schematic cross-sectional views of structures at various stages during the fabrication method of fig. 5A and 5B. The following steps of the present embodiment can be implemented by corresponding one or combination of various semiconductor process means, and the structures of fig. 3A to 3D formed by the following intermediate steps can be implemented as certain specific electronic devices independently, and are not limited to the electronic devices implemented to the final steps. Referring to fig. 5A and fig. 6A, the manufacturing method of fig. 5A may produce an electronic device having a wiring structure of a double-sided redistribution process, but is not limited thereto. In step S501, a carrier substrate 601 is provided, and the carrier substrate 601 may be a hard board or a soft board, for example, but the disclosure is not limited thereto. In step S502, a first metal layer 610 having an opening 611 is formed on the carrier substrate 601. The opening 611 may be formed by, for example, a semiconductor etching process, and the first metal layer 610 may also be formed by, for example, a semiconductor etching process to form metal or circuit components such as the electrode 612, the electrode 613, the electrode 614, the electrode 615, and the electrode 616 shown in fig. 6A, but is not limited thereto. In some embodiments, one or more of the electrodes 613-616 described above may be omitted. In step S503, a first insulating layer 620 is formed on the first metal layer 610, for example, but not limited to, the first surface S1 of the first insulating layer 620 directly or indirectly contacts the first metal layer 610. In step S504, a second metal layer 630 may be formed on the first insulating layer 620, for example, the second surface S2 of the first insulating layer 620 is in direct or indirect contact with the second metal layer 630. The first surface S1 is opposite to the second surface S2. It is noted that the projection of the opening 611 on the second surface S2 may overlap with the projection of the second metal layer 630 on the second surface S2. In step S505, a wiring layer 640 is formed on the first insulating layer 620, and the wiring layer 640 is electrically connected to the transistor circuit 650. In step S506, a second insulating layer 660 covering the second metal layer 630 and the wiring layer 640 is formed on the first insulating layer 620.

Referring to fig. 5A and 6B, in step S507, the transistor circuit 650 is disposed on the second insulating layer 660 and electrically connected to the wiring layer 640. The transistor circuit 650 may be electrically connected to the wiring layer 640 through the conductive element 651 by using a surface soldering process, but is not limited thereto. The conductive member 651 may be a through hole penetrating at least a portion of the second insulating layer 660. In step S508, the electronic component 670 may be disposed on the second insulating layer 660, and the electronic component 670 is electrically connected to the transistor circuit 650, the first metal layer 610, and the second metal layer 630. The electronic component 670 may be electrically connected to the first metal layer 610 and the second metal layer 630 through the

conductive elements

671 and 672 by surface soldering technology, and is electrically connected to the transistor circuit 650 by additional traces, but is not limited thereto. The conductive member 671 may be in the form of a via penetrating through at least a portion of the first insulating layer 620 and/or at least a portion of the second insulating layer 660, and the conductive member 672 may also be in the form of a via penetrating through at least a portion of the second insulating layer 660. In step S509, the control circuit 680 may be electrically connected to the wiring layer 640. The control circuit 680, the conductive material 682 and the wiring layer 640 may be similar to the control circuit 180, the conductive material 182 and the wiring layer 140, and are not described herein again. For example, the electronic component 670 may be similar to the electronic component 170 described above and will not be described in detail herein.

However, referring to fig. 6C, in some embodiments, the step S508 may further include further disposing another electronic component 670 'on the second insulating layer 660, and the electronic component 670' is electrically connected to the second metal layer 630. Referring to fig. 5B and 6C, in step S510, a connection layer 602 covering the electronic components 370, 370', the transistor circuit 650, and the control circuit 680 is on the second insulating layer 660, and another carrier substrate 603 is disposed on the connection layer 602. Step S510 may be similar to step S210 described above, and is not described herein again.

Fig. 7 is a schematic cross-sectional view illustrating a structure of an electronic device according to a third embodiment of the disclosure. Referring to fig. 7, an electronic device 700 may be an electronic structure having a single-sided redistribution process routing such that associated electronic and circuit elements may be disposed on one side of a substrate. Specifically, the electronic device 700 may include a first metal layer 710, a first insulating layer 720, a second metal layer 730, a wiring layer 740, a transistor circuit 750, a second insulating layer 760, a PN junction element 770, and a control circuit 780. The transistor circuit 750 may, for example, include one or more transistors, and the types of the plurality of transistors may, for example, be bottom-gate transistors, top-gate transistors, or double-gate transistors. In the present embodiment, the first insulating layer 720 includes a first surface S1 and a second surface S2, wherein the first surface S1 is opposite to the second surface S2. In the present embodiment, the first insulating layer 720 may be a flexible circuit board material, but the disclosure is not limited thereto. In some embodiments, the first insulating layer 720 may also be a material such as a rigid, flexible, or plastic circuit board.

In the present embodiment, the first metal layer 710 and the second metal layer 730 may be formed on the second surface S2 of the first insulating layer 720. It is noted that the first metal layer 710 may include a circuit component or a metal component structure of at least one of an electrode, a pad, a wire, or a heat sink, and the second metal layer 730 may also include a circuit component or a metal component structure of at least one of an electrode, a pad, or a wire. In the present embodiment, a wiring layer 740 and a transistor circuit 750 may also be formed on the second surface S2 of the first insulating layer 720. The transistor circuit 750 may be electrically connected to the wiring layer 740, and the wiring layer 740 includes a plurality of circuit traces. In some embodiments, the first metal layer 710, the second metal layer 730, the wiring layer 740, and the transistor circuit 750 may be formed on the same layer on the second surface S2 of the first insulating layer 720. In other embodiments, the first metal layer 710, the second metal layer 730, and the wiring layer 740 may have different distances from the second surface S2 of the first insulating layer 720, respectively, but are not limited thereto.

In the present embodiment, a second insulating layer 760 covering the first metal layer 710, the second metal layer 730, the wiring layer 740, and the transistor circuit 750 is further formed on the second surface S2 of the first insulating layer 720. The PN junction element 770 is disposed on the first surface S1 of the first insulating layer 720 and electrically connected to the first metal layer 710 and the second metal layer 730 through the

conductive members

771, 772. The

conductive members

771, 772 may be through holes penetrating the first insulating layer 720, wherein the

conductive members

771, 772 may be metal conductive material, such as tin-lead alloy. In this embodiment, the PN junction element 770 may include an adjustable capacitor. In this embodiment, the control circuit 780 is disposed on the carrier plate 781 and electrically connected to the wiring layer 740 through the conductive material 782, so as to be electrically connected to the transistor circuit 750 through the wiring layer 740. In this embodiment, the control circuit 780 is used for providing electrical signals such as related control signals, driving signals, etc. to the PN junction device 770 through the transistor circuit 750 to control or drive the PN junction device 770. Therefore, the electronic device 700 of the present embodiment may have a single-sided redistribution process layout and be configured with the transistor circuit 750, and the PN junction element 770 disposed on the substrate may be controlled or driven by the transistor circuit 750.

Fig. 8 is a flowchart illustrating a method for manufacturing an electronic device according to a third embodiment of the disclosure. Fig. 9A-9D are schematic cross-sectional views of structures at various stages during the fabrication method of fig. 8. The following steps of the present embodiment can be implemented by corresponding one or combination of various semiconductor process means, and the structures of fig. 9A to 9D formed by the following intermediate steps can be implemented as certain specific electronic devices independently, and are not limited to the electronic devices implemented to the final steps. Referring to fig. 8 and 9A, the method of fig. 8 may result in an electronic device having an electronic structure with a single-sided redistribution process wiring. In step S801, the carrier substrate 901 is provided, and the material of the carrier substrate 901 may include the material of the above-mentioned hard board or soft board, for example, but the disclosure is not limited thereto. In step S802, a first insulating layer 920 is formed on the carrier substrate 901. In step S803, a first metal layer 910 and a second metal layer 930 may be formed on the first insulating layer 920. The first metal layer 910 and the second metal layer 930 may be formed with metal or circuit components such as pads, heat sinks, wires, electrode pads, etc. through a semiconductor etching process, for example, but the disclosure is not limited thereto. In step S804, the transistor circuit 950 is formed on the first insulating layer 920, and the transistor circuit 950 may be electrically connected to the second metal layer 930. In step S805, a wiring layer 940 is formed on the first insulating layer 920, and the wiring layer 940 is electrically connected to the transistor circuit 950. In step S806, a second insulating layer 960 covering the first metal layer 910, the second metal layer 930, the wiring layer 940, and the transistor circuit 950 is formed on the first insulating layer 920.

Referring to fig. 8 and 9B, in step S807, the control circuit 980 is electrically connected to the wiring layer 940. The control circuit 980 may be fabricated on the carrier 981 by using a Chip On Film (COF) technology or a chip on glass (COF) technology, for example, wherein the material of the carrier 981 may include film, glass, or other suitable materials. The wiring layer 940 may include a fan-out type wiring, and a via or an opening may be formed above the wiring layer 940 corresponding to the second insulating layer 960. In the present embodiment, the control chip formed by the control circuit 980 and the carrier 981 can be placed above the wiring layer 940 with the chip facing down, and the wiring layer 940 can be electrically connected by surface soldering or anisotropic conductive adhesive, but is not limited thereto. For example, the control circuit 980 may be electrically connected to the wiring layer 940 via the conductive material 982 and to the transistor circuit 950 through the wiring layer 940.

Referring to fig. 8 and 9C, in step S808, a connection layer 902 covering the control circuit 980 is formed on the second insulating layer 960, and another carrier substrate 903 is formed on the connection layer 902. The carrier substrate 903 may comprise a hard board, a soft board, or a combination thereof, and the connection layer 902 may comprise a temporary connection material, for example. In step S809, the carrier substrate 901 is removed. The carrier substrate 901 may be removed by laser, heat or light, for example, and the disclosure is not limited thereto. In this regard, since the first insulating layer 920 may include the aforementioned soft material, in order to reduce the damage to the structure and components on both sides of the first insulating layer 920 when the carrier substrate 901 is removed, another carrier substrate 903 and the connecting layer 902 may be formed on the second insulating layer 960 first, and then the carrier substrate 901 is removed, but the invention is not limited thereto. In step S810, the electronic component 970 is disposed under the first insulating layer 920 (on the first surface S1), and the electronic component 970 is electrically connected to the first metal layer 910 and the second metal layer 930. The electronic component 970 may be electrically connected to the first metal layer 910 and the second metal layer 930 through the

conductive members

971 and 972, and electrically connected to the transistor circuit 950. The

conductive members

971, 972 may be through holes penetrating at least a portion of the first insulating layer 920. In step S811, the connection layer 902 and the other carrier substrate 903 are removed. The connecting layer 902 may be removed, for example, by laser, heat, or light irradiation, and the carrier substrate 903 may be separated from the second insulating layer 960.

Fig. 10 is a schematic cross-sectional view illustrating a structure of an electronic device according to a fourth embodiment of the disclosure. Referring to fig. 10, an electronic device 1000 may include an electronic structure having a single-sided redistribution process routing such that associated electronic and circuit elements may be disposed on one side of a first insulating layer 1020. Specifically, the electronic device 1000 includes a first metal layer 1010, a first insulating layer 1020, a second metal layer 1030, a wiring layer 1040, a transistor circuit 1050, a second insulating layer 1060, an electronic component 1070 (e.g., a PN junction component), and a control circuit 1080. The transistor circuit 1050 may, for example, include one or more transistors, and the types of the plurality of transistors may, for example, be bottom-gate transistors, top-gate transistors, or double-gate transistors. In the present embodiment, the first insulating layer 1020 includes a first surface S1 and a second surface S2, wherein the first surface S1 is opposite to the second surface S2. In the embodiment, the first insulating layer 1020 may include a soft material, but the disclosure is not limited thereto. In some embodiments, the first insulating layer 1020 may also comprise a material such as a rigid, flexible, or plastic circuit board. It is noted that the transistor circuit 1050 of the present embodiment may include a substrate (not shown) and at least one transistor disposed on the substrate. The at least one transistor may be electrically connected to electronic component 1070 and/or second metal layer 1030.

In the present embodiment, the first metal layer 1010 and the second metal layer 1030 may be formed on the second surface S2 of the first insulating layer 1020. It is noted that the first metal layer 1010 may include a circuit component or a metal component structure of at least one of an electrode, a pad, a wire, or a heat sink, and the second metal layer 1030 may also include a circuit component or a metal component structure of at least one of an electrode, a pad, or a wire, but is not limited thereto. In the present embodiment, a wiring layer 1040 may be further formed on the second surface S2 of the first insulating layer 1020. In some embodiments, the first metal layer 1010, the second metal layer 1030, and the wiring layer 1040 may be formed on the same layer on the second surface S2 of the first insulating layer 1020. In other embodiments, the first metal layer 1010, the second metal layer 1030, and the wiring layer 1040 may have different distances from the second surface S2 of the first insulating layer 1020, respectively.

In this embodiment, a second insulating layer 1060 covering the first metal layer 1010, the second metal layer 1030, and the wiring layer 1040 is further formed on the second surface S2 of the first insulating layer 1020. The transistor circuit 1050 is provided over the second insulating layer 1060, and the transistor circuit 1050 is electrically connected to the wiring layer 1040 via a conductive member 1051. The conductive member 1051 may be a through hole penetrating the second insulating layer 1060. An electronic component 1070 (e.g., a PN junction component) is disposed on the first surface S1 of the first insulating layer 1020. The

conductors

1071, 1072 may be through holes penetrating the first insulating layer 1020, wherein the

conductors

1071, 1072 may be a metal conductive material, such as a tin-lead alloy. In the present embodiment, the control circuit 1080 is disposed on the carrier 1081, and is electrically connected to the wiring layer 1040 through the conductive material 1082, so as to be electrically connected to the transistor circuit 1050 through the wiring layer 1040.

Fig. 11 is a flowchart illustrating a method for manufacturing an electronic device according to a fourth embodiment of the disclosure. Fig. 12A-12D are schematic cross-sectional views of structures at various stages during the fabrication method of fig. 11. The following steps of the present embodiment can be implemented by corresponding one or combination of various semiconductor process means, and the structures of fig. 12A to 12D formed by the following intermediate steps can be implemented as certain specific electronic devices independently, and are not limited to the electronic devices implemented to the final steps. Referring to fig. 11 and 12A, the method of fig. 11 may result in an electronic device having an electronic structure with a single-sided redistribution process wiring. In step S1101, a carrier substrate 1201 is provided, and the carrier substrate 1201 may be, for example, a hard board or a soft board, but the disclosure is not limited thereto. In step S1102, a first insulating layer 1220 is formed on the carrier substrate 1201. In step S1103, a first metal layer 1210 and a second metal layer 1230 are formed on the first insulating layer 1220. In step S1104, a wiring layer 1240 is formed on the first insulating layer 1220, and the wiring layer 1240 is electrically connected to the transistor circuit 1250. In step S1105, a second insulating layer 1260 covering the first metal layer 1210, the second metal layer 1230, and the wiring layer 1240 is formed on the first insulating layer 1220.

Referring to fig. 11 and 12B, in step S1106, a transistor circuit 1250 is disposed on the second insulating layer 1260 and electrically connected to the wiring layer 1240. Transistor circuit 1250 is electrically connected to wiring layer 1240 via conductors 1251. In step S1107, the control circuit 1280 is electrically connected to the wiring layer 1240. Referring to fig. 11 and 12C, in step S1108, a connection layer 1202 covering the control circuit 1280 and the transistor circuit 1250 is formed on the second insulating layer 1260, and another carrier substrate 1203 is formed on the connection layer 1202. In step S1109, the carrier substrate 1201 is removed. In step S1110, an electronic device 1270 (e.g., a PN junction device of an adjustable capacitor) is disposed under the first insulating layer 1220 (on the first surface S1), and the electronic device 1270 is electrically connected to the first metal layer 1210 and the second metal layer 1230. In step S1111, the connection layer 1202 and the other carrier substrate 1203 are removed. The connection layer 1202 may be removed, for example, by laser, heat, or light, such that the carrier substrate 1203 may be separated from the second insulating layer 1260.

Fig. 13 is a schematic cross-sectional view illustrating a structure of an electronic device according to a fifth embodiment of the disclosure. Referring to fig. 13, an electronic device 1300 may include an electronic structure having a single-sided redistribution process routing such that associated electronic, circuit elements may be disposed on one side of a first insulating layer 1320. Specifically, the electronic device 1300 includes a first metal layer 1310, a first insulating layer 1320, a second metal layer 1330, a wiring layer 1340, transistor circuits 1350, a second insulating layer 1360, electronic components 1370 (e.g., PN junction components), and control circuitry 1380.

Specifically, the second metal layer 1330 and the wiring layer 1340 are formed on the second surface S2 of the first insulating layer 1320. In some embodiments, the second metal layer 1330 and the wiring layer 1340 may be formed on the same layer or different layers on the second surface S2 of the first insulating layer 1320 in this embodiment, a second insulating layer 1360 covering the second metal layer 1330 and the wiring layer 1340 is further formed on the second surface S2 of the first insulating layer 1320, and the first metal layer 1310 having the opening 1311 is formed on the second insulating layer 1360. It is noted that the projection of the opening 1311 on the second surface S2 may overlap the projection of the second metal layer 1330 on the second surface S2. In this embodiment, transistor circuit 1350 is electrically connected to second metal layer 1330 via conductive element 1351. In the present embodiment, the electronic component 1370 is disposed on the first surface S1 of the first insulating layer 1320, and may also be electrically connected to the first metal layer 1310 and the second metal layer 1330 through the

conductive members

1371 and 1372.

In the present embodiment, the control circuit 1380 is used for providing electrical signals such as related control signals, driving signals, etc. to the electronic component 1370 through the transistor circuit 1350 to control or drive the electronic component 1370. For example, the electronic component 1370 may include a PN junction device, and the control circuit 1380 may adjust the capacitance through the transistor circuit 1350, so that the capacitance between the first metal layer 1310 and the second metal layer 1330 may be adjusted accordingly. An electromagnetic wave radiation element or an electromagnetic wave radiation modulator may be formed between the opening 1311 of the first metal layer 1310 and the second metal layer 1330, for example. Fig. 14 is a schematic cross-sectional view illustrating a structure of an electronic device according to a sixth embodiment of the disclosure. Referring to fig. 14, an electronic device 1400 may be an electronic structure having a single-sided redistribution process routing such that associated electronic and circuit elements may be disposed on one side of a first insulating layer 1420. Specifically, the electronic device 1400 includes a first metal layer 1410, a first insulating layer 1420, a second metal layer 1430, a wiring layer 1440, a transistor circuit 1450, a second insulating layer 1460, an electronic component 1470, and a control circuit 1480.

In the present embodiment, the transistor circuit 1450 can be electrically connected to the second metal layer 1430 through the conductive element 1452. The conductive member 1452 may be in the form of a through hole penetrating at least a portion of the first insulating layer 1420. In this embodiment, the control circuit 1480 is configured to provide electrical signals such as control signals, driving signals, etc. to the electronic device 1470 via the transistor circuit 1450 to control or drive the electronic device 1470. In one embodiment, the control circuit 1480 may be electrically connected to the electronic component 1470 through the second metal layer 1430, the transistor circuit 1450, and/or the wiring layer 1440.

Fig. 15 is a schematic cross-sectional view illustrating a structure of an electronic device according to a seventh embodiment of the disclosure. Referring to fig. 15, an electronic device 1500 may be an electronic structure having a single-sided redistribution process wiring. Specifically, the electronic device 1500 may include a first metal layer 1510, a first insulating layer 1520, a second metal layer 1530, a wiring layer 1540, transistor circuits 1550, a second insulating layer 1560, electronic components 1570, and control circuits 1580.

In the present embodiment, the transistor circuit 1550 may be formed on the first surface S1 of the first insulating layer 1520 and may be electrically connected to the PN junction element 1570 through the conductive element 1553. A conductive element 1553 is formed on the first surface S1 of the first insulating layer 1520 and connects the transistor circuit 1550 and the PN junction element 1570, wherein the conductive element 1553 may comprise a metal conductive material. In one embodiment, the control circuit 1580 may be electrically connected to the electronic component 1570 through the second metal layer 1530, the transistor circuit 1550, and/or the wiring layer 1540, but is not limited thereto.

In summary, the electronic device and the manufacturing method thereof of the present disclosure can provide an electronic structure having a single-sided or multi-sided redistribution process wiring and a transistor circuit, and can control or drive the electronic component disposed on the substrate through the transistor circuit, wherein the single-sided or multi-sided redistribution process wiring structure of the present disclosure can be implemented through a structure with fewer layers, so as to effectively reduce the size and the manufacturing cost of the electronic device.

Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present disclosure, and not for limiting the same; while the present disclosure has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the disclosed embodiments.

Claims

1. An electronic device, comprising:

a first insulating layer comprising a first surface and a second surface opposite the first surface;

a first metal layer having an opening and formed on the first surface of the first insulating layer;

a second metal layer formed on the second surface, and a projection of the opening on the second surface overlaps a projection of the second metal layer on the second surface; and

and the electronic component is electrically connected with the first metal layer and the second metal layer, and is arranged on the second surface of the first insulating layer.

2. The electronic device of claim 1, further comprising:

the transistor circuit is electrically connected with the electronic component;

a wiring layer formed on the second surface and electrically connected to the transistor circuit; and

and the control circuit is electrically connected with the wiring layer so as to be electrically connected with the transistor circuit through the wiring layer.

3. An electronic device, comprising:

a first metal layer formed over the second surface;

a second metal layer formed on the second surface;

a PN junction element disposed on the first surface and electrically connected to the first metal layer and the second metal layer, wherein the PN junction element comprises an adjustable capacitor; and

and the transistor circuit is electrically connected with the second metal layer.

4. The electronic device according to claim 3, wherein the first metal layer has an opening, and the first metal layer is formed over the second metal layer, wherein a projection of the opening on the second surface overlaps a projection of the second metal layer on the second surface.

5. A method of manufacturing an electronic device, comprising:

providing a bearing substrate;

forming a first metal layer with an opening on the bearing substrate;

forming a first insulating layer on the first metal layer so that a first surface of the first insulating layer is in contact with the first metal layer;

forming a second metal layer on the first insulating layer so that a second surface of the first insulating layer is in contact with the second metal layer, wherein the first surface is opposite to the second surface, and a projection of the opening on the second surface overlaps a projection of the second metal layer on the second surface; and

and arranging an electronic component on the second surface of the first insulating layer, wherein the electronic component is electrically connected with the first metal layer and the second metal layer.

6. The manufacturing method according to claim 5, further comprising:

forming a transistor circuit on the first insulating layer;

forming a wiring layer on the first insulating layer and electrically connecting the wiring layer to the transistor circuit;

forming a second insulating layer covering the second metal layer, the transistor circuit, and the wiring layer on the first insulating layer;

arranging the electronic component on the second insulating layer and electrically connecting the electronic component with the transistor circuit; and

and electrically connecting the control circuit with the wiring layer.

7. The manufacturing method according to claim 5, characterized by further comprising:

forming a wiring layer on the first insulating layer;

forming a second insulating layer covering the second metal layer and the wiring layer on the first insulating layer;

arranging a transistor circuit on the second insulating layer and electrically connecting the transistor circuit to the wiring layer;

and electrically connecting the control circuit with the wiring layer.

8. A method of manufacturing an electronic device, comprising:

providing a bearing substrate;

forming a first insulating layer on the bearing substrate so that a first surface of the first insulating layer contacts the bearing substrate;

forming a first metal layer and a second metal layer on the first insulating layer so that a second surface of the first insulating layer is in contact with the first metal layer and the second metal layer, wherein the first surface is opposite to the second surface;

electrically connecting a transistor circuit to the second metal layer;

removing the bearing substrate; and

disposing a PN junction device having an adjustable capacitance on the first insulating layer, and electrically connecting the PN junction device to the first metal layer and the second metal layer.

9. The method of manufacturing of claim 8, further comprising, prior to the step of removing the carrier substrate:

forming the transistor circuit on the first insulating layer;

forming a second insulating layer covering the first metal layer, the second metal layer, the transistor circuit, and the wiring layer on the first insulating layer; and

and electrically connecting the control circuit with the wiring layer.

10. The method of manufacturing of claim 8, further comprising, prior to the step of removing the carrier substrate:

forming a wiring layer on the first insulating layer;

forming a second insulating layer covering the first metal layer, the second metal layer, and the wiring layer on the first insulating layer;

disposing the transistor circuit on the second insulating layer and electrically connecting the transistor circuit to the wiring layer; and

and electrically connecting the control circuit with the wiring layer.