CN112309976A - Manufacturing method of bidirectional power device - Google Patents

Manufacturing method of bidirectional power device Download PDF

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CN112309976A
CN112309976A CN202011165967.7A CN202011165967A CN112309976A CN 112309976 A CN112309976 A CN 112309976A CN 202011165967 A CN202011165967 A CN 202011165967A CN 112309976 A CN112309976 A CN 112309976A
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trench
gate
dielectric layer
forming
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CN112309976B (en
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杨彦涛
张邵华
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Hangzhou Silan Microelectronics Co Ltd
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Hangzhou Silan Microelectronics Co Ltd
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Priority to PCT/CN2021/089607 priority patent/WO2022088627A1/en
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Abstract

The application discloses a manufacturing method of a bidirectional power device, which comprises the following steps: forming a first doped region in the semiconductor layer; forming a plurality of grooves in the first groove region, wherein the grooves of the first groove region are positioned in the first doping region and divide the first doping region into a first sub-doping region and a second sub-doping region which are alternated; forming a gate dielectric layer covering the lower side walls of the plurality of grooves of the first groove area; forming a control gate in contact with the gate dielectric layer at the lower part of the plurality of trenches in the first trench region; forming a shielding dielectric layer which covers the upper side walls of the plurality of grooves of the first groove region and the surfaces of the control gates; and forming a shielding grid which is in contact with the shielding medium layer on the upper parts of the plurality of trenches in the first trench region, wherein the shielding medium layer separates the control grid from the shielding grid. The manufacturing method utilizes the groove to divide the first doped region into the first type sub-doped region and the second type sub-doped region which are alternated, so that a source region and a drain region of the bidirectional power device are formed, and the area of the device is reduced.

Description

Manufacturing method of bidirectional power device
Technical Field
The present disclosure relates to the field of semiconductor manufacturing technologies, and more particularly, to a method for manufacturing a bidirectional power device.
Background
Bidirectional power devices are widely used in charging devices having a secondary charging function. Taking the lithium battery charging and discharging device as an example, when the lithium battery charging and discharging device continuously supplies power to the terminal device to a certain extent, the lithium battery charging and discharging device needs to be prevented from over-discharging so as to prevent the terminal device from stopping running, and the lithium battery needs to be charged in time. In the process of charging the lithium battery, the lithium battery also needs to supply power to the terminal equipment, and meanwhile, the lithium battery is prevented from being overcharged. Therefore, in order to manage and control the charge/discharge state of the lithium battery, a charge/discharge protection circuit having a bidirectional switch for controlling current conduction is generally used.
As shown in fig. 1, in the first charge/discharge protection circuit, two drain-connected single planar gate NMOS transistors M1 and M2 were used as bidirectional switches. When charging is performed, a high voltage is applied to the gate G1 of M1 to turn on M1, and a low voltage is applied to the gate G2 of M2 to turn off M2, and at this time, current flows from the source S2 of M2 to the drain of M2 through the parasitic diode D2 of M2, and then flows from the drain of M1 to the source S1 of M1. When discharging, a low voltage is applied to gate G1 of M1, turning off M1, and a high voltage is applied to gate G2 of M2, turning on M2. At this time, the current flows from the source S1 of M1 to the drain of M1 through the parasitic diode D1 of M1, and then flows from the drain of M2 to the source S2 of M2. However, the MOS process using the planar gate structure requires a sufficient area to meet the requirement of higher withstand voltage, and the device has low on-state efficiency and large power consumption.
Therefore, it is desirable to further optimize the structure of the bidirectional power device, so that the bidirectional power device has smaller area and higher performance.
Disclosure of Invention
In view of the above problems, an object of the present invention is to provide a method for manufacturing a bidirectional power device, in which a trench is used to separate a first doped region into a first type sub-doped region and a second type sub-doped region alternately, so as to form a source region and a drain region of the bidirectional power device, thereby reducing the area of the device.
The manufacturing method of the bidirectional power device provided by the embodiment of the invention comprises the following steps: forming a first doped region in the semiconductor layer; forming a plurality of grooves in a first groove region, wherein the grooves of the first groove region are positioned in the first doping region and divide the first doping region into a first sub-doping region and a second sub-doping region which are alternated; forming a gate dielectric layer covering the lower side walls of the plurality of grooves of the first groove area; forming a control gate in contact with the gate dielectric layer at the lower part of the plurality of trenches in the first trench region; forming a shielding dielectric layer which covers the upper side walls of the plurality of grooves of the first groove region and the surfaces of the control gates; and forming a shielding grid which is in contact with the shielding medium layer on the upper parts of the plurality of trenches in the first trench region, wherein the shielding medium layer separates the control grid from the shielding grid.
Optionally, in a case where one of the first type sub-doping region and the second type sub-doping region serves as a source region, the other of the first type sub-doping region and the second type sub-doping region serves as a drain region, and the source region and the drain region may be interchanged.
Optionally, the semiconductor layer includes a substrate and an epitaxial layer on the substrate, and the manufacturing method further includes forming a conductive channel extending from a surface of the epitaxial layer to the substrate, wherein the conductive channel is in contact with the substrate.
Optionally, the step of forming the conductive channel comprises: forming a doped region in the epitaxial layer; and annealing the doped region so that the doped region is in contact with the substrate, wherein the doping type of the doped region is the same as that of the epitaxial layer.
Optionally, the process of forming the first doped region and the doped region includes: one or more of implantation doping, diffusion source doping and coating doping.
Optionally, the step of forming the conductive channel comprises: forming a recess extending from the epitaxial layer surface toward the substrate, a portion of the substrate being exposed by the recess; and filling a conductive material in the groove.
Optionally, forming a trench in a second trench region, the trench of the second trench region being located in the semiconductor layer and being separated from the first doped region; the gate dielectric layer is further formed on the side wall of the groove of the second groove region; the control gate is further formed in the trench of the second trench region, the trench of the first trench region is communicated with the trench of the second trench region, and the control gate in the trench of the first trench region is connected with the control gate in the trench of the second trench region.
Optionally, the method further comprises: forming a first contact region in the first type doped region; forming a second contact region in the second type sub-doping region; and forming a third contact region in the semiconductor layer.
Optionally, forming a channel region in the semiconductor layer adjacent to the control gate is further included.
Optionally, the method further comprises: forming a covering dielectric layer on the surface of the semiconductor layer; and forming a substrate electrode, a first contact electrode, a second contact electrode, a first gate electrode and a second gate electrode which penetrate through the covering dielectric layer, wherein the substrate electrode is connected with the third contact area, the first contact electrode is connected with the first contact area, the second contact electrode is connected with the second contact area, the first gate electrode is connected with the control grid, and the second gate electrode is connected with the shielding grid.
Optionally, the first gate electrode is connected to the second gate electrode to receive the same control voltage.
Optionally, the first gate electrode is electrically isolated from the second gate electrode to receive different control voltages.
Optionally, before the step of forming the capping dielectric layer on the surface of the semiconductor layer, and after the step of forming the shielding gate in contact with the shielding dielectric layer on the upper portion of the plurality of trenches in the first trench region, the manufacturing method further includes: removing a part of the shielding gate in the plurality of trenches of the first trench region; and forming a blocking structure in the plurality of grooves of the first groove area, wherein the blocking structure is positioned between the shielding gate and the covering dielectric layer, the second gate electrode further penetrates through the blocking structure, and the surfaces of the first contact electrode, the second contact electrode, the first gate electrode, the second gate electrode and the substrate electrode are flush with the covering dielectric layer.
Optionally, the thickness of the shielding dielectric layer is greater than the thickness of the gate dielectric layer.
Optionally, the thickness of the shielding dielectric layer on the surface of the control gate is greater than the thickness of the shielding dielectric layer covering the upper sidewalls of the plurality of trenches of the first trench region.
Optionally, the thickness range of the gate dielectric layer includes
Figure BDA0002745781870000031
Optionally, the thickness range of the shielding dielectric layer on the control gate surface includes
Figure BDA0002745781870000032
Optionally, the thickness range of the shielding dielectric layer covering the upper sidewalls of the plurality of trenches of the first trench region includes
Figure BDA0002745781870000041
Optionally, the depth of the plurality of trenches in the first trench region and the second trench region ranges from 0.1 μm to 50 μm.
Optionally, the distance from the surface of the control gate in the first trench region to the surface of the semiconductor layer is 0.1-49 μm.
Optionally, when the bidirectional power device is turned off, the shield gate depletes charges in the first sub-doped region and the second sub-doped region through the shield dielectric layer, so as to improve a withstand voltage characteristic of the bidirectional power device.
According to the manufacturing method of the bidirectional power device provided by the embodiment of the invention, the first doped region is formed in the epitaxial layer, the first doped region is divided into the first sub-doped region and the second sub-doped region which are alternated by the groove, and the first contact region and the second contact region are respectively formed in the first sub-doped region and the second sub-doped region, so that the two doped regions of the bidirectional power device are formed, the two doped regions are a source region and a drain region, and the area of the device is reduced.
More specifically, the first doped region is typically deeper, and higher diffusion temperatures and longer diffusion times are required to achieve deeper junction depths. Therefore, the first doping region is formed in the first step of the manufacturing method according to the requirements of product parameters, and the requirements of product structures and parameters can be realized by selecting proper doping conditions. Under the condition that the junction depth requirement of the first doped region is shallow, the first doped region can be formed without the first step of the manufacturing method, and the first doped region can also be annealed in the annealing process of other doped regions in the subsequent manufacturing method, so that the requirements of the junction depth and parameters required by the device structure are met.
Furthermore, by forming the control gates and the shielding gates in the plurality of grooves, when the bidirectional power device is cut off, the shielding gates deplete charges in the source region and the drain region through the shielding dielectric layer, and the voltage resistance of the device is improved; in the case of conduction of the bidirectional power device, the source region and/or the drain region and the channel region provide a low-impedance conduction path.
Furthermore, the control gate and the shielding gate in the device structure are separated from each other, the control gate in the first groove region and the control gate in the second groove region are connected and are led out through the electrodes, the shielding gate in the first groove region is led out through the electrodes, the connection between the shielding gate and the control gate can be realized through the leading-out electrodes (a structure similar to single polycrystal is formed), the shielding gate and the control gate can be isolated through the leading-out electrodes for separating the shielding gate from the control gate (namely, the upper section of polycrystal is independently connected), the electric field of the upper section is controlled, the independent control of the shielding gate is realized, and the shielding effect can be flexibly adjusted according to needs.
Furthermore, the body resistance of the device is reduced through the conductive channel connected with the substrate, and the performance of the bidirectional power device is improved.
Further, when the bidirectional power device is conducted, the substrate electrode connected with the substrate is in short circuit with one of the first contact electrode and the second contact electrode, and bidirectional selection of the current direction is achieved. Under the condition that the substrate electrode is in short circuit with the first contact electrode, current flows to the first contact electrode from the second contact electrode through the second type sub-doping area, the channel area and the first type sub-doping area in sequence; under the condition that the substrate electrode is in short circuit with the second contact electrode, current flows to the second contact electrode from the first contact electrode through the first type sub-doping area, the channel area and the second type sub-doping area in sequence.
Further, the channel length, and thus the channel resistance, may be reduced by reducing the width of the trench.
Furthermore, the device adopts a longitudinal control grid field structure, makes full use of a charge balance mechanism, and effectively improves the conduction efficiency and reduces the chip size by making the drift region resistance small under the condition of meeting the withstand voltage requirement.
Furthermore, the substrate electrode, the first contact electrode, the second contact electrode, the first gate electrode, the second gate electrode and the covering dielectric layer of the device are flush with each other, so that the requirement of a subsequent planarization process is facilitated.
Further, in the case that the control gate and the shield gate are located in the same trench, for example, in the first trench region, since the vertical depth of the entire trench is implemented at one time, the vertical distance from the central line of the control gate extending in the substrate thickness direction to the inner boundaries of the shield dielectric layers located on the two side walls of the trench is the same, and the vertical distance from the central line of the control gate extending in the substrate thickness direction to the outer boundaries of the shield dielectric layers located on the two side walls of the trench is the same, that is, the control gate is located right below the shield gate.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description only relate to some embodiments of the present application and are not limiting on the present application.
Fig. 1 shows a circuit schematic of a prior art bi-directional power device.
Fig. 2 shows a circuit schematic of a bi-directional power device of an embodiment of the invention.
Fig. 3a to 3l are block diagrams illustrating a method of manufacturing a bidirectional power device according to a first embodiment of the present invention at some stages.
Fig. 4 is a block diagram illustrating a method of manufacturing a bi-directional power device at some stages according to a second embodiment of the present invention.
Fig. 5a to 5d are block diagrams illustrating a method of manufacturing a bidirectional power device according to a third embodiment of the present invention at some stages.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.
It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.
If for the purpose of describing the situation directly on another layer, another area, the expressions "directly on … …" or "on … … and adjacent thereto" will be used herein.
In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
The present invention may be embodied in various forms, some examples of which are described below.
Fig. 2 shows a circuit schematic of a bi-directional power device of an embodiment of the invention.
The bidirectional power device of the embodiment of the invention is formed by one transistor and has a bidirectional conduction function. As shown in fig. 2, the bidirectional power device includes: a substrate Sub, two output poles S1 and S2 located on the substrate Sub, and two parasitic body diodes D1 and D2. When the output electrode S2 and the substrate Sub are in short circuit, a high voltage is applied to the grid G, the voltage is higher than the threshold voltage of the bidirectional power device, the bidirectional power device is conducted, and current flows from the output electrode S1 to the output electrode S2; when the output electrode S1 and the substrate Sub are in short circuit, a high voltage is applied to the grid G, the voltage is higher than the threshold voltage of the bidirectional power device, the bidirectional power device is conducted, and current flows from the output electrode S2 to the output electrode S1; when the substrate Sub is connected to zero voltage, a low voltage is applied to the gate G, and the voltage is lower than the threshold voltage, so that the bidirectional power device is turned off. In the embodiment of the present invention, the bidirectional power device is a trench type device, and may be a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), an IGBT device, or a diode. However, the present invention is not limited thereto.
Fig. 3a to 3l are block diagrams illustrating a method of manufacturing a bidirectional power device according to a first embodiment of the present invention at some stages. It should be noted that the structure of each step of the structure diagram disclosed in this embodiment is not necessarily in a cross section, and may be placed in different regions and directions of a product through a specific design according to the requirements of a product layout, where the illustration diagram only includes 4 trenches, a source region and a drain region, and in an actual product, the number of the trenches, the source region and the drain region may be changed, and when one of the first-type sub-doped region and the second-type sub-doped region is used as a source region, the other is used as a drain region, that is, through different working and application occasions, the source region and the drain region of the structure may be interchanged. In the embodiment of the present disclosure, in order to facilitate understanding of the forming process of the device structure in each step in the embodiment process, the main structure of the device is shown in a cross section in the embodiment of the present disclosure, but it is not intended to limit the claims, and any person skilled in the art may make possible changes and modifications without departing from the spirit and scope of the embodiment, so the scope of the embodiment should be determined by the scope defined by the claims of the present disclosure.
In the present embodiment, the manufacturing process starts with a semiconductor layer having a specific doping type, as shown in fig. 3a, the semiconductor layer includes a substrate 101 and an epitaxial layer 110 located on the substrate 101, wherein the substrate 101 includes a silicon substrate, a silicon germanium substrate, a group iii-v compound substrate or other semiconductor material substrates known to those skilled in the art, and a silicon substrate is used in the present embodiment. More specifically, the silicon substrate employed in the present embodiment may be formed with semiconductor devices such as MOS field effect transistors, IGBT insulated gate field effect transistors, schottky, and the like.
The semiconductor layer having a specific doping type refers to an N-type or P-type substrate 101 doped with a certain amount of impurities according to product characteristics and an N-type or P-type epitaxial layer 110 having a certain resistivity and thickness. For example, in the case that the bidirectional power device is an NMOS transistor, the doping types of the substrate 101 and the epitaxial layer 110 are P-type; in the case where the bidirectional power device is a PMOS, the doping types of the substrate 101 and the epitaxial layer 110 are N-type.
Further, a first doped region 120 is formed in the epitaxial layer 110, as shown in fig. 3 a.
In this step, the first doped region 120 is formed by one or more of implantation doping, diffusion source doping and coating doping, wherein the implantation energy is 20 to 800KeV and the implantation dose is 1E11 to 1E16cm2The annealing temperature is 600-1200 ℃.
In this embodiment, the bidirectional power device has a first trench region 103 and a second trench region 104, the first doped region 120 is located in the first trench region 103, and the doping type is opposite to that of the epitaxial layer 110, for example, in the case that the bidirectional power device is a PMOS transistor, the doping type of the first doped region 120 is P-type, and the doping impurities generally adopt B +; in the case where the bidirectional power device is an NMOS, the doping type of the first doped region 120 is an N type, and the doping impurity is usually As + or P +. The first trench region 103 is separated from the second trench region 104, and the second trench region 104 is located in the epitaxial layer 110.
Further, a plurality of trenches 111a to 111d are formed as shown in fig. 3 b.
In this step, for example, a barrier layer 10 is formed on the surface of the epitaxial layer 110 by using thermal oxidation or deposition, the barrier layer 10 is selectively removed by photolithography and etching processes to form an opening 11, and then the semiconductor layer is etched through the opening 11 to form a trench, and the region reserved in the barrier layer 10 is not formed with a trench.
Fig. 3b is a cross-sectional view showing a total of 4 grooves, including the groove 111a, the groove 111b, the groove 111c, and the groove 111 d. The trenches 111a, 111c, and 111d are located in the first trench region 103, the bottoms of the trenches 111a, 111c, and 111d are located in the epitaxial layer 110, and the trench 111b is located in the second trench region 104. Specifically, the trench 111a is located in the first doping region 120, and the trenches 111d and 111c are located at the boundary of the first doping region 120, and the three trenches divide the first doping region 120 into a first sub-doping region 121 and a second sub-doping region 122. The trench 111b is located in the epitaxial layer 110 and is separated from the first doped region 120. The trench 111c and the trench 111d are respectively located at two sides of the first doped region 120 and are in contact with the first doped region 120, for example, the trench 111c is in contact with the second-type sub-doped region 122, and the trench 111d is in contact with the first-type sub-doped region 121. The groove 111c is located between the grooves 111a and 111 b. In a plane perpendicular to the thickness direction of the substrate 101, the trench 111a, the trench 111d, the trench 111c in the first trench region 103 and the trench 111b in the second trench region are communicated, for example, sequentially in an "S" shape, but the implementation of the present invention is not limited thereto, and one skilled in the art can separate at least two trenches as needed.
In the present embodiment, the widths of the plurality of trenches 111a to 111d are determined according to the product structure and the process capability, and the depths h1 of the plurality of trenches 111a to 111d are determined according to the withstand voltage of the product and the like. Specifically, the width of the plurality of grooves 111a to 111d ranges from 0.05 to 5 μm, and the depth h1 ranges from 0.1 to 50 μm. However, the embodiments of the present invention are not limited thereto, and those skilled in the art may match the depth h1 and the width of the trenches 111a to 111d according to the conditions of epitaxy, withstand voltage, doping, gate oxide thickness, etc. of the product. Those skilled in the art can make other arrangements to the number of trenches in the first trench region 103 as required, so that the plurality of trenches separate the first doped region 120 into the alternating first-type sub-doped regions 121 and second-type sub-doped regions 122.
Further, a channel region 130 is formed in the epitaxial layer 110 through the bottom of the plurality of trenches 111a to 111d, as shown in fig. 3 c.
In this step, for example, the bottom of the plurality of trenches 111a to 111d is first doped through the opening 11 of the barrier layer 10 to form the channel region 130 in the epitaxial layer 110, and then the barrier layer 10 is removed. For example, a zero angle implantation process is used to form a channel region 130 at the bottom of the trenches 111a to 111d for adjusting the threshold voltage of the device, wherein the implantation energy is 20 to 800KeV and the implantation dose is 1E11 to 1E16cm2The annealing temperature is 600-1200 ℃.
In the present embodiment, the channel region 130 is in contact with the first-type sub-doping region 121 and the second-type sub-doping region 122, respectively, and the doping types of the channel region 130 and the first-type sub-doping region 121 and the second-type sub-doping region 122 are the same. For example, in the case that the bidirectional power device is a PMOS transistor, the doping type of the channel region 130 is P-type, and the doping impurities generally adopt B +; in the case where the bidirectional power device is an NMOS, the doping type of the channel region 130 is an N type, and the doping impurity is usually As + or P +.
Further, a first dielectric layer 141a is formed on the inner surfaces of the trenches 111a to 111d, the surface of the epitaxial layer 110, the surface of the first type sub-doping region 121 and the surface of the second type sub-doping region 122, as shown in fig. 3 d.
In this step, the first dielectric layer 141a is formed, for example, by using one or a combination of various processes such as an oxide growth process, a chemical vapor deposition process, LPCVD, SACVD, HTO, and SRO. In some preferred embodiments, the first dielectric layer 141a is formed by an oxidation growth process, and in a subsequent step, the first dielectric layer 141a will form the gate dielectric layer 141. Wherein, the first isThe thickness T1 of the dielectric layer 141a should be considered in combination with the threshold voltage required for the product, the depth of the trench in the device structure, the doping concentration of the first doped region 120 and the junction depth, and the range of T1 includes
Figure BDA0002745781870000091
Further, a first conductive layer 142a is formed on the first dielectric layer 141a on the surface of the epitaxial layer 110 and in the plurality of trenches 111a to 111d, as shown in fig. 3 e.
In this step, the first conductive layer 142a is formed, for example, using a deposition process such that the first conductive layer 142a fills the plurality of trenches 111a to 111d, and the first conductive layer 142a and the first dielectric layer 141a are in contact with each other. The material of the first conductive layer 142a includes in-situ doped polysilicon. In some other embodiments, polysilicon that is not doped with impurities may be deposited first, followed by implantation of doped impurities. In the subsequent steps, the first conductive layer 142a will form the control gate 142.
In this embodiment, in the case that the bidirectional power device is a PMOS transistor, the doping type of the first conductive layer 142a is P-type; in the case that the bidirectional power device is an NMOS, the doping type of the first conductive layer 142a is an N type.
Further, the first conductive layer 142a on the surface of the first dielectric layer 141a is removed, and the first conductive layer 142a in the trench of the first trench region 103 is selectively removed, and the remaining first conductive layer 142a forms the control gate 142, as shown in fig. 3 f.
In this step, for example, a combination of one or more of dry etching, wet etching and CMP processes is firstly used to remove the first conductive layer 142a outside the trenches 111a to 111d, so that the first dielectric layer 141a on the surface of the epitaxial layer 110 is exposed, and the first conductive layer 142a in the trenches 111a to 111d is flush with the first dielectric layer 141a on the surface of the epitaxial layer 110. Then, by photolithography and etching processes, the first conductive layer 142a in the trenches 111a, 111c, and 111d of the first trench region 103 is selectively removed, so that the depth of the first conductive layer 142a in the trenches 111a, 111c, and 111d of the first trench region 103 from the surface of the epitaxial layer 110 is h 2. The remaining first conductive layer 142a forms the control gate 142 such that the control gate 142 is located in the lower portions of the trenches 111a, 111c, and 111d of the first trench region 103 and the trench 111b of the second trench region 104, respectively. Wherein the control gate in the trench of the first trench region 103 is connected to the control gate in the trench of the second trench region 104.
In the present embodiment, the depth h2 of the control gate 142 in the trench 111a, the trenches 111c and 111d of the first trench region 103 from the surface of the epitaxial layer 110 needs to be matched in combination with the epitaxy, the withstand voltage, the doping, the gate oxide thickness, etc. of the product, and the depth h2 ranges from 0.1 μm to 49 μm. In this embodiment, the first dielectric layer 141a is remained after the formation of the control gate 142, so that the whole process is simple.
In some other embodiments, after forming the control gate 142, a wet process or the like may be further employed to remove the first dielectric layer 141a on the sidewalls of the trenches 111a, 111c and 111d of the first trench region 103 and the surface of the epitaxial layer 110.
Further, a second dielectric layer 143a is formed on the sidewalls of the trenches 111a, 111c and 111d in the first trench region 103, the surface of the control gate 142, and the first dielectric layer 141a on the surface of the epitaxial layer 110, as shown in fig. 3 g.
In this step, for example, an oxide growth process, a chemical vapor deposition process: one or more of LPCVD, SACVD, HTO, and SRO processes may be combined to form second dielectric layer 143 a. In some preferred embodiments, the second dielectric layer 143a is formed using an oxide growth process. The thickness of the second dielectric layer 143a grown on the surface of the control gate 142 is T2, and the thickness of the second dielectric layer 143a grown on the sidewalls of the upper portions of the trenches 111a, 111c, and 111d is T3. Under the same oxidation growth conditions, T2 is common>T3. Wherein the range of T2 includes
Figure BDA0002745781870000111
The range of T3 should be considered in combination with the voltage required for the product, the depth of the trench in the device structure, the doping concentration of the first doped region, and the junction depth, and the range of T3 includes
Figure BDA0002745781870000112
And T3>T1。
In the present embodiment, an oxidation growth process is used to form the second dielectric layer 143a, in which a portion of the exposed control gate 142 is oxidized to form a portion of the second dielectric layer 143a, and in the subsequent steps, the second dielectric layer 143a on the surface of the control gate 142 and on the sidewalls of the upper portions of the trenches 111a, 111c, and 111d forms the shielding dielectric layer 143.
Further, a second conductive layer 144a covering the second dielectric layer 143a and filling the trench 111a, the trench 111c and the trench 111d of the first trench region 103 is formed, as shown in fig. 3 h.
In this step, the second conductive layer 144a is formed, for example, using a deposition process. The material of the second conductive layer 144a includes in-situ doped polysilicon, and in some other embodiments, the polysilicon without doping impurities may be deposited first, and then the doping impurities may be implanted. In a subsequent step, the second conductive layer 144a will form the shield gate 144.
In this embodiment, the doping type of the second conductive layer 144a is P-type in the case that the bidirectional power device is a PMOS transistor; in the case that the bidirectional power device is an NMOS, the doping type of the second conductive layer 144a is an N type.
Further, the second conductive layer 144a, the second dielectric layer 143a and the first dielectric layer 141a on the surface of the epitaxial layer 110 are removed, so as to form the shielding gate 144, the shielding dielectric layer 143 and the gate dielectric layer 141, as shown in fig. 3 i.
In this step, for example, one or a combination of a dry etching process, a wet etching process and a CMP process is used to remove the second conductive layer 144a, the second dielectric layer 143a and the first dielectric layer 141a outside the trenches 111a to 111d, so that the surfaces of the epitaxial layer 110, the first type sub-doping region 121 and the second type sub-doping region 122 are exposed, the remaining second dielectric layer 143a in the trenches 111a, 111c and 111d of the first trench region 103 is used as the shielding dielectric layer 143, and the remaining second conductive layer 144a is used as the shielding gate 144, where the remaining second dielectric layer 143a is also left at the top of the trench 111 d. The remaining first dielectric layer 141a in the trenches 111a to 111d serves as a gate dielectric layer 141. The gate dielectric layer 141 is located on the inner surface of the lower portion of the trenches 111a, 111c, 111d of the first trench region 103 and the entire inner surface of the trench 111b of the second trench region 104. The shielding dielectric layer 143 is located on sidewalls of upper portions of the trenches 111a, 111c, and 111d of the first trench region 103, and covers a surface of the control gate 142, and the shielding gate 144 is filled on the upper portions of the trenches 111a, 111c, and 111d, wherein the control gate 142 and the shielding gate 144 are separated by the shielding dielectric layer 143.
In some embodiments, the second conductive layer 144a above the epitaxial layer 110 is removed by CMP and dry etching, or by dry etching. The second dielectric layer 143a above the epitaxial layer 110 is removed by a CMP wetting process. The thickness T2 of the shielding dielectric layer 143 on the surface of the control gate 142 and the thickness T3 of the shielding dielectric layer 143 on the upper sidewall of the trench are both greater than the thickness T1 of the gate dielectric layer 141.
In the case where the control gate 142 and the shield gate 144 are located in the same trench, for example, in the first trench region 103, since the vertical depth of the entire trench is implemented at one time, the control gate 142 is located directly below the shield gate 144, and the vertical distance from the central line of the control gate 142 extending along the thickness direction of the substrate 101 to the inner boundary of the shield dielectric layer 143 located on the two side walls of the trench is the same, that is, d1 is d2, and the vertical distance from the central line of the control gate 142 extending along the thickness direction of the substrate 101 to the outer boundary of the shield dielectric layer 143 located on the two side walls of the trench is the same, that is, d3 is d 4.
Further, a first contact region 151 is formed in the first type sub-doping region 121, a second contact region 152 is formed in the second type sub-doping region 122, and a third contact region 153 is formed in the epitaxial layer 110, as shown in fig. 3 j.
In this step, the first-type sub-doping region 121, the second-type sub-doping region 122 and the epitaxial layer 110 are doped by implantation and diffusion, for example, through a photolithography mask. Wherein the implantation energy of the doping process is 20-180 Kev, and the implantation dosage is 1E 11-1E 16cm2。
In the present embodiment, the doping types of the first contact region 151 and the second contact region 152 are the same as the doping type of the first sub-doping region 121, and the doping type of the third contact region 153 is the same as the doping type of the epitaxial layer 110. For example, when the bidirectional power device is a PMOS, the doping types of the first contact region 151 and the second contact region 152 are P-type, and the doping type of the third contact region 153 is N-type; when the bidirectional power device is an NMOS, the doping types of the first contact region 151 and the second contact region 152 are N-type, and the doping type of the third contact region 153 is P-type. The P-type contact region is doped with B +/BF2+ and the N-type contact region is doped with As + and P +.
Further, a capping dielectric layer 102 is formed on the epitaxial layer 110, and a plurality of contact holes 102a extending from the surface of the capping dielectric layer 102 toward the substrate direction 101 are formed, as shown in fig. 3 k.
In this step, the capping dielectric layer 102 is formed by, for example, a chemical vapor deposition process, which may include one or a combination of LPCVD, SACVD, HTO, and SRO. The material of the cover dielectric layer 102 includes one or more of undoped silicon dioxide, boron-doped silicon dioxide, phosphorus-doped silicon dioxide, silicon dioxide doped with both boron and phosphorus, undoped polysilicon, silicon nitride, and silicon oxynitride material. Then, for example, photolithography and etching processes are used to form a plurality of contact holes 102a, the plurality of contact holes 102a respectively extend into the first contact region 151, the second contact region 152, the third contact region 153, the control gate 142 and the shield gate 144 to a depth h3, which includes
Figure BDA0002745781870000131
Further, a substrate electrode 163, a first contact electrode 161, a second contact electrode 162, a first gate electrode 164, and a second gate electrode 165 are formed in the plurality of contact holes, respectively, as shown in fig. 3 l.
In this step, for example, a metal conductive layer is deposited on the capping dielectric layer 102, the metal conductive layer extending from the surface of the capping dielectric layer 102 into the contact hole. Finally, photolithography and etching processes are used to form the first contact electrode 161, the second contact electrode 162, the substrate electrode 163, the first gate electrode 164, and the second gate electrode 165. The first contact electrode 161 and the second contact electrode 162 are a source electrode and a drain electrode, and may be interchanged.
The first contact electrode 161 is connected to the first contact region 151, the second contact electrode 162 is connected to the second contact region 152, the substrate electrode 163 is connected to the third contact region 153, the first gate electrode 164 is connected to the control gate 142, and the second gate electrode 165 is connected to the shield gate 144. The material of the metal conductive layer may be one or a combination of metals including Ti, TiN, TiSi, W, Al, AlSi, AlCu, AlSiCu, Cu, Ni, and the like. The metal etching adopts one or more of wet etching and plasma etching to form a substrate electrode 163, a first contact electrode 161, a second contact electrode 162, a first gate electrode 164 and a second gate electrode 165, and voltage or current is applied through the 5 electrodes to realize the performance of the device.
In the present embodiment, the position of the first gate electrode 164 corresponds to the trench 111b, and the position of the second gate electrode 165 corresponds to the trench 111 c. However, the embodiment of the present invention is not limited thereto, and since the plurality of trenches 111a to 111d are communicated such that the control gates 142 in the plurality of trenches 111a to 111d are connected to each other and the shield gates 144 in the plurality of trenches are connected to each other, the position of the second gate electrode 165 may also correspond to the trench 111a and/or the trench 111 d. The control gate 142 in the first trench region 103 and the control gate 142 in the second trench region 104 are led out through the first gate electrode 164, and the shield gate 144 in the first trench region 103 is led out through the second gate electrode 165.
In some embodiments, the first gate electrode 164 is connected to the second gate electrode 165 to connect the control gate 142 and the shield gate 144, so that the shield gate 144 overlaps the first-type sub-doped region 121 and the second-type sub-doped region 122, and a single poly-like structure is formed. When the voltages of the control gate 142 and the shielding gate 144 rise, the parasitic capacitance is charged, and the bidirectional power device is turned on; when the voltages of the control gate 142 and the shield gate 144 are reduced, the parasitic capacitance discharges and the bi-directional power device turns off. When the bidirectional power device is switched on and off at a high speed, the charging and discharging time of the parasitic capacitor can reduce the switching frequency, and the parasitic capacitor is charged and discharged to generate extra power consumption.
In other embodiments, the first gate electrode 164 can be separated from the second gate electrode 165 to receive different control voltages, i.e., the upper poly is connected separately to control the electric field in the upper half. For example, the second gate electrode 165 is connected to the substrate electrode 163 to connect the shielding gate 144 to the substrate 101, and the voltage of the shielding gate 144 is fixed during the switching process of the device, so that the charging and discharging of parasitic capacitance caused by the voltage variation of the shielding gate 144 can be avoided, the switching frequency of the bidirectional power device can be increased, and the power consumption can be reduced. The bidirectional power device can be used as a high-speed switch in certain application occasions requiring that the bidirectional power device not only has the lowest resistance as possible, but also has small parasitic capacitance.
Furthermore, the first embodiment of the present invention discloses a method for manufacturing a bidirectional power device, which can further optimize a wiring method and a method by increasing metal levels, so as to minimize resistance in the application process of the device and reduce signal interference to the maximum extent.
Further, the first embodiment of the present invention discloses a method for manufacturing a bidirectional power device, which can be combined with the practical application of products to add structures such as a passivation layer and polyimide, thereby protecting the device and enhancing the reliability.
Further, the first embodiment of the present invention discloses a method for manufacturing a bidirectional power device, which can form a structure required by a product through subsequent processes such as thinning and back evaporation, thereby realizing functions.
Further, the bidirectional power device with bidirectional conduction function according to the first embodiment of the present invention may draw the first gate electrode 164, the second gate electrode 165, the substrate electrode 163, the first contact electrode 161, and the second contact electrode 162 from the surface of the semiconductor structure, and may meet the packaging requirements of Chip Scale Package (CSP).
Further, the first embodiment of the present invention discloses a method for manufacturing a bidirectional power device, which can be applied to products such as power MOSFET, CMOS, BCD, high-power transistor, IGBT, schottky, and the like.
Fig. 4 is a block diagram illustrating a method of manufacturing a bi-directional power device at some stages according to a second embodiment of the present invention.
The structure and the manufacturing method of the bidirectional power device of this embodiment are substantially the same as those of the bidirectional power device of the first embodiment, and are not described herein again, and reference may be made to the description of fig. 3a to 3 l. The difference from the first embodiment is that the bidirectional power device of the present embodiment further includes a conductive via 170, as shown in fig. 4.
In this embodiment, the conductive vias 170 may be implemented in two ways.
The first embodiment of the conductive via 170 forms a doped region in the epitaxial layer 110 by one or more of implantation doping, diffusion source doping, and coating doping, and anneals the doped region to contact the doped region with the substrate 101, wherein the implantation energy is 50 to 10000Kev and the implantation dose is 1E11 to 1E16cm2The annealing temperature is 600-1200 ℃. In a subsequent step, the formed third contact region 153 is contacted with the conductive via 170.
Conductive via 170 in the first embodiment, the doping type of the doped region (conductive via 170) is the same as that of the epitaxial layer 110. For example, in the case that the bidirectional power device is an NMOS transistor, the doping type of the doped region is P-type, and the doping impurities generally adopt B +; in the case where the bidirectional power device is a PMOS transistor, the doping type of the doped region is N type, and the doping impurity is usually As + or P +.
In the first embodiment of the conductive via 170, the doped region is usually implanted with high energy, so as to reduce the process difficulty of the annealing process and reduce the area occupied by the impurity laterally diffused on the chip during the annealing process of the doped region. The doped region penetrates through the epitaxial layer 110 to the substrate 101, and as shown in fig. 4, the third doped region 153 is connected to the conductive via 170 and the substrate electrode 163, so as to reduce the bulk resistance, enhance the charge collection capability of the semiconductor substrate 101, and improve the parameter performance of the power device.
A second embodiment of the conductive via 170 is formed by filling a conductive material by etching from the surface of the epitaxial layer 110 and extending towards the substrate 101, for example, using a notching process.
In the second embodiment of the conductive via 170, the in-situ doped polysilicon may be directly filled, and in some other embodiments, the polysilicon without impurity may be filled first, and then the impurity may be implanted.
As shown in fig. 4, the third doped region 153 is connected to the conductive via 170 and the substrate electrode 163, so as to reduce the bulk resistance, enhance the charge collection capability of the semiconductor substrate, and improve the parameter performance of the power device. By adopting the mode of filling the groove with the conductive material, the body resistance is reduced, the reaction speed of the device is further improved, and the efficiency is improved.
Fig. 5a to 5d are block diagrams illustrating a method of manufacturing a bidirectional power device according to a third embodiment of the present invention at some stages.
The structure and the manufacturing method of the bidirectional power device of this embodiment are substantially the same as those of the bidirectional power device of the first embodiment, and this embodiment differs from fig. 3i of the first embodiment, and the details of the parts that are the same as those of the first embodiment are not repeated here, and reference may be made to the description of fig. 3a to 3 i. The difference from the first embodiment is in the contact hole and electrode manufacturing process of the bidirectional power device of the present embodiment. In contrast to the first embodiment, the metal electrode of the third embodiment is flush with the capping dielectric layer 102 and fills in the contact hole.
In this embodiment, with reference to fig. 3i in the first embodiment, the part of the shielding gate 144 in the trenches 111a, 111c, and 111d of the first trench region 103 is removed, as shown in fig. 5 a.
In this step, portions of the shield gate 144 in the trenches 111a, 111c, and 111d of the first trench region 103 are removed by photolithography and etching, so that the depth of the shield gate 144 remaining in the trenches 111a, 111c, and 111d below the surface of the epitaxial layer 110 is h 4. In some embodiments, a dry etch process is typically used such that h4 ranges from
Figure BDA0002745781870000161
Further, a blocking structure 180 is formed on the remaining shielding gate 144, as shown in fig. 5b, the blocking structure 180 is located at the upper portions of the trench 111a, the trench 111c and the trench 111d and contacts the shielding gate 144, and the remaining shielding gate 144 is surrounded by the blocking structure 180 and the shielding dielectric layer 143.
In this step, the barrier structure 180 is formed by using one or more of a chemical vapor deposition process, LPCVD, SACVD, HTO, and SRO process, wherein the material of the barrier structure 180 includes one or more of impurity-free silicon dioxide, boron-doped silicon dioxide, phosphorus-doped silicon dioxide, silicon dioxide doped with boron and phosphorus simultaneously, impurity-free polysilicon, silicon nitride, and silicon oxynitride material. In some preferred embodiments, the top of the trenches 111a, 111c, and 111d is filled with HDP, and then a CMP process is performed to expose the surface of the epitaxial layer 110.
Further, a first contact region 151 is formed in the first type sub-doping region 121, a second contact region 152 is formed in the second type sub-doping region 122, and a third contact region 153 is formed in the epitaxial layer 110, as shown in fig. 5 c.
In this step, the first-type sub-doping region 121, the second-type sub-doping region 122 and the epitaxial layer 110 are doped by implantation and diffusion, for example, through a photolithography mask. Wherein the implantation energy of the doping process is 20-180 Kev, and the implantation dosage is 1E 11-1E 16cm2。
In the present embodiment, the doping types of the first contact region 151 and the second contact region 152 are the same as the doping type of the first sub-doping region 121, and the doping type of the third contact region 153 is the same as the doping type of the epitaxial layer 110. For example, when the bidirectional power device is a PMOS, the doping types of the first contact region 151 and the second contact region 152 are P-type, and the doping type of the third contact region 153 is N-type; when the bidirectional power device is an NMOS, the doping types of the first contact region 151 and the second contact region 152 are N-type, and the doping type of the third contact region 153 is P-type. The P-type contact region is doped with B +/BF2+ and the N-type contact region is doped with As + and P +.
Further, a capping dielectric layer 102 is formed on the epitaxial layer 110, and a substrate electrode 163, a first contact electrode 161, a second contact electrode 162, a first gate electrode 164, and a second gate electrode are formed through the capping dielectric layer 102Gate electrode 165, as shown in fig. 5 d. The capping dielectric layer 102 covers the blocking structure 180, i.e., the blocking structure 180 is located between the shielding gate 144 and the capping dielectric layer 102. The formation method and structure of the capping dielectric layer 102 and the electrodes can be as described with reference to fig. 3k, except that the contact hole corresponding to the second gate electrode 165 needs to pass through the blocking structure 180, so that the second gate electrode 165 can pass through the blocking structure 180 to contact the shield gate 144. In the present embodiment, the substrate electrode 163, the first contact electrode 161, the second contact electrode 162, the first gate electrode 164, and the second gate electrode 165 respectively extend in the third contact region 153, the first contact region 151, the second contact region 152, the control gate 142, and the shield gate 144 to a depth h5, and the range of h5 includes
Figure BDA0002745781870000171
Compared with other embodiments, the metal electrode of the present embodiment is flush with the capping dielectric layer 102, which is beneficial to the subsequent planarization process requirement. Meanwhile, the substrate electrode 163, the first contact electrode 161, the second contact electrode 162, the first gate electrode 164, and the second gate electrode 165 have a larger area in the semiconductor structure, so that the contact area between the electrode and the conductive region is increased, the conductive capability can be further increased, the size of the contact hole can be reduced, and the chip area can be further reduced.
According to the manufacturing method of the bidirectional power device provided by the embodiment of the invention, the first doped region is formed in the epitaxial layer, the first doped region is divided into the first sub-doped region and the second sub-doped region which are alternated by the groove, and the first contact region and the second contact region are respectively formed in the first sub-doped region and the second sub-doped region, so that the two doped regions of the bidirectional power device are formed, the two doped regions are a source region and a drain region, and the area of the device is reduced.
More specifically, the first doped region is typically deeper, and higher diffusion temperatures and longer diffusion times are required to achieve deeper junction depths. Therefore, the first doping region is formed in the first step of the manufacturing method according to the requirements of product parameters, and the requirements of product structures and parameters can be realized by selecting proper doping conditions. Under the condition that the junction depth requirement of the first doped region is shallow, the first doped region can be formed without the first step of the manufacturing method, and the first doped region can also be annealed in the annealing process of other doped regions in the subsequent manufacturing method, so that the requirements of the junction depth and parameters required by the device structure are met.
Furthermore, by forming the control gates and the shielding gates in the plurality of grooves, when the bidirectional power device is cut off, the shielding gates deplete charges in the source region and the drain region through the shielding dielectric layer, and the voltage resistance of the device is improved; in the case of conduction of the bidirectional power device, the source region and/or the drain region and the channel region provide a low-impedance conduction path.
Furthermore, the control gate and the shielding gate in the device structure are separated from each other, the control gate in the first groove region and the control gate in the second groove region are connected and are led out through the electrodes, the shielding gate in the first groove region is led out through the electrodes, the connection between the shielding gate and the control gate can be realized through the leading-out electrodes (a structure similar to single polycrystal is formed), the shielding gate and the control gate can be isolated through the leading-out electrodes for separating the shielding gate from the control gate (namely, the upper section of polycrystal is independently connected), the electric field of the upper section is controlled, the independent control of the shielding gate is realized, and the shielding effect can be flexibly adjusted according to needs.
Furthermore, the body resistance of the device is reduced through the conductive channel connected with the substrate, and the performance of the bidirectional power device is improved.
Further, when the bidirectional power device is conducted, the substrate electrode connected with the substrate is in short circuit with one of the first contact electrode and the second contact electrode, and bidirectional selection of the current direction is achieved. Under the condition that the substrate electrode is in short circuit with the first contact electrode, current flows to the first contact electrode from the second contact electrode through the second type sub-doping area, the channel area and the first type sub-doping area in sequence; under the condition that the substrate electrode is in short circuit with the second contact electrode, current flows to the second contact electrode from the first contact electrode through the first type sub-doping area, the channel area and the second type sub-doping area in sequence.
Further, the channel length, and thus the channel resistance, may be reduced by reducing the width of the trench.
Furthermore, the device adopts a longitudinal control grid field structure, makes full use of a charge balance mechanism, and effectively improves the conduction efficiency and reduces the chip size by making the drift region resistance small under the condition of meeting the withstand voltage requirement.
Furthermore, the substrate electrode, the first contact electrode, the second contact electrode, the first gate electrode, the second gate electrode and the covering dielectric layer of the device are flush with each other, so that the requirement of a subsequent planarization process is facilitated.
Further, in the case that the control gate and the shield gate are located in the same trench, for example, in the first trench region, since the vertical depth of the entire trench is implemented at one time, the vertical distance from the central line of the control gate extending in the substrate thickness direction to the inner boundaries of the shield dielectric layers located on the two side walls of the trench is the same, and the vertical distance from the central line of the control gate extending in the substrate thickness direction to the outer boundaries of the shield dielectric layers located on the two side walls of the trench is the same, that is, the control gate is located right below the shield gate.
The embodiments of the present invention have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the invention, and these alternatives and modifications are intended to fall within the scope of the invention.

Claims (21)

1. A method of manufacturing a bi-directional power device, comprising:
forming a first doped region in the semiconductor layer;
forming a plurality of grooves in a first groove region, wherein the grooves of the first groove region are positioned in the first doping region and divide the first doping region into a first sub-doping region and a second sub-doping region which are alternated;
forming a gate dielectric layer covering the lower side walls of the plurality of grooves of the first groove area;
forming a control gate in contact with the gate dielectric layer at the lower part of the plurality of trenches in the first trench region;
forming a shielding dielectric layer which covers the upper side walls of the plurality of grooves of the first groove region and the surfaces of the control gates; and
forming a shield grid contacting with the shield dielectric layer on the upper part of the plurality of trenches in the first trench region,
wherein the shielding dielectric layer separates the control gate from the shielding gate.
2. The manufacturing method according to claim 1, wherein in a case where one of the first type sub-doping region and the second type sub-doping region serves as a source region, the other of the first type sub-doping region and the second type sub-doping region serves as a drain region, and the source region and the drain region are interchangeable.
3. The method of manufacturing of claim 1, wherein the semiconductor layer comprises a substrate and an epitaxial layer on the substrate, the method further comprising forming a conductive channel extending from the epitaxial layer surface toward the substrate,
wherein the conductive via is in contact with the substrate.
4. The manufacturing method of claim 3, wherein the step of forming the conductive via comprises:
forming a doped region in the epitaxial layer; and
annealing the doped region so that the doped region is in contact with the substrate,
wherein the doping type of the doping region is the same as that of the epitaxial layer.
5. The method of manufacturing of claim 4, wherein the process of forming the first doped region and the doped region comprises: one or more of implantation doping, diffusion source doping and coating doping.
6. The manufacturing method of claim 3, wherein the step of forming the conductive via comprises:
forming a recess extending from the epitaxial layer surface toward the substrate, a portion of the substrate being exposed by the recess; and
and filling a conductive material in the groove.
7. The method of manufacturing of claim 1, further comprising forming a trench in a second trench region, the trench of the second trench region being in the semiconductor layer and being separated from the first doped region;
the gate dielectric layer is further formed on the side wall of the groove of the second groove region;
the control gate is further formed in the trench of the second trench region, the trench of the first trench region is communicated with the trench of the second trench region, and the control gate in the trench of the first trench region is connected with the control gate in the trench of the second trench region.
8. The manufacturing method according to claim 1, further comprising:
forming a first contact region in the first type doped region;
forming a second contact region in the second type sub-doping region; and
a third contact region is formed in the semiconductor layer.
9. The manufacturing method according to any one of claims 1 to 8, further comprising forming a channel region adjacent to the control gate in the semiconductor layer.
10. The manufacturing method according to claim 8, further comprising:
forming a covering dielectric layer on the surface of the semiconductor layer; and
and forming a substrate electrode, a first contact electrode, a second contact electrode, a first gate electrode and a second gate electrode which penetrate through the covering dielectric layer, wherein the substrate electrode is connected with the third contact area, the first contact electrode is connected with the first contact area, the second contact electrode is connected with the second contact area, the first gate electrode is connected with the control gate, and the second gate electrode is connected with the shielding gate.
11. The manufacturing method according to claim 10, wherein the first gate electrode and the second gate electrode are connected to receive the same control voltage.
12. The manufacturing method according to claim 10, wherein the first gate electrode is electrically isolated from the second gate electrode to receive different control voltages.
13. The manufacturing method according to claim 10, before the step of forming a capping dielectric layer on the surface of the semiconductor layer, and after the step of forming a shield gate in contact with the shield dielectric layer on the upper portion of the plurality of trenches in the first trench region, the manufacturing method further comprising:
removing a part of the shielding gate in the plurality of trenches of the first trench region; and
forming a barrier structure in a plurality of trenches of the first trench region,
the blocking structure is located between the shielding gate and the covering dielectric layer, the second gate electrode further penetrates through the blocking structure, and the surfaces of the first contact electrode, the second contact electrode, the first gate electrode, the second gate electrode and the substrate electrode are flush with the covering dielectric layer.
14. The method of manufacturing of any of claims 1-8, wherein a thickness of the shield dielectric layer is greater than a thickness of the gate dielectric layer.
15. The manufacturing method according to any of claims 1-8, wherein the thickness of said shielding dielectric layer at the surface of said control gate is larger than the thickness of said shielding dielectric layer covering the upper sidewalls of the plurality of trenches of said first trench region.
16. The method of manufacturing of any of claims 1-8, wherein the gate dielectric layer has a thickness in a range including
Figure FDA0002745781860000031
17. The manufacturing method according to any one of claims 1-8, wherein the thickness of the shielding dielectric layer on the control gate surface is in a range including
Figure FDA0002745781860000032
18. The method of any of claims 1-8, wherein a thickness of the shield dielectric layer covering upper sidewalls of the plurality of trenches of the first trench region comprises
Figure FDA0002745781860000033
19. The manufacturing method according to claim 7, wherein a depth of the plurality of trenches in the first trench region and the second trench region ranges from 0.1 to 50 μm.
20. The manufacturing method according to any one of claims 1 to 8, wherein a distance from a surface of the control gate located in the first trench region to a surface of the semiconductor layer comprises 0.1 to 49 μm.
21. The manufacturing method according to any one of claims 1 to 8, wherein, in a case where the bidirectional power device is turned off, the shielding gate depletes charges of the first-type sub-doped region and the second-type sub-doped region through the shielding dielectric layer, so as to improve a withstand voltage characteristic of the bidirectional power device.
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