CN112309969B - Forming method of array substrate, array substrate and display device - Google Patents
Forming method of array substrate, array substrate and display device Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
- H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
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Abstract
The invention relates to a forming method of an array substrate, the array substrate and a display device, wherein the forming method of the array substrate comprises the following steps: forming a patterned first semiconductor layer on a substrate, wherein the first semiconductor layer comprises first active structures distributed in an array; forming a first insulating layer on one side of the first semiconductor layer, which is far away from the substrate; forming a patterned second semiconductor layer on one side, away from the substrate, of the first insulating layer, wherein the second semiconductor layer comprises second active structures and shielding structures which are distributed at intervals, and the orthographic projection of the shielding structures on the substrate is at least partially overlapped with the orthographic projection of the first active structures on the substrate; and carrying out ion implantation on the first active structure by taking the shielding structure as a shielding layer to form a first channel region and a first doping region, wherein the two sides of the first channel region in the first direction are respectively provided with the first doping region. According to the embodiment of the invention, different types of transistors can be simultaneously formed on the same substrate, and the cost control of the array substrate can be facilitated.
Description
Technical Field
The invention relates to the technical field of display, in particular to a forming method of an array substrate, the array substrate and a display device.
Background
With the real start of the information technology era, the field of displays for graphically representing electrical information signals has developed rapidly. Accordingly, various types of display devices, such as Liquid Crystal Display (LCD) devices, organic Light Emitting Display (OLED) devices, electrophoretic display (EPD) devices, and electrowetting display (EWD) devices, etc., which are thinner, lighter, and lower in power consumption, have been developed.
When a display device such as an OLED display device works, a corresponding array substrate is required to drive a display panel of the display device. The array substrate generally includes transistors, which can be classified according to the material of the active layer, and the conventional array substrate, when including two or more types of transistors, has a complicated forming method, which is not favorable for cost control of the array substrate.
Disclosure of Invention
The embodiment of the invention provides a forming method of an array substrate, the array substrate and a display device.
In one aspect, a method for forming an array substrate is provided according to an embodiment of the present invention, including:
forming a patterned first semiconductor layer on a substrate, wherein the first semiconductor layer comprises first active structures distributed in an array;
forming a first insulating layer on one side of the first semiconductor layer, which is far away from the substrate;
forming a patterned second semiconductor layer on one side, away from the substrate, of the first insulating layer, wherein the second semiconductor layer comprises second active structures and shielding structures which are distributed at intervals, and the orthographic projection of the shielding structures on the substrate is at least partially overlapped with the orthographic projection of the first active structures on the substrate;
and carrying out ion implantation on the first active structure by taking the shielding structure as a shielding layer to form a first channel region and a first doping region, wherein the two sides of the first channel region in the first direction are respectively provided with the first doping region.
In another aspect, an array substrate is provided according to an embodiment of the present invention, including a substrate and a device layer stacked on the substrate, where the device layer has a plurality of first transistors and second transistors distributed in an array, and the device layer includes:
the first semiconductor layer is arranged on the substrate and comprises first active structures distributed in an array mode, each first active structure comprises a first channel region and a first doping region, and the two ends of each first channel region in the first direction are respectively provided with the first doping regions;
the first insulating layer is arranged on one side, away from the substrate, of the first semiconductor layer;
the second semiconductor layer is arranged on one side, away from the substrate, of the first insulating layer and comprises second active structures and shielding structures which are distributed at intervals, and the orthographic projection of the shielding structures on the substrate covers the orthographic projection of the channel regions on the substrate and the orthographic projection of part of the first doping regions on the substrate.
In another aspect, a display device is provided according to an embodiment of the present invention, and includes the array substrate.
According to the forming method of the array substrate, the array substrate and the display device provided by the embodiment of the invention, the forming method of the array substrate comprises the steps of sequentially forming the patterned first semiconductor layer, the patterned first insulating layer and the patterned second semiconductor layer on the substrate, wherein the formed patterned second semiconductor layer comprises the shielding structure, and the orthographic projection of the shielding structure on the substrate is at least partially overlapped with the orthographic projection of the first active structure on the substrate, which is included by the first semiconductor layer, so that when the first active structure is subjected to ion implantation, the shielding structure can be used as the shielding layer for carrying out ion implantation, the first active structure is enabled to form the first channel region and the first doping region, the mask plate structure of the first active structure during doping is omitted, the forming method of the array substrate is simplified, the cost control of the array substrate is facilitated, and the forming efficiency of the array substrate is improved.
Drawings
Features, advantages and technical effects of exemplary embodiments of the present invention will be described below with reference to the accompanying drawings.
Fig. 1 is a schematic flow chart illustrating a method for forming an array substrate according to an embodiment of the present invention;
fig. 2 to 15 are schematic structural diagrams corresponding to steps of a method for forming an array substrate according to an embodiment of the invention;
fig. 16 to 25 are schematic structural views corresponding to partial steps of a molding method of an array substrate according to another embodiment of the present invention;
fig. 26 to 32 are schematic structural views corresponding to partial steps of a molding method of an array substrate according to yet another embodiment of the present invention;
FIG. 33 is a top view of a partial structure of an array substrate according to an embodiment of the invention;
FIG. 34 isbase:Sub>A cross-sectional view taken along line A-A of FIG. 33;
fig. 35 is a sectional view of a partial structure of an array substrate according to another embodiment of the present invention.
10-a substrate;
21-a first semiconductor layer; 211-a first active structure; 211 a-a first channel region; 211 b-first doped region; 2111-lightly doped region; 2112-heavily doped region;
22-a first insulating layer;
23-a second semiconductor layer; 231-a second active structure; 231 a-a second channel region; 231b — second doped region; 232-a shielding structure;
24-a first metal layer; 241-a first gate; 242-a second gate;
25-a second insulating layer; 251-a first region; 252-a second zone;
26-a third insulating layer;
27-a second metal layer; 271-a first source; 272-a first drain; 273-second source electrode; 274-a second drain;
28-via holes;
x-a first direction;
y-thickness direction.
In the drawings, like parts are provided with like reference numerals. The figures are not drawn to scale.
Detailed Description
Features of various aspects and exemplary embodiments of the present invention will be described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the present invention. In the drawings and the following description, at least some well-known structures and techniques have not been shown in detail in order to avoid unnecessarily obscuring the present invention; also, the dimensions of some of the structures may be exaggerated for clarity. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
In the description of the present invention, it is to be noted that, unless otherwise specified, "a plurality" means two or more; the terms "upper," "lower," "left," "right," "inner," "outer," and the like, as used herein, refer to an orientation or positional relationship indicated for convenience in describing the invention and to simplify description, but do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the invention. Furthermore, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
The directional terms used in the following description are intended to refer to directions shown in the drawings, and are not intended to limit the specific structure of embodiments of the present invention. In the description of the present invention, it should also be noted that, unless otherwise explicitly specified or limited, the terms "mounted" and "connected" are to be interpreted broadly, e.g., as either a fixed connection, a removable connection, or an integral connection; can be directly connected or indirectly connected. Specific meanings of the above terms in the present invention can be understood as appropriate by those of ordinary skill in the art.
In the existing method for forming the array substrate, when the array substrate to be formed includes more than two types of transistors, the main forming mode is to form a first semiconductor layer corresponding to one type of transistor in advance, and when the first semiconductor layer is subjected to ion implantation after an active structure of the first semiconductor layer is formed, a mask plate needs to be separately arranged to shield a partial area of the active structure of the first semiconductor layer and then corresponding ion implantation is performed, so that the active structure of the first semiconductor layer forms a corresponding doped area. And then forming a second semiconductor layer corresponding to the other type of transistor, doping and the like to form the required array substrate. Although the forming method can meet the forming requirement of the array substrate, when the first semiconductor layer of one type of transistor is doped, a corresponding mask plate needs to be arranged, and the forming method is complex and is not beneficial to cost control of the array substrate.
Based on the above technical problem, embodiments of the present invention provide a method for forming an array substrate, and a display device, in which different types of transistors can be formed on the same substrate, so as to meet the performance requirements of the array substrate, and the forming method is simplified, and is beneficial to controlling the cost of the array substrate.
For a better understanding of the present invention, embodiments of the present invention are described in detail below with reference to fig. 1 to 35.
Referring to fig. 1 to 15, fig. 1 is a schematic flow chart illustrating a method for forming an array substrate according to an embodiment of the present invention, and fig. 2 to 15 are schematic structural diagrams corresponding to steps of the method for forming an array substrate according to an embodiment of the present invention
As shown in fig. 1 to fig. 15, a method for forming an array substrate according to an embodiment of the present invention includes the following steps:
s100, as shown in fig. 2 and fig. 3, a patterned first semiconductor layer 21 is formed on the substrate 10, and the first semiconductor layer 21 includes first active structures 211 distributed in an array.
S200, as shown in fig. 4, a first insulating layer 22 is formed on a side of the first semiconductor layer 21 away from the substrate 10, and the first insulating layer 22 covers each first semiconductor layer 21.
S300, as shown in fig. 5 and fig. 6, forming a patterned second semiconductor layer 23 on a side of the first insulating layer 22 away from the substrate 10, where the patterned second semiconductor layer 23 includes second active structures 231 and blocking structures 232 distributed at intervals, and an orthographic projection of the blocking structures 232 on the substrate 10 at least partially overlaps an orthographic projection of the first active structure 211 on the substrate 10.
S400, as shown in fig. 7 to 11, the first active structure 211 is ion-implanted by using the shielding structure 232 as a shielding layer to form a first channel region 211a and a first doped region 211b, wherein the first doped region 211b is formed on two sides of the first channel region 211a in the first direction X, respectively.
According to the forming method of the array substrate provided by the embodiment of the invention, the patterned first semiconductor layer 21, the first insulating layer 22 and the patterned second semiconductor layer 23 are sequentially formed on the substrate 10, and the formed patterned second semiconductor layer 23 includes the shielding structure 232, and at least part of an orthographic projection of the shielding structure 232 on the substrate 10 is overlapped with an orthographic projection of the first active structure 211, which is included in the first semiconductor layer 21, on the substrate 10, so that when the first active structure 211 is subjected to ion implantation, the shielding structure 232 can be used as the shielding layer for carrying out ion implantation, and the first active structure 211 forms the first channel region 211a and the first doping region 211b, so that a mask plate structure of the first active structure 211 during doping is omitted, the forming method of the array substrate is simplified, the cost control of the array substrate is facilitated, and the forming efficiency of the array substrate is improved.
Alternatively, in step S100, the substrate 10 may be provided, but is not limited to, glass, quartz, ceramic or plastic, and the patterned first semiconductor layer 21 formed on the substrate 10 may include silicon, and may optionally include polysilicon.
Exemplarily, step S100 may specifically include:
an amorphous silicon layer is formed in advance on the substrate 10.
And forming a polycrystalline silicon layer on the amorphous silicon layer by adopting a low-temperature crystallization process, wherein the low-temperature crystallization process is solid-phase crystallization, excimer laser crystallization, rapid thermal annealing or a metal transverse induction method.
The polysilicon layer is patterned to form a patterned first semiconductor layer 21 including the first active structures 211 distributed in an array.
Alternatively, in step S200, the first insulating layer 22 may be formed of one or more of silicon oxide, silicon nitride, and phosphosilicate glass. The first insulating layer 22 may be formed by one of Plasma Enhanced Chemical Vapor Deposition (PECVD), sputtering (sputter), atomic deposition (ALD), anodization, and sol-gel) processes.
Alternatively, in step S300, the formed second semiconductor layer 23 may include an oxide material including, for example, oxygen and at least one of gallium, indium, zinc, and tin, and in some embodiments, the second semiconductor layer 23 may include a mixture oxide, such as IGZO, inZnO, inGaO, inSnO, znSnO, gaSnO, gaZnO, and the like.
Alternatively, in step S300, the second semiconductor layer 23 may be formed on the side of the first insulating layer 22 facing away from the substrate 10 by sputtering or evaporating an oxide semiconductor material or by a vapor deposition method (PVD). Then, the patterned second semiconductor layer 23 is formed by an etching process to include the second active structures 231 spaced apart from each other and the shielding structures 232.
Illustratively, the number of the shielding structures 232 included in the patterned second semiconductor layer 23 may be the same as the number of the first active structures 211 included in the first semiconductor layer 21 and may be arranged in a one-to-one correspondence in a thickness direction Y of the substrate 10, where the thickness direction Y of the substrate is perpendicular to the first direction X.
Optionally, at least a portion of an orthographic projection of each shielding structure 232 on the substrate 10 may overlap with an orthographic projection of one of the first active structures 211 on the substrate 10, so that an orthographic projection of a position, on the substrate 10, where each of the first active structures 211 needs to be ion-implanted, may at least partially expose the shielding structure 232.
Alternatively, when the first active structure 211 is ion-implanted in step S400, the ion implantation may be N-type ion implantation or P-type ion implantation. Illustratively, the ion implantation performed on the first active structure 211 may be an N-type ion implantation, and the doped ions may be phosphorus (P) ions or other N-type element ions.
In order to further optimize the effect of performing the ion implantation on the first active structure 211 by using the shielding structure 232 as the shielding layer, as an alternative embodiment, as shown in fig. 8 and fig. 9, before the step S400, the forming method further includes: a patterned first metal layer 24 is formed on one side of the first insulating layer 22 away from the substrate 10, the patterned first metal layer 24 includes first gate electrodes 241 distributed in an array, an orthographic projection of the shielding structure 232 on the substrate 10 at least partially overlaps with an orthographic projection of the first gate electrode 241 on the substrate 10, and two sides of the orthographic projection of the shielding structure 232 on the substrate 10 in the first direction X respectively protrude from the orthographic projection of the first gate electrode 241.
Through the above arrangement, when step S400 is executed, in the step of performing ion implantation on each first active structure 211 by using the shielding structure 232 as a shielding layer, the first gate may shield the first channel region 211a of the first active structure, and the shielding structure 232 may shield a position of the first active structure where the lightly doped region 2111 is to be formed, so that the first doped region 211b after ion implantation includes the lightly doped region 2111 and the heavily doped region 2112, and in the first direction X, the lightly doped region 2111 is located between the first channel region 211a and the heavily doped region 2112. In the primary ion implantation process, the heavily doped region 2112 and the lightly doped region 2111 may be simultaneously formed in the first doped region 211b, and the first gate 241 may shield the first channel region 211a of the first active structure 211, so as to optimize performance requirements of the first active structure 211 after ion implantation.
Optionally, the size of the orthographic projection of the shielding structure 232 on the substrate 10 protruding from the orthographic projection of the first gate 241 on each side of the first direction X is any value between 0.5um and 3um, including both ends of 0.5um and 3 um. When the first doping region 211b is formed on the array substrate, the shielding structure 232 can shield the lightly doped region 2111, so as to meet the requirement of synchronous forming of the lightly doped region 2111 and the heavily doped region 2112.
In some alternative embodiments, the step of forming the patterned first metal layer 24 on the side of the first insulating layer 22 facing away from the substrate 10 comprises:
as shown in fig. 8, the first metal layer 24 may be formed on a side of the first insulating layer 22 away from the substrate 10 and a side of the second semiconductor layer 23 away from the substrate 10, specifically, a metal material layer may be formed by depositing first on a side of the second semiconductor layer 23 away from the substrate 10 by a magnetron sputtering (sputter) or thermal evaporation method, the metal material layer may be a metal or an alloy such as Cr, W, ti, ta, mo, al, cu, or a composite film formed by multiple metal films.
As shown in fig. 9, the first metal layer 24 is patterned to form the first gates 241 distributed in an array. The metal material layer may be etched and patterned by an etching process, for example, including steps of photoresist coating, exposing, developing, etching, photoresist stripping, etc., to form the patterned first metal layer 24.
As an alternative embodiment, the step of patterning the first metal layer 24 may include: a mask is laid on the first metal layer 24, and the first metal layer 24 is etched to form a first gate 241. Alternatively, the second gate 242 may be simultaneously formed while patterning the first metal layer 24 to form the first gate 241, and an orthographic projection of the second gate 242 on the substrate 10 may at least partially cover the second active structure 231.
In some optional embodiments, before the step of forming the first metal layer 24 on the side of the second semiconductor layer 23 facing away from the substrate 10, the molding method further includes: a second insulating layer 25 is formed on the side of the second semiconductor layer 23 facing away from the substrate 10 to form the form of the structure shown in fig. 7.
Illustratively, the second insulating layer 25 may include one or more of silicon oxide, silicon nitride, phosphosilicate glass. The second insulating layer 25 may be formed by one of Plasma Enhanced Chemical Vapor Deposition (PECVD), sputtering (sputter), atomic deposition (ALD), anodization, and sol-gel (sol-gel)) processes.
Since the second semiconductor layer 23 has conductivity, the second insulating layer 25 is formed on the side of the second semiconductor layer 23 away from the substrate 10 before the step of forming the first metal layer 24 on the side of the second semiconductor layer 23 away from the substrate 10, so that the second semiconductor layer 23 can be prevented from affecting the width of the formed first gate electrode 241, the precision of the formed transistor can be ensured, and the occurrence probability of abnormal driving conditions can be reduced.
As shown in fig. 10, as an optional implementation manner, before step S400, the molding method further includes: and patterning the second insulating layer 25, wherein the patterned second insulating layer 25 comprises first regions 251 distributed in an array, the first gate electrodes 241 are arranged in a stacked manner with the first regions 251, and the orthographic projection of the first gate electrodes 241 on the substrate 10 is coincident with the orthographic projection of the first regions 251 on the substrate 10. Through the above arrangement, in step S400, when the shielding structure 232 is used as a shielding layer to perform ion implantation on the first active structure 211, the second insulating layer 25 can be prevented from interfering with the ion implantation, which is beneficial to forming the lightly doped region 2111 and the heavily doped region 2112 in the first doped region 211b.
Optionally, the patterned second insulating layer 25 may further include second regions 252 distributed in an array, the second gate 242 is stacked on the second regions 252, and an orthogonal projection of the second gate 242 on the substrate 10 coincides with an orthogonal projection of the second regions 252 on the substrate 10.
Optionally, the step of patterning the second insulating layer 25 comprises: the same mask as used for patterning the first metal layer 24 may be used, and after etching the first metal layer 24, the second insulating layer 25 may be continuously etched to form the first region 251 and the second region 252.
As an optional implementation manner, in the step of performing ion implantation on the first active structure 211 in step S400, ion implantation may be performed on the second active structure 231 simultaneously, so that the second active structure 231 forms the second channel region 231a and the second doping region 231b, thereby further simplifying the forming method of the array substrate and improving the forming efficiency thereof.
In some optional implementations, the method for forming an array substrate provided in the foregoing embodiments further includes:
as shown in fig. 12, a third insulating layer 26 is formed on a side of the first metal layer 24 facing away from the substrate 10, and the third insulating layer 26 may include one or more of silicon oxide, silicon nitride, and phosphosilicate glass. The third insulating layer 26 may be formed by one of Plasma Enhanced Chemical Vapor Deposition (PECVD), sputtering (sputter), atomic deposition (ALD), anodization, and sol-gel) processes.
As shown in fig. 13, the third insulating layer 26 is patterned such that the first doping region 211b and the second doping region 231b are exposed from the third insulating layer 26 through the via hole 28.
As shown in fig. 14, a second metal layer 27 is formed on a side of the third insulating layer 26 facing away from the substrate 10, and the second metal layer 27 is electrically connected to the first doped region 211b and the second doped region 231b through the via 28, respectively.
As shown in fig. 15, the second metal layer 27 is patterned to form a first source 271 and a first drain 272 electrically connected to the first doped region 211b. And a second source 273 and a second drain 274 electrically connected to the second doped region 231b, formed by arraying the low temperature polysilicon thin film transistors and the oxide semiconductor thin film transistors on the substrate 10.
It can be understood that, in the forming method of the array substrate provided by the foregoing embodiments, in the step of forming the patterned first metal layer 24 on the side of the first insulating layer 22 away from the substrate 10, the first metal layer 24 is formed on the side of the second semiconductor layer 23 away from the substrate 10 for illustration, which is an alternative implementation manner, but is not limited to the foregoing implementation manner. In some embodiments, in the step of forming the patterned first metal layer 24 on the side of the first insulating layer 22 away from the substrate 10, and the patterned first metal layer 24 includes the first gates 241 distributed in an array, the formed first metal layer 24 may also be located between the first semiconductor layer 21 and the second semiconductor layer 23, that is, the formed first metal layer 24 may also be located on the side of the second semiconductor layer 23 facing the substrate 10.
For example, referring to fig. 16 to 25, fig. 16 to 25 show schematic structural diagrams corresponding to a part of steps of a molding method of an array substrate according to another embodiment of the present invention. In this example, the implementation of step S100 and step S200 is the same as that of the above embodiment, and the same parts are not repeated herein, and the difference between this example and the above embodiment is that, before step S300, the molding method includes:
as shown in fig. 16, a first metal layer 24 is formed on the side of the first insulating layer 22 facing away from the substrate 10.
As shown in fig. 17, the first metal layer 24 is patterned to form first gates 241 distributed in an array, and optionally, in this step, second gates 242 distributed in an array may also be simultaneously formed.
As shown in fig. 18, a second insulating layer 25 is formed on a side of the patterned first metal layer 24 facing away from the substrate 10, and the second insulating layer 25 may cover the first gate electrode 241 and the second gate electrode 242.
As shown in fig. 19 and 20, in the step of forming the patterned second semiconductor layer 23 on the side of the first insulating layer 22 away from the substrate 10, the formed second semiconductor layer 23 is stacked on the second insulating layer 25, an orthographic projection of the shielding structure 232 on the substrate 10 at least partially overlaps an orthographic projection of the first gate electrode 241 on the substrate 10, and orthographic projections of the shielding structure 232 on the substrate 10 at two sides in the first direction X respectively protrude from the orthographic projection of the first gate electrode 241. That is, the first metal layer 24 is located between the first semiconductor layer 21 and the second semiconductor layer 23 in the thickness direction Y of the substrate 10.
As shown in fig. 21, in the step of performing ion implantation on each first active structure 211 by using the shielding structure 232 as a shielding layer, the first doped region 211b after the ion implantation includes a lightly doped region 2111 and a heavily doped region 2112, and in the first direction X, the lightly doped region 2111 is located between the first channel region 211a and the heavily doped region 2112. Through the above arrangement, when step S400 is executed, a heavily doped region 2112 and a lightly doped region 2111 can be synchronously formed in the first doped region 211b in one ion implantation process, and the first gate 241 can shield the first channel region 211a of the first active structure 211, so as to optimize the performance requirement of the first active structure 211 after ion implantation. In this example, ion implantation may be performed simultaneously with the first active structure 211 by disposing a blocking layer on the second active structure 231 to form a second channel region 231a and a second doping region 231b.
As shown in fig. 22 and fig. 23, after step S400 is performed, the forming method may further include forming a third insulating layer 26 on a side of the second semiconductor layer 23 away from the substrate 10, and patterning the third insulating layer 26, so that the first doping region 211b and the second doping region 231b are exposed to the third insulating layer 26 through the via 28.
As shown in fig. 24 and 25, a second metal layer 27 is formed on a side of the third insulating layer 26 away from the substrate 10, and the second metal layer 27 is electrically connected to the first doped region 211b and the second doped region 231b through the via 28, respectively. The second metal layer 27 is patterned to form a first source 271 and a first drain 272 electrically connected to the first doped region 211b, and a second source 273 and a second drain 274 electrically connected to the second doped region 231b, thereby forming ltps tfts and osfets on the substrate 10 in an array.
It is understood that, when the method for forming the array substrate provided by the above embodiments includes the step of forming the patterned first metal layer 24, one ion implantation may be used to simultaneously form the heavily doped region 2112 and the lightly doped region 2111 in the first doped region 211b, which is an alternative implementation manner, but is not limited to the above implementation manner.
Referring to fig. 26 to 32, fig. 26 to 32 are schematic structural diagrams corresponding to a part of steps of a forming method of an array substrate according to another embodiment of the present invention. In this example, the implementation of step S100 and step S200 is the same as the above embodiment, and the same parts are not repeated again, and the difference between this example and the above embodiment is that the method for forming the array substrate further includes, before step S300:
as shown in fig. 26, a first metal layer 24 is formed on the side of the first insulating layer 22 facing away from the substrate 10.
As shown in fig. 27, the first metal layer 24 is patterned to form first gates 241 distributed in an array, and optionally, in this step, second gates 242 distributed in an array may also be simultaneously formed.
As shown in fig. 28, each first active structure 211 is ion-implanted by using the first gate electrode 241 as a shielding layer to form a first channel region 211a and a lightly doped region 2111, wherein the lightly doped region 2111 is formed on two sides of the first channel region 211a in the first direction X.
As shown in fig. 29, a second insulating layer 25 is formed on the side of the patterned first metal layer 24 facing away from the substrate 10.
As shown in fig. 30 and 31, in the step of forming the patterned second semiconductor layer 23 on the side of the first insulating layer 22 away from the substrate 10, the formed second semiconductor layer 23 is stacked on the second insulating layer 25, and the orthographic projection of the shielding structure 232 on the substrate 10 covers the orthographic projection of the first channel region 211a and part of the lightly doped region 2111.
As shown in fig. 32, in the step of performing ion implantation on each first active structure 211 by using the shielding structure 232 as a shielding layer, the shielding structure 232 may shield a portion of the lightly doped region 2111, and perform ion implantation on the remaining portion again to form a heavily doped region 2112, so that the first doped region 211b after ion implantation includes the lightly doped region 2111 and the heavily doped region 2112. With the above arrangement, the shielding structure 232 can also serve as a shielding layer for the lightly doped region 2111, so that the first doped region 211b is formed to include the lightly doped region 2111 and the heavily doped region 2112.
Referring to fig. 33 and 34, fig. 33 isbase:Sub>A schematic top view of an array substrate according to an embodiment of the invention, and fig. 34 isbase:Sub>A cross-sectional view taken alongbase:Sub>A-base:Sub>A of fig. 33.
On the other hand, the embodiment of the present invention further provides an array substrate, and the array substrate may be formed by the forming method of the array substrate provided in the above embodiments. The array substrate includes a substrate 10 and a device layer stacked on the substrate 10, wherein the device layer has a plurality of first transistors 20a and second transistors 20b distributed in an array. The device layer includes a first semiconductor layer 21, a first insulating layer 22 and a second semiconductor layer 23, the first semiconductor layer 21 is disposed on the substrate 10, the first semiconductor layer 21 includes first active structures 211 distributed in an array, the first active structures 211 include a first channel region 211a and a first doped region 211b, and two ends of the first channel region 211a in the first direction X are respectively provided with the first doped region 211b. The first insulating layer 22 is disposed on a side of the first semiconductor layer 21 facing away from the substrate 10. The second semiconductor layer 23 is disposed on a side of the first insulating layer 22 away from the substrate 10, the second semiconductor layer 23 includes second active structures 231 and shielding structures 232 distributed at intervals, and an orthographic projection of the shielding structures 232 on the substrate 10 covers an orthographic projection of the first channel region 211a on the substrate 10 and an orthographic projection of a portion of the first doped region 211b on the substrate 10.
According to the array substrate provided by the embodiment of the invention, the second semiconductor layer 23 comprises the second active structures 231 and the shielding structures 232 which are distributed at intervals, and the orthographic projection of the shielding structures 232 on the substrate 10 covers the orthographic projection of the first channel region 211a on the substrate 10 and the orthographic projection of part of the first doping region 211b on the substrate 10, so that when the first active structure 211 is subjected to ion implantation, the shielding structures 232 can be used as shielding layers to shield the corresponding region of the first active structure 211, the ion implantation is completed, the working procedure is saved, the formation of the array substrate is facilitated, and the cost control requirement of the array substrate is met.
Optionally, in the array substrate provided in the embodiment of the present invention, a material of the first semiconductor layer 21 includes silicon, which may be polysilicon, and a material of the second semiconductor layer 23 includes metal oxide, which may include, for example, oxygen and at least one of gallium, indium, zinc, and tin. In some embodiments, the second semiconductor layer 23 may include a mixture oxide, such as IGZO, inZnO, inGaO, inSnO, znSnO, gaSnO, gaZnO, and the like.
As an optional implementation manner, the device layer further includes a first metal layer 24 disposed on a side of the first insulating layer 22 away from the substrate 10, the first metal layer 24 includes first gates 241 distributed in an array, the first doped region 211b includes a lightly doped region 2111 and a heavily doped region 2112, in the first direction X, the lightly doped region 2111 is located between the first channel region 211a and the heavily doped region 2112, an orthographic projection of the first gate 241 on the substrate 10 covers the first channel region 211a, and an orthographic projection of the shielding structure 232 on the substrate 10 covers the first channel region 211a and the lightly doped region 2111.
By arranging the first metal layer 24 and making the first metal layer and the shielding structure 232 satisfy the above projection relationship, the molding requirement of the first gate 241 of the first transistor 20a can be satisfied, and meanwhile, the arrangement of the first gate 241 can shield the first channel region 211a, so that when the first active structure 211 is ion-implanted, a lightly doped region 2111 and a heavily doped region 2112 can be formed in the first doped region 211b by one-time implantation.
In some optional embodiments, in the first direction X, a minimum distance from an outer edge of a forward projection of the first gate 241 on the substrate 10 to an outer edge of a forward projection of the shielding structure 232 on the substrate 10 is W, where W is any value between 0.5um and 3um, including both 0.5um and 3 um. Through the arrangement, when the array substrate is used for forming the first doping region 211b, the shielding structure 232 can better shield the lightly doped region 2111, and better synchronous forming of the lightly doped region 2111 and the heavily doped region 2112 is met.
Optionally, the first metal layer 24 further includes second gates 242 distributed in an array, the second active structure 231 includes a second channel region 231a and a second doped region 231b, the second channel region 231a is respectively provided with the second doped region 231b at two ends in the first direction X, and an orthographic projection of the second gate 242 on the substrate 10 covers the second channel region 231a. Through the above arrangement, the first gate 241 and the second gate 242 can be arranged in the same layer, so that the forming process of the array substrate during forming can be simplified, and meanwhile, when the first doping region 211b is formed through ion implantation, the second gate 242 can be used as a shielding layer to form the second doping region 231b synchronously.
In some optional embodiments, the device layer further comprises a second insulating layer 25, and the second semiconductor layer 23 is arranged to be insulated from the first metal layer 24 by the second insulating layer 25. Since the second semiconductor layer 23 has conductivity, the second insulating layer 25 is formed on the second semiconductor layer 23 on the side away from the substrate 10, so that the second semiconductor layer 23 can be prevented from affecting the width of the first gate electrode 241, the precision of the formed transistor can be ensured, and the occurrence probability of abnormal driving can be reduced.
As an alternative embodiment, when the array substrate includes the first metal layer 24, the first semiconductor layer 21, the first insulating layer 22, the second semiconductor layer 23, the second insulating layer 25 and the first metal layer 24 are sequentially distributed from one side of the substrate 10 and away from the substrate 10, the second insulating layer 25 includes first regions 251 distributed in an array, and an orthographic projection of the first gate 241 on the substrate 10 coincides with an orthographic projection of the first regions 251 on the substrate 10.
Optionally, the second insulating layer 25 may further include a second region 252, and an orthogonal projection of the first gate 242 on the substrate 10 coincides with an orthogonal projection of the second region 252 on the substrate 10. With the above arrangement, the second gate electrode 242 and the second semiconductor layer 23 can be insulated from each other, and the second semiconductor layer 23 can be prevented from affecting the width of the second gate electrode 242 to be formed, thereby similarly reducing the probability of occurrence of abnormal driving.
Optionally, the array substrate provided in the embodiment of the present invention may further include a third insulating layer 26 and a second metal layer 27, the third insulating layer 26 is disposed to cover the first metal layer 24, the second metal layer 27 includes a first source 271, a second drain 272, a second source 273 and a second drain 274, the first source 271 and the second drain 272 are electrically connected to the first doped region 211b, respectively, and the second source 273 and the second drain 274 are electrically connected to the second doped region 231b, respectively.
Referring to fig. 35, fig. 35 is a cross-sectional view illustrating an array substrate according to another embodiment of the present invention. It is to be understood that the second semiconductor layer 23 is disposed between the first semiconductor layer 21 and the first metal layer 24 in the thickness direction Y of the substrate 10, but not limited to the above, and in some embodiments, the first semiconductor layer 21, the first insulating layer 22, the first metal layer 24, the second insulating layer 25 and the second semiconductor layer 23 may be sequentially distributed from one side of the substrate 10 and away from the substrate 10, as shown in fig. 35. That is, in some embodiments, the first metal layer 24 may be disposed between the first semiconductor layer 21 and the second semiconductor layer 23 in the thickness direction Y of the substrate 10, which can also meet the performance requirements of the array substrate.
In another aspect, an embodiment of the present invention further provides a display device, where the display device includes the array substrate provided in each of the above embodiments. Optionally, the display device may further include a light emitting layer, and the first transistor 20a and the second transistor 20b on the array substrate may form a corresponding pixel circuit to control the corresponding sub-pixel on the light emitting layer, so as to ensure the display requirement. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator and the like. Because the second semiconductor layer 23 of the array substrate includes the second active structures 231 and the shielding structures 232 which are distributed at intervals, and the orthographic projection of the shielding structures 232 on the substrate 10 covers the orthographic projection of the first channel region 211a on the substrate 10 and the orthographic projection of part of the first doping region 211b on the substrate 10, when the first active structure 211 is subjected to ion implantation, the shielding structure 232 can be used as a shielding layer to shield a region corresponding to the first active structure 211, so that the ion implantation is completed, the process is saved, and the forming efficiency and the cost control of the display device are favorably improved.
While the invention has been described with reference to a specific embodiment, various modifications may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In particular, the technical features mentioned in the embodiments can be combined in any way as long as there is no structural conflict. It is intended that the invention not be limited to the particular embodiments disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.
Claims (14)
1. A method for forming an array substrate is characterized by comprising the following steps:
forming a patterned first semiconductor layer on a substrate, wherein the first semiconductor layer comprises first active structures distributed in an array;
forming a first insulating layer on one side, away from the substrate, of the first semiconductor layer;
forming a patterned second semiconductor layer on one side, away from the substrate, of the first insulating layer, wherein the second semiconductor layer comprises second active structures distributed at intervals and shielding structures, and orthographic projections of the shielding structures on the substrate at least partially overlap with orthographic projections of the first active structures on the substrate;
forming a first metal layer on one side of the second semiconductor layer, which is far away from the substrate;
patterning the first metal layer to form first gates distributed in an array, wherein orthographic projections of the shielding structures on the substrate are at least partially overlapped with orthographic projections of the first gates on the substrate, and the orthographic projections of the shielding structures on the substrate respectively protrude out of the orthographic projections of the first gates on two sides of the first direction;
carrying out ion implantation on the first active structure by taking the shielding structure as a shielding layer to form a first channel region and a first doping region, wherein the first doping region is respectively formed on two sides of the first channel region in a first direction;
the first doped region after ion implantation comprises a lightly doped region and a heavily doped region, and the lightly doped region is located between the first channel region and the heavily doped region in the first direction.
2. The method for forming an array substrate according to claim 1, wherein before the step of forming the first metal layer on the side of the second semiconductor layer facing away from the substrate, the method further comprises:
and forming a second insulating layer on one side of the second semiconductor layer, which is far away from the substrate.
3. The method for forming an array substrate of claim 2, wherein before the step of performing the ion implantation on the first active structure by using the shielding structure as the shielding layer, the method further comprises:
and patterning the second insulating layer, wherein the patterned second insulating layer comprises first regions distributed in an array, the first grid electrodes and the first regions are arranged in a stacked mode, and the orthographic projection of the first grid electrodes on the substrate is coincident with the orthographic projection of the first regions on the substrate.
4. The method of claim 3, wherein the patterning the first metal layer comprises:
laying a mask plate on the first metal layer;
etching the first metal layer to form the first grid;
the step of patterning the second insulating layer includes:
and continuously etching the second insulating layer after etching the first metal layer by using the same mask plate to form the first region.
5. The method for forming an array substrate according to claim 1, wherein before the step of forming the patterned second semiconductor layer on the side of the first insulating layer facing away from the substrate, the method further comprises:
forming a first metal layer on one side of the first insulating layer, which faces away from the substrate;
patterning the first metal layer to form first gates distributed in an array;
forming a second insulating layer on one side of the patterned first metal layer, which faces away from the substrate;
in the step of forming the patterned second semiconductor layer on the side, away from the substrate, of the first insulating layer, the formed second semiconductor layer is stacked on the second insulating layer, an orthographic projection of the shielding structure on the substrate is at least partially overlapped with an orthographic projection of the first gate on the substrate, and the orthographic projections of the shielding structure on the substrate respectively protrude from orthographic projections of the first gate on two sides of the first direction;
in the step of performing ion implantation on each first active structure by using the shielding structure as a shielding layer, the first doping region after ion implantation comprises a lightly doped region and a heavily doped region, and in the first direction, the lightly doped region is located between the first channel region and the heavily doped region.
6. The method for forming an array substrate according to claim 1, wherein before the step of forming the patterned second semiconductor layer on the side of the first insulating layer facing away from the substrate, the method further comprises:
forming a first metal layer on one side, away from the substrate, of the first insulating layer;
patterning the first metal layer to form first gates distributed in an array;
performing ion implantation on each first active structure by taking the first grid electrode as a shielding layer to form a first channel region and a lightly doped region, wherein the lightly doped region is formed on two sides of the first channel region in the first direction respectively;
forming a second insulating layer on one side of the patterned first metal layer, which is far away from the substrate;
in the step of forming a patterned second semiconductor layer on the side, away from the substrate, of the first insulating layer, the formed second semiconductor layer is stacked on the second insulating layer, and an orthographic projection of the shielding structure on the substrate covers the first channel region and an orthographic projection of part of the lightly doped region;
in the step of performing ion implantation on each first active structure by using the shielding structure as a shielding layer, the first doped region after ion implantation comprises the lightly doped region and a heavily doped region, and in the first direction, the lightly doped region is located between the first channel region and the heavily doped region.
7. The method for forming an array substrate according to any one of claims 1 to 6, wherein in the step of patterning the first metal layer, second gates distributed in an array are further formed, an orthographic projection of the second active structures on the substrate at least partially overlaps the second gates, and the orthographic projection of the second active structures on the substrate at two sides in the first direction respectively protrudes from the orthographic projection of the second gates;
in the step of performing ion implantation on the first active structure by using the shielding structure as a shielding layer, the second active structure is simultaneously subjected to ion implantation to form a second channel region and a second doped region, wherein the second doped region is formed on each of two sides of the second channel region in the first direction.
8. An array substrate, comprising a substrate and a device layer stacked on the substrate, wherein the device layer has a plurality of first transistors and second transistors distributed in an array, and the device layer comprises:
the first semiconductor layer is arranged on the substrate and comprises first active structures distributed in an array mode, the first active structures comprise first channel regions and first doping regions, and the two ends of each first channel region in a first direction are respectively provided with the first doping regions;
the first insulating layer is arranged on one side, away from the substrate, of the first semiconductor layer;
the first metal layer is arranged on one side, away from the substrate, of the first insulating layer and comprises first grid electrodes distributed in an array mode, each first doping area comprises a light doping area and a heavy doping area, the light doping area is located between the corresponding first channel area and the corresponding heavy doping area in the first direction, the orthographic projection of the first grid electrode on the substrate covers the corresponding first channel area, and the orthographic projection of the shielding structure on the substrate covers the corresponding first channel area and the light doping area;
the second semiconductor layer is arranged on one side, away from the substrate, of the first insulating layer and comprises second active structures and shielding structures which are distributed at intervals, and the orthographic projection of the shielding structures on the substrate covers the orthographic projection of the channel regions on the substrate and the orthographic projection of part of the first doping regions on the substrate;
and the second semiconductor layer and the first metal layer are arranged in an insulated mode through the second insulating layer.
9. The array substrate of claim 8, wherein the first semiconductor layer, the first insulating layer, the second semiconductor layer, the second insulating layer, and the first metal layer are sequentially distributed from one side of the substrate to a direction away from the substrate, the second insulating layer comprises a first region distributed in an array, and an orthographic projection of the first gate on the substrate coincides with an orthographic projection of the first region on the substrate.
10. The array substrate of claim 9, wherein the first semiconductor layer, the first insulating layer, the first metal layer, the second insulating layer, and the second semiconductor layer are sequentially distributed from one side of the substrate in a direction away from the substrate.
11. The array substrate of any one of claims 8 to 10, wherein the first metal layer further comprises second gates distributed in an array, the second active structure comprises a second channel region and a second doped region, the second channel region is respectively disposed at two ends of the first direction, and an orthographic projection of the second gate on the substrate covers the second channel region.
12. The array substrate of any one of claims 8 to 10, wherein in the first direction, the minimum distance from the outer edge of the orthographic projection of the first gate on the substrate to the outer edge of the orthographic projection of the shielding structure on the substrate is W, wherein W is greater than or equal to 0.5um and less than or equal to 3 um.
13. The array substrate of any one of claims 8 to 10, wherein the material of the first semiconductor layer comprises silicon, and the material of the second semiconductor layer comprises metal oxide.
14. A display device comprising the array substrate according to any one of claims 8 to 13.
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| CN105355588A (en) * | 2015-09-30 | 2016-02-24 | 深圳市华星光电技术有限公司 | Fabrication method of thin film transistor (TFT) array substrate, TFT array substrate and display device |
| CN106981520A (en) * | 2017-04-12 | 2017-07-25 | 京东方科技集团股份有限公司 | Thin film transistor (TFT) and preparation method thereof, array base palte and display device |
| CN108565247A (en) * | 2018-04-19 | 2018-09-21 | 武汉华星光电技术有限公司 | The production method and LTPS TFT substrates of LTPS TFT substrates |
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| US7579220B2 (en) * | 2005-05-20 | 2009-08-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device manufacturing method |
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| JPH0629319A (en) * | 1991-12-30 | 1994-02-04 | Gold Star Co Ltd | Thin-film transistor |
| TW200735278A (en) * | 2006-03-01 | 2007-09-16 | Univ Stuttgart | Method for producing CMOS circuit |
| CN104916584A (en) * | 2015-04-30 | 2015-09-16 | 京东方科技集团股份有限公司 | Manufacturing method, array substrate and display device |
| CN105355588A (en) * | 2015-09-30 | 2016-02-24 | 深圳市华星光电技术有限公司 | Fabrication method of thin film transistor (TFT) array substrate, TFT array substrate and display device |
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