CN112309858A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

Info

Publication number
CN112309858A
CN112309858A CN201910696119.XA CN201910696119A CN112309858A CN 112309858 A CN112309858 A CN 112309858A CN 201910696119 A CN201910696119 A CN 201910696119A CN 112309858 A CN112309858 A CN 112309858A
Authority
CN
China
Prior art keywords
source
layer
drain doping
doping layer
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201910696119.XA
Other languages
Chinese (zh)
Other versions
CN112309858B (en
Inventor
周飞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201910696119.XA priority Critical patent/CN112309858B/en
Publication of CN112309858A publication Critical patent/CN112309858A/en
Application granted granted Critical
Publication of CN112309858B publication Critical patent/CN112309858B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate, wherein the substrate comprises a substrate and a fin part protruding out of the substrate, a gate structure is formed on the substrate, and the gate structure crosses the fin part and covers part of the top and part of the side wall of the fin part; forming a first source-drain doping layer in the fin parts on two sides of the grid structure; forming at least one second source-drain doping layer on the first source-drain doping layer, wherein the step of forming the second source-drain doping layer comprises the following steps: forming a protective layer which is positioned on the substrate and exposes the first source drain doping layer or a second source drain doping layer positioned below the first source drain doping layer; forming a second source-drain doping layer on the first source-drain doping layer exposed out of the protective layer or the second source-drain doping layer positioned below the first source-drain doping layer; forming an interlayer dielectric layer covering the second source drain doping layer on the protection layer; and forming a contact hole plug surrounding the first source-drain doping layer and the second source-drain doping layer in the interlayer dielectric layer and the protective layer. The embodiment of the invention is beneficial to reducing the contact resistance of the source-drain doping layer and the contact hole plug.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
With the gradual development of semiconductor process technology, the development trend of semiconductor process nodes following moore's law is continuously reduced. In order to adapt to the reduction of process nodes, the channel length of the MOSFET field effect transistor is correspondingly and continuously shortened. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate to the channel is deteriorated, the difficulty of the gate voltage pinch-off (ping off) channel is increased, and the sub-threshold leakage (SCE) phenomenon, namely, the so-called short-channel effect (SCE) is easier to occur.
Therefore, in order to better accommodate the scaling requirements of device dimensions, semiconductor processes are gradually starting to transition from planar MOSFETs to three-dimensional transistors with higher performance, such as fin field effect transistors (finfets). In the FinFET, the gate can control the ultrathin body (fin part) at least from two sides, and compared with a planar MOSFET, the gate has stronger control capability on a channel and can well inhibit a short-channel effect; and finfets have better compatibility with existing integrated circuit fabrication relative to other devices.
Disclosure of Invention
The embodiment of the invention provides a semiconductor structure and a forming method thereof, which can reduce the contact resistance of a source-drain doping layer and a contact hole plug.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a substrate and a fin part protruding out of the substrate, a gate structure is formed on the substrate, and the gate structure stretches across the fin part and covers part of the top and part of the side wall of the fin part; forming a first source-drain doping layer in the fin parts on two sides of the grid structure; forming at least one second source-drain doping layer on the first source-drain doping layer, wherein the step of forming the second source-drain doping layer comprises the following steps: forming a protective layer which is positioned on the substrate and exposes the first source drain doping layer or a second source drain doping layer positioned below the first source drain doping layer; forming a second source-drain doping layer on the first source-drain doping layer exposed out of the protective layer or the second source-drain doping layer positioned below the first source-drain doping layer; forming an interlayer dielectric layer on the protective layer, wherein the interlayer dielectric layer covers the second source drain doping layer; and forming a contact hole plug surrounding the first source-drain doping layer and the second source-drain doping layer in the interlayer dielectric layer and the protective layer.
Optionally, the step of forming the first source-drain doping layer includes: etching the fin parts on two sides of the grid structure, and forming grooves in the fin parts on two sides of the grid structure; and forming the first source drain doping layer in the groove, wherein the top of the first source drain doping layer is higher than the top of the fin part.
Optionally, the number of the second source-drain doping layers is one, and the step of forming the second source-drain doping layers includes: forming a protective layer exposing the top of the first source-drain doping layer on the substrate exposed by the gate structure, wherein the top of the protective layer is higher than the top of the fin portion and lower than the top of the first source-drain doping layer; and forming the epitaxial layer on the first source-drain doping layer exposed out of the protective layer by adopting an epitaxial process, and forming the second source-drain doping layer by in-situ self-doping ions in the process of forming the epitaxial layer.
Optionally, the material of the protective layer is a dielectric material.
Optionally, the protective layer and the interlayer dielectric layer are made of the same material.
Optionally, the step of forming the contact hole plug includes: etching the interlayer dielectric layer and the protective layer to form a contact hole exposing the first source drain doping layer and the second source drain doping layer; and forming a contact hole plug for filling the contact hole.
Optionally, the groove is sigma shaped.
Optionally, the first source-drain doping layer or the second source-drain doping layer has a diamond structure in an extending direction perpendicular to the fin portion.
Optionally, after forming the contact hole and before forming the contact hole plug, the method further includes: and forming silicide layers on the surfaces of the first source-drain doping layer and the second source-drain doping layer exposed from the contact hole.
Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate; the fin part protrudes out of the substrate; the grid electrode structure stretches across the fin part and covers part of the top and part of the side wall of the fin part; the first source drain doping layer is positioned in the fin parts on two sides of the grid structure; the protective layer is positioned on the substrate, is at the same layer with the first source-drain doping layer and exposes the top of the first source-drain doping layer; at least one second source-drain doping layer located on the first source-drain doping layer exposed out of the protection layer; the interlayer dielectric layer is positioned on the protective layer and covers the second source drain doping layer; and the contact hole plug is positioned in the interlayer dielectric layer and the protective layer and surrounds the first source-drain doping layer and the second source-drain doping layer.
Optionally, the top of the first source-drain doping layer is higher than the top of the fin portion; the number of the second source-drain doped layers is one; the top of the protective layer is higher than the top of the fin part and lower than the top of the first source drain doping layer; the second source-drain doping layer comprises an epitaxial layer which is positioned on the first source-drain doping layer exposed out of the protective layer and is doped with ions.
Optionally, the material of the protective layer is a dielectric material.
Optionally, the protective layer and the interlayer dielectric layer are made of the same material.
Optionally, the material of the protective layer includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, or silicon oxycarbonitride.
Optionally, the semiconductor structure further includes: and the silicide layers are positioned between the first source drain doping layer and the contact hole plug and between the second source drain doping layer and the contact hole plug.
Optionally, in the normal direction of the substrate surface, the distance between the top of the protection layer and the top of the first source-drain doping layer is 1 nm to 3 nm.
Optionally, in the normal direction of the substrate surface, the top of the second source-drain doping layer is lower than the top of the gate structure, and the distance between the top of the second source-drain doping layer and the top of the gate structure is 100 to 500 angstroms.
Optionally, the first source-drain doping layer or the second source-drain doping layer has a diamond structure in an extending direction perpendicular to the fin portion.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the embodiment of the invention, at least one second source-drain doping layer is formed on the first source-drain doping layer after the first source-drain doping layer, that is, the source-drain doping layer formed in the embodiment of the invention is of a laminated structure, and compared with the scheme that the source-drain doping layer is not of a laminated structure, the embodiment of the invention is easy to increase the surface area of the source-drain doping layer by adjusting the size and the profile morphology of the first source-drain doping layer and the second source-drain doping layer, so that when a contact hole plug surrounding the first source-drain doping layer and the second source-drain doping layer is formed subsequently, the contact area of the contact hole plug and the first source-drain doping layer and the second source-drain doping layer is increased, and the contact resistance of the source-drain doping layer and the contact hole plug is further reduced.
In addition, the embodiment of the invention increases the contact surface of the source-drain doping layer along the direction vertical to the substrate (longitudinal direction), and is beneficial to preventing the problem that the adjacent source-drain doping layers are easy to generate short circuit (merge) due to the overlarge transverse size of the source-drain doping layer compared with the scheme of increasing the surface of the source-drain doping layer along the direction vertical to the fin portion (transverse direction).
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure;
FIGS. 2 to 13 are schematic structural diagrams corresponding to steps of a method for forming a semiconductor structure according to an embodiment of the present invention;
fig. 14 and 15 are schematic structural diagrams of an embodiment of a semiconductor structure of the present invention.
Detailed Description
The devices formed at present still have the problem of poor performance. The semiconductor structure is now combined to analyze the cause of poor device performance.
Referring to fig. 1, a schematic diagram of a semiconductor structure is shown.
The semiconductor structure includes: a substrate 1; a fin portion 2 protruding from the substrate 1; a gate structure (not shown) crossing the fin 2 and covering a portion of the top and a portion of the sidewalls of the fin 2; the source-drain doping layer 3 is positioned in the fin parts 2 at two sides of the grid structure; the interlayer dielectric layer 4 is positioned on the substrate 1 and covers the source-drain doping layer 3; and the contact hole plug 5 is positioned in the interlayer dielectric layer 4 and surrounds the source-drain doping layer 3.
In the semiconductor structure, the contact hole plug 5 surrounds the source-drain doping layer 3, so that the contact area between the contact hole plug 5 and the source-drain doping layer 3 is increased.
However, as the critical dimension of the device is further reduced, the dimension of the source-drain doping layer 3 is also continuously reduced, and the surface area of the source-drain doping layer 3 is also reduced, which results in that the contact area between the contact hole plug 5 and the source-drain doping layer 3 is also smaller, and the contact resistance between the contact hole plug 5 and the source-drain doping layer 3 is difficult to meet the process requirements.
In the prior art, the size of the source-drain doped layer 3 is increased, so that the surface area of the source-drain doped layer 3 is increased, and the contact area between the contact hole plug 5 and the source-drain doped layer 3 is increased to reduce the contact resistance.
However, increasing the size of the source and drain doped layers 3 also increases the size of the source and drain doped layers 3 along the direction (lateral direction) perpendicular to the extending direction of the fin 2. Along with the reduction of the critical dimension of the device, the distance between the adjacent fin parts 2 is also reduced continuously, the transverse dimension of the source-drain doping layer 3 is large, and the problem that the distance between the adjacent source-drain doping layers 3 is too short-circuited easily is caused.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a substrate and a fin part protruding out of the substrate, a gate structure is formed on the substrate, and the gate structure stretches across the fin part and covers part of the top and part of the side wall of the fin part; forming a first source-drain doping layer in the fin parts on two sides of the grid structure; forming at least one second source-drain doping layer on the first source-drain doping layer, wherein the step of forming the second source-drain doping layer comprises the following steps: forming a protective layer which is positioned on the substrate and exposes the first source drain doping layer or a second source drain doping layer positioned below the first source drain doping layer; forming a second source-drain doping layer on the first source-drain doping layer exposed out of the protective layer or the second source-drain doping layer positioned below the first source-drain doping layer; forming an interlayer dielectric layer on the protective layer, wherein the interlayer dielectric layer covers the second source drain doping layer; and forming a contact hole plug surrounding the first source-drain doping layer and the second source-drain doping layer in the interlayer dielectric layer and the protective layer.
In the embodiment of the invention, at least one second source-drain doping layer is formed on the first source-drain doping layer after the first source-drain doping layer, that is, the source-drain doping layer formed in the embodiment of the invention is of a laminated structure, and compared with the scheme that the source-drain doping layer is not of a laminated structure, the embodiment of the invention is easy to increase the surface area of the source-drain doping layer by adjusting the size and the profile morphology of the first source-drain doping layer and the second source-drain doping layer, so that when a contact hole plug surrounding the first source-drain doping layer and the second source-drain doping layer is formed subsequently, the contact area of the contact hole plug and the first source-drain doping layer and the second source-drain doping layer is increased, and the contact resistance of the source-drain doping layer and the contact hole plug is further reduced.
In addition, the embodiment of the invention increases the contact surface of the source-drain doping layer along the direction vertical to the substrate (longitudinal direction), and is beneficial to preventing the problem that the adjacent source-drain doping layers are easy to generate short circuit due to the overlarge transverse dimension of the source-drain doping layer compared with the scheme of increasing the surface of the source-drain doping layer along the direction vertical to the fin portion (transverse direction).
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 2 to 13 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 2 and 3, fig. 2 is a cross-sectional view along a vertical fin extending direction, fig. 3 is a cross-sectional view along a fin extending direction, a base (not labeled) is provided, the base includes a substrate 100 and a fin 110 protruding from the substrate 100, a gate structure 135 is formed on the base, and the gate structure 135 crosses over the fin 110 and covers a portion of a top and a portion of a sidewall of the fin 110.
The substrate 100 provides a process platform for subsequently forming semiconductor structures.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The fin 110 is used to provide a conductive channel for the field effect transistor during operation.
The fin 110 is the same material as the substrate 100. In this embodiment, the fin 110 is made of silicon. In other embodiments, the material of the fin may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
In this embodiment, after the substrate 100 and the fin portion 110 are formed, the method further includes: an isolation layer 120 is formed on the substrate 100 where the fins 110 are exposed, and the isolation layer 120 covers a portion of sidewalls of the fins 110.
The isolation layer 120 serves as an isolation structure of the semiconductor structure, and is used for isolating adjacent devices. In this embodiment, the material of the isolation layer 120 is silicon oxide. In other embodiments, the material of the isolation layer may be silicon nitride, silicon oxynitride, or other insulating materials.
In this embodiment, the gate structure 135 is a dummy gate structure (dummy gate), and the gate structure 135 occupies a space for forming a metal gate structure subsequently.
In this embodiment, the gate structure 135 is a single layer structure, and the gate structure 135 includes a gate layer. The material of the gate layer can be polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride or amorphous carbon. In this embodiment, the gate layer is made of polysilicon.
In other embodiments, the gate structure may also be a stacked structure, and the gate structure respectively includes a gate oxide layer and a gate layer on the gate oxide layer. In this embodiment, the material of the gate oxide layer may be silicon oxide or silicon oxynitride.
In this embodiment, the step of forming the gate structure 135 includes: forming a gate material layer (not shown) crossing the fins 110 and covering the top and sidewalls of the fins 110; forming a patterned gate mask layer 121 on the gate material layer; and patterning the gate material layer by using the gate mask layer 121 as a mask to form the gate structure 135.
In this embodiment, after the gate structure 135 is formed, the gate mask layer 121 is retained, and the gate mask layer 121 can protect the top of the gate structure 135 in a subsequent process. In this embodiment, the gate mask layer 121 is made of silicon nitride.
In this embodiment, after forming the gate structure 135, the forming method further includes: a sidewall spacer 122 is formed on the sidewall of the gate structure 135.
The sidewall spacers 122 are used to protect the sidewalls of the gate structures 135, and the sidewall spacers 122 are also used to define a formation region of a subsequent first source-drain doping layer.
The material of the sidewall 122 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, boron nitride, and boron carbonitride, and the sidewall 122 may have a single-layer structure or a stacked structure. In this embodiment, the sidewall 122 has a single-layer structure, and the material of the sidewall 122 is silicon nitride.
It should be noted that, for convenience of illustration and description, the gate structure 135, the gate mask layer 121, and the sidewalls 122 are only illustrated in a cross-sectional view along the extending direction of the fin 110 in the embodiment.
Referring to fig. 4 to 7, fig. 4 and 6 are cross-sectional views along a direction perpendicular to an extending direction of the fin, and fig. 5 and 7 are cross-sectional views along the extending direction of the fin, wherein first source/drain doping layers 130 are formed in the fin 110 on both sides of the gate structure 135 (as shown in fig. 6).
The first source-drain doping layer 130 is used for providing a process foundation for the subsequent formation of a second source-drain doping layer, and the first source-drain doping layer 130 and the subsequent second source-drain doping layer form a source-drain doping layer of the semiconductor structure.
When an NMOS transistor is formed, the first source-drain doped layer 130 comprises a stress layer doped with N-type ions, the material of the stress layer is Si or SiC, the stress layer provides a tensile stress effect for a channel region of the NMOS transistor, and therefore carrier mobility of the NMOS transistor is improved, wherein the N-type ions are P ions, As ions or Sb ions; when a PMOS transistor is formed, the first source-drain doped layer 130 includes a stress layer doped with P-type ions, the stress layer is made of Si or SiGe, and the stress layer provides a compressive stress effect for a channel region of the PMOS transistor, so as to improve carrier mobility of the PMOS transistor, wherein the P-type ions are B ions, Ga ions, or In ions.
In this embodiment, the step of forming the first source-drain doping layer 130 includes: as shown in fig. 4 and 5, the fin portions 110 on two sides of the gate structure 135 are etched, and a groove 145 is formed in the fin portions 110 on two sides of the gate structure 135; as shown in fig. 6 and 7, the first source-drain doping layer 130 is formed in the recess 145, and a top of the first source-drain doping layer 130 is higher than a top of the fin 110.
In this embodiment, the recess 145 is sigma shaped. In other embodiments, the recess may also be bowl-shaped or rectangular.
In this embodiment, the top of the first source-drain doping layer 130 is higher than the top of the fin portion 110, so as to provide a process basis for subsequently forming a protection layer exposing the top of the first source-drain doping layer 130 and covering the fin portion 110, and further, a second source-drain doping layer can be subsequently formed on the first source-drain doping layer 130 exposed by the protection layer.
In this embodiment, an epitaxial layer is formed in the groove 145 by an epitaxial process, and the first source-drain doping layer 130 is formed by in-situ self-doping ions in the process of forming the epitaxial layer. Wherein the epitaxial layer is used as the stress layer.
In this embodiment, the first source-drain doping layer 130 has a sigma-shaped structure, that is, the first source-drain doping layer 130 has a diamond structure along an extending direction perpendicular to the fin portion 110. In other embodiments, the shape of the first source-drain doped layer may also be mushroom-shaped, inverted bowl-shaped, or other shapes.
Referring to fig. 8 to 10, at least one second source-drain doping layer 160 is formed on the first source-drain doping layer 130 (as shown in fig. 10), and the step of forming the second source-drain doping layer 160 includes: forming a protection layer 150 on the substrate 100 and exposing the first source-drain doping layer 130 or the second source-drain doping layer 160 below; a second source-drain doping layer 160 is formed on the first source-drain doping layer 130 exposed by the protection layer 150 or the second source-drain doping layer 160 located below.
In this embodiment, after the first source-drain doping layer 130 is formed, at least one second source-drain doping layer 160 is further formed on the first source-drain doping layer 130, that is, the source-drain doping layer formed in this embodiment is of a stacked structure, and compared with a scheme that the source-drain doping layer is not of a stacked structure, in this embodiment, the surface area of the source-drain doping layer is made larger by adjusting the size and the profile morphology of the first source-drain doping layer 130 and the second source-drain doping layer 160, so that when a contact hole plug surrounding the first source-drain doping layer 130 and the second source-drain doping layer 160 is formed subsequently, the contact area between the contact hole plug and the first source-drain doping layer 130 and the second source-drain doping layer 160 is increased, and further, the contact resistance between the source-drain doping layer and the contact hole plug.
In addition, in the embodiment, the contact surface of the source/drain doping layer is increased in the direction (longitudinal direction) perpendicular to the substrate 100, and compared with the scheme of increasing the surface of the source/drain doping layer in the direction (transverse direction) perpendicular to the fin portion, the method is favorable for preventing the problem that short circuit (merge) is easy to occur between adjacent source/drain doping layers due to the fact that the transverse dimension of the source/drain doping layer is too large.
In this embodiment, the second source-drain doping layer 160 and the first source-drain doping layer 130 are made of the same material.
When an NMOS transistor is formed, the second source-drain doped layer 160 includes a stress layer doped with N-type ions, the material of the stress layer is Si or SiC, and the stress layer provides a tensile stress effect for a channel region of the NMOS transistor, so As to facilitate improvement of carrier mobility of the NMOS transistor, wherein the N-type ions are P ions, As ions, or Sb ions; when a PMOS transistor is formed, the second source-drain doping layer 160 includes a stress layer doped with P-type ions, the stress layer is made of Si or SiGe, and the stress layer provides a compressive stress effect for a channel region of the PMOS transistor, so as to improve carrier mobility of the PMOS transistor, wherein the P-type ions are B ions, Ga ions, or In ions.
In this embodiment, the number of the second source-drain doping layers 160 is one. In other embodiments, the number of the second source-drain doped layers is not limited to one.
It should be noted that, in this embodiment, the top of the second source-drain doping layer 160 is lower than the top of the gate structure 135, so as to provide a process foundation for forming an interlayer dielectric layer on the substrate 100 exposed by the gate structure 135 and forming a contact hole plug surrounding the first source-drain doping layer 130 and the second source-drain doping layer 160.
In the normal direction of the surface of the substrate 100, the distance between the top of the second source-drain doping layer 160 and the top of the gate structure 135 should not be too small or too large. If the distance is too small, the height of the top of the second source-drain doping layer 160 is correspondingly larger, and the relative area between the second source-drain doping layer 160 and the gate structure 135 is correspondingly larger, which easily increases the parasitic capacitance between the source-drain doping layer and the gate structure 135, and also easily increases the difficulty of forming an interlayer dielectric layer on the substrate 100 exposed by the gate structure 135 and forming a contact hole plug surrounding the first source-drain doping layer 130 and the second source-drain doping layer 160; if the distance is too large, the height of the top of the second source-drain doped layer 160 is correspondingly small, which easily results in an insignificant effect of increasing the contact surface of the source-drain doped layer. For this reason, in this embodiment, in the normal direction of the surface of the substrate 100, the distance between the top of the second source-drain doping layer 160 and the top of the gate structure 135 is 100 to 500 angstroms.
Specifically, in this embodiment, the step of forming the second source-drain doping layer 160 includes:
as shown in fig. 8 and 9, a protection layer 150 (shown in fig. 9) exposing the top of the first source/drain doping layer 130 is formed on the substrate 100 exposed by the gate structure 135 (shown in fig. 7), and the top of the protection layer 150 is higher than the top of the fin 110 and lower than the top of the first source/drain doping layer 130. Specifically, the protective layer 150 is formed on the isolation layer 120.
The forming of the second source/drain doping layer generally includes an epitaxial process, and the protection layer 150 is used to play a role of a mask in the subsequent step of forming the second source/drain doping layer, so as to protect a portion of the sidewall of the first source/drain doping layer 130 and prevent epitaxial growth on the entire surface of the first source/drain doping layer 130.
Moreover, the top of the protection layer 150 is higher than the top of the fin 110, so as to prevent epitaxial growth based on the fin 110 when forming the second source-drain doping layer 160 in the subsequent process.
In this embodiment, the material of the protection layer 150 is a dielectric material. By selecting the dielectric material, the influence of the protective layer 150 on the performance of the semiconductor structure can be reduced, and the protective layer 150 does not need to be removed subsequently, thereby simplifying the process steps and improving the process compatibility.
The material of the protective layer 150 includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, or silicon oxycarbonitride. In this embodiment, the material of the protection layer 150 is silicon oxide. The silicon oxide is a dielectric material with common process and low cost, has high process compatibility, and is beneficial to reducing the process difficulty and the process cost for forming the protective layer 150.
It should be noted that, along the normal direction of the surface of the substrate 100, the distance between the top of the protection layer 150 and the top of the first source-drain doping layer 130 is not too small or too large. If the distance is too small, the height of the first source-drain doping layer 130 exposed by the protection layer 150 is correspondingly too small, and when a second source-drain doping layer is formed on the first source-drain doping layer 130 exposed by the protection layer 150, the volume of the second source-drain doping layer is correspondingly too small, so that the effect of increasing the surface area of the source-drain doping layer is not obvious, and the second source-drain doping layer is formed by an epitaxial process generally, so that the process difficulty of the epitaxial process is increased easily when the height of the first source-drain doping layer 130 exposed by the protection layer 150 is too small; if the distance is too large, the risk that the protective layer 150 exposes the fin portion 110 is easily increased, and a second source-drain doped layer is easily formed on the side wall of the first source-drain doped layer 130, so that the lateral dimension of the source-drain doped layer is too large, and the risk that a short circuit problem occurs between adjacent source-drain doped layers is also easily increased. For this reason, in this embodiment, in the normal direction of the surface of the substrate 100, the distance between the top of the protection layer 150 and the top of the first source-drain doping layer 130 is 1 nm to 3 nm.
In this embodiment, the step of forming the protection layer 150 includes: as shown in fig. 8, an initial protection layer 140 covering the first source-drain doping layer 130 is formed on the substrate; as shown in fig. 9, a portion of the initial protection layer 140 is removed, and the initial protection layer 140 is left as the protection layer 150.
In this embodiment, the initial protection layer 140 is formed by a Flowable Chemical Vapor Deposition (FCVD) process. By selecting the flowable chemical vapor deposition process, the filling capacity of the initial protection layer 140 material is improved, so that the probability of generating defects such as voids (void) in the initial protection layer 140 is reduced, and the formation quality of the protection layer 150 is correspondingly improved.
In this embodiment, in the step of forming the initial protection layer 140, the initial protection layer 140 further covers the top of the gate structure 135. Therefore, in this embodiment, before removing a part of the thickness of the initial protection layer 140, the method further includes: the initial protection layer 140 above the top of the gate mask layer 122 is removed by a planarization process.
Through the planarization process, the top surface flatness of the initial protection layer 140 is improved, and accordingly, the top surface flatness of the protection layer 150 is advantageously improved. Specifically, in this embodiment, the planarization process is performed by using a Chemical-Mechanical Polishing (CMP) process.
In this embodiment, a dry etching process is used to remove a portion of the thickness of the initial protection layer 140.
The dry etching process is easy to realize anisotropic etching, has good process controllability, and is beneficial to accurately etching the initial protection layer 140, so that the height of the protection layer 150 meets the process requirements.
In this embodiment, taking the number of the second source-drain doping layers 160 as one example, only one protection layer 150 is correspondingly formed. In other embodiments, when the number of the second source-drain doping layers is greater than or equal to two, a plurality of protection layers may be correspondingly formed.
As shown in fig. 10, an epitaxial process is used to form the epitaxial layer on the first source/drain doping layer 130 exposed by the protection layer 150, and the second source/drain doping layer 160 is formed by in-situ self-doping ions in the process of forming the epitaxial layer.
Specifically, the epitaxial layer serves as the stress layer to provide a compressive stress or tensile stress effect for the channel region.
By adopting the epitaxial process, the second source-drain doping layer 160 material with higher purity can be obtained, and the formation quality of the second source-drain doping layer 160 can be further improved.
In this embodiment, after the second source-drain doping layer 160 is formed by an epitaxial process, the second source-drain doping layer 160 also has a diamond structure along the extending direction perpendicular to the fin 110. In other embodiments, the shape of the second source-drain doping layer may also be mushroom-shaped, inverted bowl-shaped, or other shapes.
In this embodiment, the second source-drain doping layer 160 and the first source-drain doping layer 130 are both diamond-shaped along the extending direction perpendicular to the fin portion 110, which is beneficial to further increase the surface area of the formed source-drain doping layer.
Referring to fig. 11, an interlayer dielectric layer 170 is formed on the protection layer 150, and the interlayer dielectric layer 170 covers the second source-drain doping layer 160.
After the interlayer dielectric layer 170 is formed, the interlayer dielectric layer 170 and the protection layer 150 form a dielectric layer for isolating adjacent devices, and the interlayer dielectric layer 170 and the protection layer 150 also provide a process platform for forming a contact hole plug surrounding the second source-drain doping layer 160 and the first source-drain doping layer 130.
Accordingly, the material of the interlayer dielectric layer 170 is a dielectric material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.
In this embodiment, the material of the interlayer dielectric layer 170 is the same as that of the protective layer 150, and the material of the interlayer dielectric layer 170 is silicon oxide, which is beneficial to improving process compatibility.
Referring to fig. 12 to 13, contact hole plugs 190 (shown in fig. 13) surrounding the first source-drain doping layer 130 and the second source-drain doping layer 160 are formed in the interlayer dielectric layer 170 and the protective layer 150.
The contact hole plugs 190 are used to electrically connect the source-drain doped layers with other interconnect structures or external circuitry.
In this embodiment, the surface area of the source-drain doping layer formed by the first source-drain doping layer 130 and the second source-drain doping layer 160 is large, so that when the contact hole plug 190 surrounding the first source-drain doping layer 130 and the second source-drain doping layer 160 is formed, the contact area between the contact hole plug 190 and the first source-drain doping layer 130 and the contact area between the contact hole plug 190 and the second source-drain doping layer 160 are increased, and further, the contact resistance between the source-drain doping layer and the contact hole plug 190 is reduced.
In this embodiment, the contact plug 190 is made of tungsten. In other embodiments, the material of the contact hole plug may also be other conductive materials such as cobalt.
In this embodiment, the step of forming the contact hole plug 190 includes:
as shown in fig. 12, the interlayer dielectric layer 170 and the protection layer 150 are etched to form a contact hole 200 exposing the first source-drain doping layer 130 and the second source-drain doping layer 160.
The contact hole 200 provides a spatial location for the subsequent formation of a contact hole plug. The contact hole 200 exposes the first source drain dopant layer 130 and the second source drain dopant layer 160, thereby providing for subsequent contact hole plugs to surround the first source drain dopant layer 130 and the second source drain dopant layer 160.
In this embodiment, the interlayer dielectric layer 170 and the protective layer 150 are etched by a dry etching process.
As shown in fig. 13, a contact hole plug 190 filling the contact hole 200 is formed.
Specifically, a conductive layer (not shown) is formed to fill the contact hole 200 and cover the top of the interlayer dielectric layer 170; and removing the conductive layer higher than the top of the interlayer dielectric layer 170, and using the residual conductive layer as the contact hole plug 190.
In this embodiment, the conductive layer is formed by a chemical vapor deposition process.
In this embodiment, a chemical mechanical polishing process is used to remove the conductive layer higher than the top of the interlayer dielectric layer 170, so as to improve the flatness of the top surface of the contact hole plug 190.
In this embodiment, referring to fig. 12 in combination, after forming the contact hole 200 and before forming the contact hole plug 190, the method further includes: and forming a silicide layer 180 on the surfaces of the first source-drain doping layer 130 and the second source-drain doping layer 160 exposed from the contact hole 200.
After the contact hole plug filling the contact hole 200 is formed subsequently, the silicide layer 180 is located between the first source-drain doping layer 130 and the contact hole plug, and between the second source-drain doping layer 160 and the contact hole plug, and the silicide layer 180 is used for reducing contact resistance between the contact hole plug and the first source-drain doping layer 130 and the second source-drain doping layer 160, improving adhesiveness between the contact hole plug and the first source-drain doping layer 130 and the second source-drain doping layer 160, and further improving contact performance between the contact hole plug and the source-drain doping layer.
The material of the silicide layer 180 may be TiSi, NiSi, CoSi, or the like. In this embodiment, the material of the silicide layer 180 is TiSi.
It should be further noted that, in this embodiment, the gate structure 135 is a dummy gate structure, and therefore, after the forming the interlayer dielectric layer 170 and before the forming the contact hole 200, the forming method further includes: removing the gate mask layer 121 and the gate structure 135, and forming a gate opening (not shown) in the interlayer dielectric layer 170; a metal gate structure (not shown) is formed in the gate opening.
The gate opening provides a spatial location for forming a metal gate structure.
The metal gate structure is used for controlling the on and off of the conducting channel when the field effect transistor works.
A metal gate structure crosses the fin 110 and covers a portion of the top and a portion of the sidewalls of the fin 110. The metal gate structure includes a gate dielectric layer (not shown), and a gate electrode layer (not shown) on the gate dielectric layer.
The gate dielectric layer is used to electrically isolate the metal gate structure from the fin 110. In this embodiment, the gate dielectric layer is made of a high-k dielectric material. Specifically, the material of the gate dielectric layer is HfO2. In other embodiments, the material of the gate dielectric layer may also be selected from ZrO2HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3And the like.
The gate electrode layer is used to electrically connect the metal gate structure to other interconnect structures or external circuitry. In this embodiment, the gate electrode layer is made of a magnesium-tungsten alloy. In other embodiments, the gate electrode layer may be made of W, Al, Cu, Ag, Au, Pt, Ni, Ti, or the like.
The detailed description of the steps related to forming the metal gate structure is omitted here for brevity.
Correspondingly, the invention also provides a semiconductor structure. Referring to fig. 14 to 15, fig. 14 is a cross-sectional view taken along a direction perpendicular to a direction in which the fin extends, and fig. 15 is a cross-sectional view taken along the direction in which the fin extends, illustrating a schematic structural view of an embodiment of a semiconductor structure according to the present invention.
The semiconductor structure includes: a substrate 300; a fin 310 protruding from the substrate 300; a gate structure 400 crossing the fin 310 and covering a portion of the top and a portion of the sidewall of the fin 310; the first source-drain doping layer 330 is located in the fin portions 310 on two sides of the gate structure 400; the protective layer 350 is located on the substrate 300, is at the same layer as the first source-drain doping layer 330, and exposes the top of the first source-drain doping layer 330; at least one second source-drain doping layer 360 located on the first source-drain doping layer 330 exposed by the protection layer 350; an interlayer dielectric layer 370, located on the protection layer 350 and covering the second source drain doping layer 360; and a contact hole plug 390 positioned in the interlayer dielectric layer 370 and the protection layer 350 and surrounding the first source drain doping layer 330 and the second source drain doping layer 360.
In this embodiment, the semiconductor structure includes at least one second source-drain doping layer 360 on the first source-drain doping layer 330 exposed by the protection layer 350, that is, the source-drain doping layer of the semiconductor structure provided in this embodiment is a stacked structure, and compared with a scheme in which the source-drain doping layer is not a stacked structure, the embodiment is easy to increase the surface area of the source-drain doping layer by adjusting the size and the profile morphology of the first source-drain doping layer 330 and the second source-drain doping layer 360, thereby being beneficial to increasing the contact area between the contact hole plug 390 and the first source-drain doping layer 330 and the second source-drain doping layer 360, and further being beneficial to reducing the contact resistance between the source-drain doping layer and the contact hole plug 390.
In addition, in the embodiment, the contact surface of the source and drain doping layer is increased in the direction (longitudinal direction) perpendicular to the substrate 300, and compared with the scheme that the surface of the source and drain doping layer is increased in the direction (transverse direction) perpendicular to the fin portion, the problem that short circuit is easy to occur between adjacent source and drain doping layers due to the fact that the transverse dimension of the source and drain doping layer is too large is favorably solved.
The substrate 300 provides a process platform for the formation of semiconductor structures. In this embodiment, the substrate 300 is a silicon substrate.
Fin 310 is used to provide a conductive channel for the operation of a field effect transistor. In this embodiment, the material of the fin 310 is silicon.
In this embodiment, the semiconductor structure further includes: an isolation layer 320 is disposed on the substrate 300 where the fin 310 is exposed, and the isolation layer 320 covers a portion of the sidewall of the fin 310.
The isolation layer 320 serves as an isolation structure of the semiconductor structure, and is used for isolating adjacent devices. In this embodiment, the isolation layer 320 is made of silicon oxide. In other embodiments, the material of the isolation layer may be silicon nitride, silicon oxynitride, or other insulating materials.
The gate structure 400 is used to control the on and off of the conductive channel when the field effect transistor is operating.
In this embodiment, the gate structure 400 is a metal gate structure. The gate structure 400 includes a gate dielectric layer (not shown), and a gate electrode layer (not shown) on the gate dielectric layer.
The gate dielectric layer is used to electrically isolate the gate structure 400 from the fin 310. In this embodiment, the gate dielectric layer is made of a high-k dielectric material. Specifically, the material of the gate dielectric layer is HfO2。
The gate electrode layer is used to enable electrical connection of the gate structure 400 to other interconnect structures or external circuitry. In this embodiment, the gate electrode layer is made of a magnesium-tungsten alloy.
In other embodiments, the gate structure may not be a metal gate structure, and the gate structure may include a gate oxide layer and a gate layer on the gate oxide layer. In this embodiment, the material of the gate oxide layer may be silicon oxide or silicon oxynitride, and the material of the gate electrode layer may be polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride or amorphous carbon.
In this embodiment, the semiconductor structure further includes: and a sidewall spacer 322 on a sidewall of the gate structure 400. The sidewall spacers 322 are used to protect the sidewalls of the gate structure 400, and the sidewall spacers 322 are also used to define a formation region of the first source-drain doping layer 330.
The side wall 322 may be made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, boron nitride, and boron carbonitride, and the side wall 322 may have a single-layer structure or a stacked-layer structure. In this embodiment, the sidewall spacers 322 have a single-layer structure, and the material of the sidewall spacers 322 is silicon nitride.
It should be noted that, in this embodiment, for convenience of illustration and description, only the gate structure 400 and the sidewall spacers 322 are illustrated in fig. 15.
The first source-drain doping layer 330 is used for providing a process foundation for forming the second source-drain doping layer 360, and the first source-drain doping layer 330 and the second source-drain doping layer 360 form a source-drain doping layer of the semiconductor structure.
When an NMOS transistor is formed, the first source-drain doped layer 330 includes a stress layer doped with N-type ions, the material of the stress layer is Si or SiC, and the stress layer provides a tensile stress effect for a channel region of the NMOS transistor, so As to facilitate improvement of carrier mobility of the NMOS transistor, wherein the N-type ions are P ions, As ions, or Sb ions; when a PMOS transistor is formed, the first source-drain doped layer 330 includes a stress layer doped with P-type ions, the stress layer is made of Si or SiGe, and the stress layer provides a compressive stress effect for a channel region of the PMOS transistor, so as to improve carrier mobility of the PMOS transistor, wherein the P-type ions are B ions, Ga ions, or In ions.
In this embodiment, the first source-drain doping layer 330 has a sigma-shaped structure, that is, the first source-drain doping layer 330 has a diamond structure along an extending direction perpendicular to the fin portion 310. In other embodiments, the shape of the first source-drain doped layer may also be mushroom-shaped, inverted bowl-shaped, or other shapes.
In this embodiment, the top of the first source-drain doping layer 330 is higher than the top of the fin portion 310, so as to provide a process foundation for forming the protection layer 350, and further enable the second source-drain doping layer 360 to be located on the first source-drain doping layer 330 exposed from the protection layer 350.
In this embodiment, the top of the protection layer 350 is higher than the top of the fin portion 310 and lower than the top of the first source drain doping layer 330.
The forming step of the second source/drain doping layer 360 generally includes an epitaxial process, and the protection layer 350 is used to play a role of a mask in the forming step of the second source/drain doping layer 360, so as to protect a part of the sidewall of the first source/drain doping layer 330 and prevent epitaxial growth on the entire surface of the first source/drain doping layer 330.
In this embodiment, the top of the protection layer 350 is higher than the top of the fin portion 310, so as to prevent the epitaxial growth based on the fin portion 310 in the step of forming the second source drain doping layer 360.
In this embodiment, the material of the protection layer 350 is a dielectric material. By selecting a dielectric material, the influence of the protective layer 350 on the performance of the semiconductor structure can be reduced, and the protective layer 350 can be remained in the semiconductor structure, thereby facilitating the simplification of process steps and the improvement of process compatibility.
The material of the protection layer 350 includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, or silicon oxycarbonitride. In this embodiment, the material of the protection layer 350 is the same as that of the interlayer dielectric layer 370, which is beneficial to improving process compatibility.
Specifically, the material of the protection layer 350 is silicon oxide. The silicon oxide is a dielectric material with common process and low cost, has high process compatibility, and is beneficial to reducing the process difficulty and the process cost for forming the protective layer 350.
It should be noted that, along the normal direction of the surface of the substrate 300, the distance between the top of the protection layer 350 and the top of the first source-drain doping layer 330 is not too small or too large. If the distance is too small, the height of the first source-drain doping layer 330 exposed by the protection layer 350 is correspondingly too small, and the volume of the second source-drain doping layer 360 is also too small, so that the effect of increasing the surface area of the source-drain doping layer is not obvious easily, and the forming difficulty of the second source-drain doping layer 360 is increased easily; if the distance is too large, the risk that the fin portion 310 is exposed by the protection layer 350 is easily increased, and the second source-drain doping layer 360 is easily formed on the sidewall of the first source-drain doping layer 330, so that the lateral dimension of the source-drain doping layer is easily too large. For this reason, in this embodiment, in the normal direction of the surface of the substrate 300, the distance between the top of the protection layer 350 and the top of the first source-drain doping layer 330 is 1 nm to 3 nm.
In this embodiment, taking the number of the second source-drain doped layers 360 as one example, the number of the layers of the protection layer 350 is only one. In other embodiments, when the number of the second source-drain doping layers is greater than or equal to two, the semiconductor structure may include a plurality of the protection layers.
The material of the second source drain doping layer 360 is the same as that of the first source drain doping layer 330.
The second source/drain doping layer 360 includes an epitaxial layer doped with ions and located on the first source/drain doping layer 330 exposed by the protection layer 350.
When an NMOS transistor is formed, the second source-drain doped layer 360 includes a stress layer doped with N-type ions, the material of the stress layer is Si or SiC, and the stress layer provides a tensile stress effect for a channel region of the NMOS transistor, so As to facilitate improvement of carrier mobility of the NMOS transistor, wherein the N-type ions are P ions, As ions, or Sb ions; when a PMOS transistor is formed, the second source-drain doped layer 360 includes a stress layer doped with P-type ions, the stress layer is made of Si or SiGe, and the stress layer provides a compressive stress effect for a channel region of the PMOS transistor, so as to improve carrier mobility of the PMOS transistor, wherein the P-type ions are B ions, Ga ions, or In ions.
Wherein the epitaxial layer is used as the stress layer.
In this embodiment, the number of the second source-drain doped layers 360 is one. In other embodiments, the number of the second source-drain doped layers is not limited to one.
It should be noted that in this embodiment, the top of the second source-drain doping layer 360 is lower than the top of the gate structure 400, so as to provide a process basis for forming the interlayer dielectric layer 370 and the contact hole plug 390.
It should be further noted that, along the normal direction of the surface of the substrate 300, the distance between the top of the second source-drain doping layer 360 and the top of the gate structure 400 is not too small or too large. If the distance is too small, the height of the top of the second source-drain doping layer 360 is correspondingly larger, and the relative area between the second source-drain doping layer 360 and the gate structure 400 is correspondingly larger, so that the parasitic capacitance between the source-drain doping layer and the gate structure 400 is easily increased, and the forming difficulty of the contact hole plug 390 is also easily increased; if the distance is too large, the height of the top of the second source-drain doped layer 360 is correspondingly small, which easily results in an insignificant effect of increasing the contact surface of the source-drain doped layer. Therefore, in this embodiment, in the normal direction of the surface of the substrate 300, the distance between the top of the second source-drain doping layer 360 and the top of the gate structure 400 is 100 to 500 angstroms.
In this embodiment, the second source-drain doped layer 360 also has a diamond structure along the extending direction perpendicular to the fin 310. In other embodiments, the second source-drain doped layer may also have other shapes such as a mushroom shape, an inverted bowl shape, and the like.
In this embodiment, the second source-drain doping layer 360 and the first source-drain doping layer 330 are both diamond-shaped along the extending direction perpendicular to the fin portion 310, which is beneficial to further increase the surface area of the source-drain doping layer.
The interlayer dielectric layer 370 and the protection layer 350 constitute a dielectric layer for isolating adjacent devices, and the interlayer dielectric layer 370 and the protection layer 350 also provide a process platform for forming the contact hole plug 390.
Accordingly, the material of the interlayer dielectric layer 370 is a dielectric material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
In this embodiment, the material of the interlayer dielectric layer 370 is the same as that of the protection layer 350, and the material of the interlayer dielectric layer 370 is silicon oxide, which is beneficial to improving process compatibility.
The contact hole plugs 390 are used to electrically connect the source and drain doped layers to other interconnect structures or external circuitry. In this embodiment, the contact plug 390 is made of tungsten. In other embodiments, the material of the contact hole plug may also be other conductive materials such as cobalt.
In this embodiment, the semiconductor structure further includes: and silicide layers 380 located between the first source-drain doping layer 330 and the contact hole plug 390 and between the second source-drain doping layer 360 and the contact hole plug 390.
The silicide layer 380 is used for reducing contact resistance between the contact hole plug 390 and the first source-drain doping layer 330 and the second source-drain doping layer 360, improving adhesiveness between the contact hole plug 390 and the first source-drain doping layer 330 and the second source-drain doping layer 360, and further improving contact performance between the contact hole plug 390 and the source-drain doping layer.
The material of the silicide layer 380 may be TiSi, NiSi, CoSi, or the like. In this embodiment, the material of the silicide layer 380 is TiSi.
The semiconductor structure may be formed by the formation method described in the foregoing embodiment, or may be formed by another formation method. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (18)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a substrate and a fin part protruding out of the substrate, a gate structure is formed on the substrate, and the gate structure stretches across the fin part and covers part of the top and part of the side wall of the fin part;
forming a first source-drain doping layer in the fin parts on two sides of the grid structure;
forming at least one second source-drain doping layer on the first source-drain doping layer, wherein the step of forming the second source-drain doping layer comprises the following steps: forming a protective layer which is positioned on the substrate and exposes the first source drain doping layer or a second source drain doping layer positioned below the first source drain doping layer; forming a second source-drain doping layer on the first source-drain doping layer exposed out of the protective layer or the second source-drain doping layer positioned below the first source-drain doping layer;
forming an interlayer dielectric layer on the protective layer, wherein the interlayer dielectric layer covers the second source drain doping layer;
and forming a contact hole plug surrounding the first source-drain doping layer and the second source-drain doping layer in the interlayer dielectric layer and the protective layer.
2. The method for forming a semiconductor structure according to claim 1, wherein the step of forming the first source-drain doping layer comprises: etching the fin parts on two sides of the grid structure, and forming grooves in the fin parts on two sides of the grid structure; and forming the first source drain doping layer in the groove, wherein the top of the first source drain doping layer is higher than the top of the fin part.
3. The method for forming the semiconductor structure according to claim 2, wherein the number of the second source-drain doping layers is one, and the step of forming the second source-drain doping layers includes: forming a protective layer exposing the top of the first source-drain doping layer on the substrate exposed by the gate structure, wherein the top of the protective layer is higher than the top of the fin portion and lower than the top of the first source-drain doping layer;
and forming the epitaxial layer on the first source-drain doping layer exposed out of the protective layer by adopting an epitaxial process, and forming the second source-drain doping layer by in-situ self-doping ions in the process of forming the epitaxial layer.
4. The method of claim 1, wherein the protective layer is made of a dielectric material.
5. The method of claim 1, wherein the protective layer is the same material as the interlevel dielectric layer.
6. The method of forming a semiconductor structure of claim 1, wherein the step of forming the contact hole plug comprises: etching the interlayer dielectric layer and the protective layer to form a contact hole exposing the first source drain doping layer and the second source drain doping layer; and forming a contact hole plug for filling the contact hole.
7. The method of forming a semiconductor structure of claim 2, wherein the recess is sigma shaped.
8. The method for forming the semiconductor structure according to claim 1, wherein the first source-drain doping layer or the second source-drain doping layer has a diamond structure in an extending direction perpendicular to the fin portion.
9. The method of forming a semiconductor structure according to claim 6, wherein after forming the contact hole and before forming the contact hole plug, further comprising: and forming silicide layers on the surfaces of the first source-drain doping layer and the second source-drain doping layer exposed from the contact hole.
10. A semiconductor structure, comprising:
a substrate;
the fin part protrudes out of the substrate;
the grid electrode structure stretches across the fin part and covers part of the top and part of the side wall of the fin part;
the first source drain doping layer is positioned in the fin parts on two sides of the grid structure;
the protective layer is positioned on the substrate, is at the same layer with the first source-drain doping layer and exposes the top of the first source-drain doping layer;
at least one second source-drain doping layer located on the first source-drain doping layer exposed out of the protection layer;
the interlayer dielectric layer is positioned on the protective layer and covers the second source drain doping layer;
and the contact hole plug is positioned in the interlayer dielectric layer and the protective layer and surrounds the first source-drain doping layer and the second source-drain doping layer.
11. The semiconductor structure of claim 10, wherein a top of the first source drain doping layer is higher than a top of the fin;
the number of the second source-drain doped layers is one;
the top of the protective layer is higher than the top of the fin part and lower than the top of the first source drain doping layer;
the second source-drain doping layer comprises an epitaxial layer which is positioned on the first source-drain doping layer exposed out of the protective layer and is doped with ions.
12. The semiconductor structure of claim 10, wherein a material of the protective layer is a dielectric material.
13. The semiconductor structure of claim 10, wherein the protective layer is the same material as the interlevel dielectric layer.
14. The semiconductor structure of claim 10, wherein a material of the protective layer comprises silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, or silicon oxycarbonitride.
15. The semiconductor structure of claim 10, wherein the semiconductor structure further comprises: and the silicide layers are positioned between the first source drain doping layer and the contact hole plug and between the second source drain doping layer and the contact hole plug.
16. The semiconductor structure of claim 11, wherein a distance between a top of the protection layer and a top of the first source-drain doping layer is 1 nm to 3 nm in a normal direction of the substrate surface.
17. The semiconductor structure of claim 10, wherein a top of the second source-drain doping layer is lower than a top of the gate structure along a normal direction of the substrate surface, and a distance between the top of the second source-drain doping layer and the top of the gate structure is 100 to 500 angstroms.
18. The semiconductor structure of claim 10, wherein the first source drain doped layer or the second source drain doped layer is diamond-shaped along a direction perpendicular to the fin.
CN201910696119.XA 2019-07-30 2019-07-30 Semiconductor structure and forming method thereof Active CN112309858B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910696119.XA CN112309858B (en) 2019-07-30 2019-07-30 Semiconductor structure and forming method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910696119.XA CN112309858B (en) 2019-07-30 2019-07-30 Semiconductor structure and forming method thereof

Publications (2)

Publication Number Publication Date
CN112309858A true CN112309858A (en) 2021-02-02
CN112309858B CN112309858B (en) 2023-06-13

Family

ID=74485699

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910696119.XA Active CN112309858B (en) 2019-07-30 2019-07-30 Semiconductor structure and forming method thereof

Country Status (1)

Country Link
CN (1) CN112309858B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112447593A (en) * 2019-08-30 2021-03-05 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130069128A1 (en) * 2011-09-16 2013-03-21 Kimitoshi Okano Semiconductor device and manufacturing method of the same
CN103996711A (en) * 2013-01-24 2014-08-20 三星电子株式会社 Semiconductor device and fabricating method thereof
CN104078355A (en) * 2013-03-28 2014-10-01 中芯国际集成电路制造(上海)有限公司 Forming method of fin field effect transistor
US20140299934A1 (en) * 2013-04-09 2014-10-09 Samsung Electronics Co., Ltd. Semiconductor Device and Method for Fabricating the Same
JP2014216409A (en) * 2013-04-24 2014-11-17 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． Semiconductor device manufacturing method
CN104347425A (en) * 2013-08-01 2015-02-11 三星电子株式会社 Semiconductor device and method for fabricating the same
US20150295089A1 (en) * 2014-04-11 2015-10-15 Taiwan Semiconductor Manufacturing Company, Ltd. Finfets with contact-all-around
US20170104065A1 (en) * 2015-10-12 2017-04-13 International Business Machines Corporation Semiconductor device including dual-layer source/drain region
US20170148797A1 (en) * 2015-11-20 2017-05-25 Samsung Electronics Co., Ltd. Semiconductor devices and methods of manufacturing the same
US20170345759A1 (en) * 2016-05-31 2017-11-30 Taiwan Semiconductor Manufacturing Co., Ltd. A method of forming contact trench
US20170373159A1 (en) * 2016-06-24 2017-12-28 International Business Machines Corporation Fabrication of a vertical fin field effect transistor with a reduced contact resistance
CN109037213A (en) * 2017-06-09 2018-12-18 中芯国际集成电路制造(上海)有限公司 A kind of semiconductor devices and preparation method thereof and electronic device
CN109148581A (en) * 2017-06-28 2019-01-04 中芯国际集成电路制造(上海)有限公司 A kind of manufacturing method of semiconductor devices
US20190067474A1 (en) * 2017-08-25 2019-02-28 Globalfoundries Inc. Vertical finfet with improved top source/drain contact
US20190109052A1 (en) * 2017-10-06 2019-04-11 International Business Machines Corporation Nanosheet substrate isolated source/drain epitaxy by nitrogen implantation
CN109817525A (en) * 2017-11-22 2019-05-28 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

Patent Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130069128A1 (en) * 2011-09-16 2013-03-21 Kimitoshi Okano Semiconductor device and manufacturing method of the same
CN103996711A (en) * 2013-01-24 2014-08-20 三星电子株式会社 Semiconductor device and fabricating method thereof
CN104078355A (en) * 2013-03-28 2014-10-01 中芯国际集成电路制造(上海)有限公司 Forming method of fin field effect transistor
US20140299934A1 (en) * 2013-04-09 2014-10-09 Samsung Electronics Co., Ltd. Semiconductor Device and Method for Fabricating the Same
JP2014216409A (en) * 2013-04-24 2014-11-17 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． Semiconductor device manufacturing method
CN104347425A (en) * 2013-08-01 2015-02-11 三星电子株式会社 Semiconductor device and method for fabricating the same
US20150295089A1 (en) * 2014-04-11 2015-10-15 Taiwan Semiconductor Manufacturing Company, Ltd. Finfets with contact-all-around
US20170104065A1 (en) * 2015-10-12 2017-04-13 International Business Machines Corporation Semiconductor device including dual-layer source/drain region
US20170148797A1 (en) * 2015-11-20 2017-05-25 Samsung Electronics Co., Ltd. Semiconductor devices and methods of manufacturing the same
US20170345759A1 (en) * 2016-05-31 2017-11-30 Taiwan Semiconductor Manufacturing Co., Ltd. A method of forming contact trench
US20170373159A1 (en) * 2016-06-24 2017-12-28 International Business Machines Corporation Fabrication of a vertical fin field effect transistor with a reduced contact resistance
CN109037213A (en) * 2017-06-09 2018-12-18 中芯国际集成电路制造(上海)有限公司 A kind of semiconductor devices and preparation method thereof and electronic device
CN109148581A (en) * 2017-06-28 2019-01-04 中芯国际集成电路制造(上海)有限公司 A kind of manufacturing method of semiconductor devices
US20190067474A1 (en) * 2017-08-25 2019-02-28 Globalfoundries Inc. Vertical finfet with improved top source/drain contact
US20190109052A1 (en) * 2017-10-06 2019-04-11 International Business Machines Corporation Nanosheet substrate isolated source/drain epitaxy by nitrogen implantation
CN109817525A (en) * 2017-11-22 2019-05-28 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112447593A (en) * 2019-08-30 2021-03-05 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN112447593B (en) * 2019-08-30 2024-03-01 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

Also Published As

Publication number Publication date
CN112309858B (en) 2023-06-13

Similar Documents

Publication Publication Date Title
US11411090B2 (en) Contact structures for gate-all-around devices and methods of forming the same
TW201917780A (en) A method of manufacturing a semiconductor device
CN112309860B (en) Semiconductor structure and forming method thereof
TW202044417A (en) Semiconductor devices and methods for forming the same
US9502527B2 (en) Semiconductor device structure having multi-layered insulating cap layers over metal gate
US11282748B2 (en) Semiconductor device and method of forming the same
US11676869B2 (en) Semiconductor device and manufacturing method thereof
CN111863711B (en) Semiconductor structure and forming method thereof
CN111106009B (en) Semiconductor structure and forming method thereof
CN110718465B (en) Semiconductor structure and forming method thereof
CN112151376B (en) Semiconductor structure and forming method thereof
US11955535B2 (en) Methods for forming air spacers in semiconductor devices
CN112309858B (en) Semiconductor structure and forming method thereof
CN111554578B (en) Semiconductor structure and forming method thereof
CN111463275B (en) Semiconductor structure and forming method thereof
CN112309862A (en) Semiconductor structure and forming method thereof
CN110808286B (en) Semiconductor structure and forming method thereof
CN112103249B (en) Semiconductor structure and forming method thereof
US20230411479A1 (en) Semiconductor device and manufacturing method thereof
CN117637745A (en) Semiconductor structure and forming method thereof
CN114664734A (en) Semiconductor structure and forming method thereof
CN114256350A (en) Semiconductor structure and forming method thereof
CN115692413A (en) Semiconductor structure and forming method thereof
CN115732415A (en) Semiconductor structure and forming method thereof
CN117374074A (en) Semiconductor structure and forming method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant