CN112305254A - FPGA-based EMD motion detection system - Google Patents
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Abstract
The invention discloses an FPGA-based EMD motion detection system, which comprises an FPGA system information processing platform, an ADC synchronous signal acquisition system daughter board and an infrared photodiode circuit daughter board; every two adjacent infrared photodiodes form a pair and are connected to an ADC synchronous signal acquisition system daughter board through an infrared photodiode circuit, analog signals acquired by the infrared photodiodes are converted into data signals through ADC analog-to-digital conversion and transmitted to an FPGA system information processing platform to serve as input of an EMD motion detection model; analyzing the input signal through an EMD motion detection model to realize the detection of the direction and the speed of a moving object with a specific light source; the FPGA information processing platform is used for calculating the EMD model of the multi-channel synchronously acquired motion information, so that the accurate detection of the speed and direction of a high-speed moving object can be realized, substantial reference value is provided for the research and development and application of the EMD model in the field of visual detection of unmanned aerial vehicles and robots, and the application prospect is very obvious.
Description
Technical Field
The invention relates to the technical field of visual detection, in particular to an FPGA-based EMD motion detection system.
Background
The EMD motion detection model is based on the characteristics of small insect compound eye volume, large field of view and high sensitivity, takes an embedded system FPGA as a development environment, designs a motion detection model based on the EMD model basic principle of a biological vision mechanism, and realizes the direction and speed detection of a full-view-angle moving object. In recent years, researchers have proposed various design schemes for realizing analog signal acquisition of the system, for example, CN104980156A and CN210514976U both disclose an ADC synchronous acquisition system based on an FPGA, which is limited to AD acquisition of medium-high frequency signals or low-frequency signals, and does not have a motion detection function including full-signal multi-channel acquisition and EMD from low frequency to high frequency. For example, a moving target real-time detection and tracking algorithm based on FPGA and an implementation technology thereof, which are published in the journal of optical technology by Schchenk, Li Binxia and the like, a moving target detection and tracking system in a color video image is constructed on an FPGA development board; the design of the fixed background difference method has no limit on the moving speed of the target, but when the frame difference method is used for effectively detecting the fast moving target, the frame difference interval of the target is larger than 3.2 pixels. The design has high requirements on motion background, analog signals are acquired by using an image acquisition mode, and an EMD model is not used for motion detection. For example, the FPGA design and implementation of a biological Reichardt motion detector and a receptive field template published in the journal of Chinese image graphic journal of KoljKuehnlenz, Wu Hai Yan and the like realize 6 receptive field templates based on a fly vision system on an FPGA platform so as to realize the estimation of a simple self motion mode, for example, a translation and rotation related algorithm of a camera, the design uses the FPGA to realize the EMD model consistent with the invention on the design principle, but has substantial difference on the platform construction and the function realization. The infrared photoelectric sensor is designed to be used as analog signal acquisition equipment based on the characteristics that the infrared imaging equipment has the advantages of long working distance, strong concealment performance, capability of working day and night and the like, can be widely applied to the military and civil fields, can adapt to different background environments, and has small detection error and good real-time performance. The photodiode and the high-speed multi-channel ADC module are used for collecting optical flow field information, the sampling rate of signal collection is higher, information transmission is higher in speed and accuracy, and detection of 360-degree full-view-angle range is achieved.
Disclosure of Invention
The purpose of the invention is as follows: the invention provides an FPGA-based EMD motion detection system, which is based on the design of acquisition circuits such as an ADC high-speed multi-channel acquisition system daughter board and an infrared photoelectric receptor, an FPGA signal processing platform and the like, realizes the high-speed and accurate detection of the direction and the speed of a full-view one-dimensional moving object, overcomes the defects of the conventional EMD motion detection system, and has the characteristics of high sampling rate, high detection efficiency, large detection visual angle, large dynamic range, good synchronism and the like, thereby having wide application prospect.
The technical scheme is as follows: in order to achieve the purpose, the invention adopts the technical scheme that:
an FPGA-based EMD motion detection system comprises an FPGA system information processing platform, an ADC synchronous signal acquisition system daughter board and an infrared photodiode circuit daughter board; every two adjacent infrared photodiodes form a pair and are connected to an ADC synchronous signal acquisition system daughter board through an infrared photodiode circuit, analog signals acquired by the infrared photodiodes are converted into data signals through ADC analog-to-digital conversion and transmitted to an FPGA system information processing platform to serve as input of an EMD motion detection model; the input signal is analyzed through an EMD motion detection model, and the direction and the speed of a moving object with a specific light source are detected.
The infrared photodiode circuit daughter board comprises 16 infrared photodiodes, the 16 infrared photodiodes are distributed on the circumference of the circular integrated circuit daughter board at equal angular intervals, every two adjacent channels are used as a pair of signal input, and the linear distance between the root parts of every two adjacent photodiodes is 1 cm;
the ADC synchronous signal acquisition system daughter board comprises 16 analog signal acquisition channels, and the output ends of the infrared photoelectric receiving diodes are sequentially connected with the analog signal acquisition channels;
the FPGA system information processing platform comprises an EMD motion detection model designed based on an FPGA.
Further, the design principle of the EMD motion detection model is as follows:
step S1, generating and quantizing a filter coefficient by adopting MATLABFDAtool, and designing an FIR low-pass filter;
designing filter coefficients by adopting MATLAB, and directly calling the filter coefficients by utilizing an IP core in Quartus software to generate a required low-pass filter; calling an FDAtool tool box to design a 17-order Hamming window function low-pass FIR filter; selecting a full-parallel distributed algorithm structure for the FIR filter, and directly loading the designed filter coefficients in the MATLAB;
step S2, designing a multiplier based on the FPGA system information processing platform;
designing a 12 x 25 bit binary data multiplier, calling an LPM _ MULT multiplier IP core in the Quartus, and instantiating the multiplier module into a main program, wherein the multiplier comprises two identical sub-multipliers;
step S3, designing a subtracter based on the FPGA system information processing platform;
performing subtraction operation on the output of two paths of multipliers collected under the same sampling clock signal, wherein the subtracter is generated through the IP core design of an LPM _ ADD _ SUB subtracter in the Quartus and outputs 37-bit signed binary data as the direction detection result of the whole EMD model; the positive and negative values of the output data reflect the sequence of the two paths of received input data and serve as a judgment basis for detecting the one-dimensional direction of the moving object.
Furthermore, the ADC synchronous signal acquisition system daughter board is connected to the FPGA system information processing platform through a patch panel; and clock signals of all channels are connected to clock pins of the FPGA system information processing platform, and the FPGA system clock frequency division provides clock signals.
Furthermore, the ADC synchronous signal acquisition system daughter board comprises an attenuation circuit, an AD8065 operational amplifier and a circuit thereof, and a power supply circuit; a single power supply is adopted for supplying power, and the frequency of the parallel synchronous acquisition data is 1Hz-50 MHz; the voltage range of the input signal is-5V- + 5V.
Furthermore, a high-performance sample-and-hold amplifier and a reference voltage source are arranged in the ADC synchronous signal acquisition system daughter board, and a steering engine differential pipeline architecture is adopted, so that no code loss is realized in a working temperature range.
Furthermore, the incidence angle range of the infrared photodiode is-20 degrees to +20 degrees, and the optical signal with specific wavelength is received and converted into a voltage signal of 0V-5V; the power supply voltage of the photodiode is +5V, and the response wave peak is 950 nm.
Has the advantages that: the system has the following advantages:
the invention collects the optical flow field information by utilizing the photoelectric receptor and the high-speed multi-channel ADC module, the sampling rate of signal collection is higher, the information calculation is higher and more accurate, and the detection speed and the visual angle range are larger. The FPGA information processing platform is used for calculating the EMD model of the multi-channel synchronously acquired motion time information, so that the accurate detection of the speed and direction of a high-speed moving object can be realized, substantial reference value is provided for the research and development and application of the EMD model in the field of visual detection of unmanned aerial vehicles and robots, and the method has wide applicability.
Drawings
FIG. 1 is a schematic diagram of a system design flow provided by the present invention;
FIG. 2 is a timing diagram of an ADC synchronization signal acquisition system provided by the present invention;
FIG. 3 is a flow chart of the EMD motion detection model design provided by the present invention;
FIG. 4 is a diagram of the amplitude-frequency response of the FIR low-pass filter in the EMD motion detection model provided by the present invention;
FIG. 5 is a schematic diagram of the structural design of the EMD motion detection model provided by the present invention.
Detailed Description
The present invention will be further described with reference to the accompanying drawings.
As shown in fig. 1, an EMD motion detection system based on FPGA includes an FPGA system information processing platform, an ADC synchronization signal acquisition system daughter board, and an infrared photodiode circuit daughter board; every two adjacent infrared photodiodes form a pair and are connected to an ADC synchronous signal acquisition system daughter board through an infrared photodiode circuit, analog signals acquired by the infrared photodiodes are converted into data signals through ADC analog-to-digital conversion and transmitted to an FPGA system information processing platform to serve as input of an EMD motion detection model; the input signal is analyzed through an EMD motion detection model, and the direction and the speed of a moving object with a specific light source are detected.
The infrared photodiode circuit daughter board comprises 16 infrared photodiodes, the 16 infrared photodiodes are distributed on the circumference of the circular integrated circuit daughter board at equal angular intervals, and every two adjacent channels are used as a pair of signal inputs.
The ADC synchronous signal acquisition system daughter board comprises 16 analog signal acquisition channels, the output ends of the infrared photoelectric receiving diodes are sequentially connected with the analog signal acquisition channels, and the distance between the root parts of every two adjacent photoelectric diodes is 1 cm;
the FPGA system information processing platform comprises an EMD motion detection model designed based on an FPGA.
The infrared photodiode is used as an analog signal acquisition system, the output ends of 16 infrared photodiodes are connected to 16 analog signal acquisition channels of the ADC, the incidence angle range of the photodiodes is-20 degrees to +20 degrees, optical signals with specific wavelengths are received and converted into voltage signals of 0V to 5V, the power supply voltage of the photodiodes is +5V, and the response wave peak is 950 nm. The response of the infrared photodiode to the optical signal is approximate to a sine wave, and the sine analog signal voltage of 0V to +5V is input to the ADC acquisition daughter board.
The ADC synchronous signal acquisition system daughter board comprises an attenuation circuit, an AD8065 operational amplifier and a circuit thereof, and a power supply circuit; a single power supply is adopted for supplying power, and the frequency of the parallel synchronous acquisition data is 1Hz-50 MHz; the voltage range of the input signal is-5V- +5V, and the input signal is converted into 12-bit binary data to be transmitted to the FPGA information processing platform as the signal input of the EMD model. The ADC synchronous signal acquisition system daughter board is connected to the FPGA system information processing platform through the adapter board; and clock signals of all channels are connected to clock pins of the FPGA system information processing platform, and the FPGA system clock frequency division provides clock signals.
The ADC signal acquisition chip selects an AD9226 chip, a single chip corresponds to a signal acquisition channel, each channel needs a signal acquisition clock AD _ CLK, the AD _ CLK is a 1.6MHz sampling clock obtained by 50MHz of an FPGA system clock through PLL frequency division, the AD chip acquires data in one clock period, data acquisition can be carried out as long as a clock signal is provided, and the acquisition time sequence is as shown in figure 2.
The highest sampling rate of the AD chip selected by the system reaches 50MHz, the bit width of each channel analog signal quantization is 12 bits, each data bit needs a signal output line of the ADC and occupies an IO port of the FPGA, and each channel signal needs 12 data bit IO ports of the FPGA and 1 data acquisition clock IO port.
The attenuation circuit of the ADC synchronous signal acquisition system daughter board selects AD9226 for an AD acquisition chip, the voltage input range of the attenuation circuit is 1V-3V, the attenuation circuit is needed to meet the voltage input range of-5V- +5V, the conversion formula is Vout ═ 1/5) Vin +2, and when Vin is-5V, Vout ═ 1V; when Vin is 5V, Vout is 3V; after the digital signal is converted into a numerical value signal, the conversion formula is reversely operated, and the digital signal is amplified to obtain a real numerical value of the input voltage.
The operational amplifier of the ADC synchronous signal acquisition system daughter board adopts a single-path voltage feedback type amplifier AD8065 to provide FET input, adopts a typical power supply current of 6.4mA of each amplifier, and can drive a load current of up to 30 mA.
The EMD motion detection model based on FPGA design is shown in FIG. 3, and the structural design principle is shown in FIG. 5.
The following takes a pair of EMD models as an example to illustrate the EMD information processing mechanism of the present design, and the rest seven pairs of EMD models can be obtained in the same way.
And step S1, generating and quantizing the filter coefficients by adopting MATLABFDAtool, and designing an FIR low-pass filter.
Designing filter coefficients by adopting MATLAB, and directly calling the filter coefficients by utilizing an IP core in Quartus software to generate a required low-pass filter; calling an FDAtool tool box to design a 17-order Hamming window function low-pass FIR filter; selecting a full-parallel distributed algorithm structure for the FIR filter, and directly loading the designed filter coefficients in the MATLAB; the sampling frequency is 2KHz, and the cut-off frequency is 0.6 KHz. After the filter is designed by using FDAtool, the original coefficient is quantized into 16 bits, the 16 bits are exported to a command line serial port, and the filter coefficient is written into a TEST. An FIR low-pass filter is designed by directly adopting an IP core for FPGA, the FIR filter adopts a full-parallel distributed algorithm structure in the design, and the designed filter coefficient (TXT format) in MATLAB is directly loaded, so that the universality of the module and the inheritance of the filter coefficient are facilitated, and a filter amplitude-frequency response graph is generated as shown in figure 4.
The FIR filter is designed to mainly realize the functions of filtering and delaying, a multiply-accumulate operation is performed inside an IP core of the filter, the times of the accumulate calculation are determined by the order of the filter, the order of the filter is 17, the clock period of the filter is 1.6MHz of the system sampling clock period, and the delay effect reaches 26 system clock periods. The filter design principle in Quartus is as D1, D2 in FIG. 1. And filtering the 12-bit data signal converted by the ADC high-speed acquisition module through an FIR low-pass filter based on the FPGA signal processing platform to obtain a 25-bit data signal.
Step S2, designing a multiplier based on the FPGA system information processing platform;
the module designs a 12 x 25 bit binary data multiplier, calls the LPM _ MULT multiplier IP core in Quartus, and instantiates the multiplier module to the main program. Two paths in the EMD model require two multipliers, so this multiplier is called twice in practical applications. The multiplier module is designed in Quartus as M1 and M2 in FIG. 1.
Step S3, designing a subtracter based on the FPGA system information processing platform;
the module is a total output module of an EMD model, outputs of two paths of multipliers collected under the same sampling clock signal are subjected to subtraction operation, a subtracter is generated through the IP core design of an LPM _ ADD _ SUB subtracter in the Quartus, and 37-bit signed binary data are output and are the direction detection result of the whole EMD model. The positive and negative values can directly reflect the sequence of receiving two paths of input data, and the sequence is used as a judgment basis for detecting the one-dimensional direction of the moving object by simulating the sequence of the two photoreceptors sensing light source signals. The subtractor module designs a schematic diagram in Quartus as S in fig. 1.
For the optical flow field analog signal acquisition of each channel, the output of an ADC acquisition module can be approximate to sine output response, the time interval of detecting adjacent wave crests of two acquisition channels is the movement time of a moving object, the movement time is divided by the distance interval of 1cm between adjacent photodiodes, the movement speed can be calculated, the movement speed is the speed detection result of the EMD model, and the movement speed of 0-100 m/s can be detected.
The schematic diagram of the structural design of the EMD system designed in Quartus is shown in FIG. 5.
The invention discloses an EMD motion detection device and method based on an FPGA. The EMD motion detection principle is adopted in software and hardware design, so that the motion information of the full-view-angle height moving object can be acquired and processed, and accurate speed and direction information can be obtained. The invention has the characteristics of high system integration, small volume, high sampling rate, high detection efficiency, large detection visual angle, large dynamic range, good synchronism, low cost and the like. The method has stronger practicability in the aspects of signal acquisition and processing, speed and direction detection of moving objects and the like, and can be widely applied to the field of vision processing of unmanned aerial vehicles, robots and the like.
The above description is only of the preferred embodiments of the present invention, and it should be noted that: it will be apparent to those skilled in the art that various modifications and adaptations can be made without departing from the principles of the invention and these are intended to be within the scope of the invention.
Claims (6)
1. An FPGA-based EMD motion detection system is characterized by comprising an FPGA system information processing platform, an ADC synchronous signal acquisition system daughter board and an infrared photodiode circuit daughter board; every two adjacent infrared photodiodes form a pair and are connected to an ADC synchronous signal acquisition system daughter board through an infrared photodiode circuit, analog signals acquired by the infrared photodiodes are converted into data signals through ADC analog-to-digital conversion and transmitted to an FPGA system information processing platform to serve as input of an EMD motion detection model; the input signal is analyzed through an EMD motion detection model, and the direction and the speed of a moving object with a specific light source are detected.
The infrared photodiode circuit daughter board comprises 16 infrared photodiodes, the 16 infrared photodiodes are distributed on the circumference of the circular integrated circuit daughter board at equal angular intervals, and every two adjacent channels are used as a pair of signal inputs;
the ADC synchronous signal acquisition system daughter board comprises 16 analog signal acquisition channels, the output ends of the infrared photoelectric receiving diodes are sequentially connected with the analog signal acquisition channels, and the linear distance between the root parts of every two adjacent photoelectric diodes is 1 cm;
the FPGA system information processing platform comprises an EMD motion detection model designed based on an FPGA.
2. The FPGA-based EMD motion detection system of claim 1, wherein the EMD motion detection model is designed according to the following principle:
step S1, generating and quantizing a filter coefficient by adopting MATLAB FDAtool, and designing an FIR low-pass filter;
designing filter coefficients by adopting MATLAB, and directly calling the filter coefficients by utilizing an IP core in Quartus software to generate a required low-pass filter; calling an FDA tool box to design a 17-order Hamming window function low-pass FIR filter; selecting a full-parallel distributed algorithm structure for the FIR filter, and directly loading the designed filter coefficients in the MATLAB;
step S2, designing a multiplier based on the FPGA system information processing platform;
designing a 12 x 25 bit binary data multiplier, calling an LPM _ MULT multiplier IP core in the Quartus, and instantiating the multiplier module into a main program, wherein the multiplier comprises two identical sub-multipliers;
step S3, designing a subtracter based on the FPGA system information processing platform;
performing subtraction operation on the output of two paths of multipliers collected under the same sampling clock signal, wherein the subtracter is generated through the IP core design of an LPM _ ADD _ SUB subtracter in the Quartus and outputs 37-bit signed binary data as the direction detection result of the whole EMD model; the positive and negative values of the output data reflect the sequence of the two paths of received input data and serve as a judgment basis for detecting the one-dimensional direction of the moving object.
3. The FPGA-based EMD motion detection system of claim 1, wherein the ADC synchronous signal acquisition system daughter board is switched to the FPGA system information processing platform through an adapter board; and clock signals of all channels are connected to clock pins of the FPGA system information processing platform, and the FPGA system clock frequency division provides clock signals.
4. The FPGA-based EMD motion detection system of claim 3, wherein the ADC synchronous signal acquisition system daughter board comprises an attenuation circuit, an AD8065 operational amplifier and its circuit, and a power supply circuit; a single power supply is adopted for supplying power, and the frequency of the parallel synchronous acquisition data is 1Hz-50 MHz; the voltage range of the input signal is-5V- + 5V.
5. The FPGA-based EMD motion detection system of claim 4, wherein the ADC synchronization signal acquisition system daughter board is internally provided with a high-performance sample-and-hold amplifier and a reference voltage source, and a steering engine differential pipeline architecture is adopted to realize no code loss within a working temperature range.
6. The FPGA-based EMD motion detection system of claim 1, wherein the incidence angle range of the infrared photodiode is-20 ° - +20 °, and the optical signal with a specific wavelength is received and converted into a voltage signal of 0V-5V; the power supply voltage of the photodiode is +5V, and the response wave peak is 950 nm.
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Application publication date: 20210202 |