CN112289685A - PIN diode, forming method thereof and electrostatic protection structure - Google Patents
PIN diode, forming method thereof and electrostatic protection structure Download PDFInfo
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
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Abstract
A PIN diode and a forming method and an electrostatic protection structure thereof are provided, wherein the PIN diode comprises at least two layers of stacked structures which are sequentially stacked and positioned on a substrate, and each layer of stacked structure comprises: a first semiconductor layer doped with a first type of dopant ions; a first intrinsic layer on the first semiconductor layer; a second semiconductor layer on the first intrinsic layer, the second semiconductor layer being doped with a second type of dopant ions, the first type being different from the second type; a second intrinsic layer on the second semiconductor layer. The PIN diode formed on the same substrate area has larger junction area, so that the junction heat dissipation and flow guiding capacity is effectively enhanced, and the parasitic capacitance is reduced.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a PIN diode, a forming method thereof and an electrostatic protection structure consisting of the PIN diode.
Background
In the manufacture and application of integrated circuit chips, with the continuous improvement of super-large-scale integrated circuit process technology, the current CMOS integrated circuit manufacturing technology has entered the deep submicron stage, the size of MOS devices has been continuously reduced, the thickness of gate oxide layer is thinner and thinner, the voltage endurance reliability of MOS devices has been significantly reduced, and the damage of Electrostatic Discharge (ESD) to integrated circuits has become more and more significant.
In the interface circuit of the integrated circuit, in order to prevent the electrostatic discharge from damaging the integrated circuit, a corresponding electrostatic protection circuit is required to be arranged, and the electrostatic protection circuit not only needs to protect the electronic element from being damaged by the electrostatic discharge, but also needs to ensure that the system can still continue to operate in case of the electrostatic discharge event. With the increasing working speed of the integrated circuit interface, the design difficulty of the electrostatic protection circuit for the integrated circuit interface circuit is also increasing, and the existing electrostatic protection circuit generally adopts two diodes which are connected in series at the input/output interface of the integrated circuit. When electrostatic discharge occurs, the diode is forward biased, the on-state resistance is small, and the charge can be quickly released without influencing an integrated circuit; when the integrated circuit works normally, the diode is reversely biased, the resistance is large, and the influence on input and output signals is small. In the practical application process, the polysilicon PIN diode is isolated from the substrate, so that the electrostatic protection circuit has small influence on signals of an I/O interface; and the trigger voltage can be adjusted by adjusting the thickness of the I layer, so that the method becomes an option.
However, the reliability of the existing PIN diode electrostatic protection still needs to be improved.
Disclosure of Invention
The invention aims to solve the technical problem of how to improve the reliability of the PIN diode in electrostatic protection.
The invention provides a forming method of a PIN diode, which comprises the following steps:
providing a substrate;
forming a first semiconductor layer on the substrate, wherein the first semiconductor layer is doped with first type doping ions;
forming a first intrinsic layer on the first semiconductor layer;
forming a second semiconductor layer on the first intrinsic layer, the second semiconductor layer being doped with a second type of dopant ions, the first type of dopant ions being different from the second type of dopant ions;
forming a second intrinsic layer on the second semiconductor layer;
the steps of sequentially forming the first semiconductor layer, the first intrinsic layer, the second semiconductor layer and the second intrinsic layer are repeated on the surface of the second intrinsic layer.
Optionally, the first semiconductor layer and the second semiconductor layer are made of silicon, germanium or silicon germanium.
Optionally, the first type of dopant ions and the second type of dopant ions are N-type dopant ions or P-type dopant ions.
Optionally, the first intrinsic layer and the second intrinsic layer are made of the same material, and the first semiconductor layer and the second semiconductor layer are made of the same material.
Optionally, the number of times of repeating the steps of sequentially forming the first semiconductor layer, the first intrinsic layer, the second semiconductor layer, and the second intrinsic layer is at least 1.
Optionally, all the first semiconductor layers are electrically connected together to serve as one electrode of the PIN diode, and all the second semiconductor layers are connected together to serve as the other electrode of the PIN diode, so as to form the PIN diode in a parallel mode.
Optionally, the first semiconductor layer at the bottom layer is used as one of the electrodes of the PIN diode, and the second semiconductor layer at the top layer is used as the other electrode of the PIN diode, so as to form the PIN diode in a series mode.
Optionally, an isolation layer is formed on or in the substrate, and a PIN diode is formed on the isolation layer.
Optionally, the concentration of impurity ions in the first intrinsic layer and the second intrinsic layer is less than 1E17/cm3The size of crystal grains in the first intrinsic layer and the second intrinsic layer is smaller than 0.4um, and the thickness of the first intrinsic layer and the second intrinsic layer is 0.001-0.5 mm.
The present invention also provides a PIN diode comprising:
a substrate;
at least two layers of stacked structures that are located range upon range of in proper order on the base, each layer of stacked structure all includes: a first semiconductor layer doped with a first type of dopant ions; a first intrinsic layer on the first semiconductor layer; a second semiconductor layer on the first intrinsic layer, the second semiconductor layer being doped with a second type of dopant ions, the first type of dopant ions being different from the second type of dopant ions; a second intrinsic layer on the second semiconductor layer.
Optionally, the first semiconductor layer and the second semiconductor layer are made of silicon, germanium or silicon germanium.
Optionally, the first type of dopant ions and the second type of dopant ions are N-type dopant ions or P-type dopant ions.
Optionally, the first intrinsic layer and the second intrinsic layer are made of the same material, and the first semiconductor layer and the second semiconductor layer are made of the same material.
Optionally, all the first semiconductor layers are electrically connected together to serve as one electrode of the PIN diode, and all the second semiconductor layers are connected together to serve as the other electrode of the PIN diode, so that the PIN diode in a parallel mode is formed.
Optionally, the first semiconductor layer at the bottom layer is used as one of the electrodes of the PIN diode, and the second semiconductor layer at the top layer is used as the other electrode of the PIN diode, so as to form the PIN diode in a series mode.
Optionally, the substrate or the substrate has an isolation layer thereon, and the PIN diode is located on the isolation layer.
Optionally, the concentration of impurity ions in the first intrinsic layer and the second intrinsic layer is less than 1E17/cm3The size of crystal grains in the first intrinsic layer and the second intrinsic layer is smaller than 0.4um, and the thickness of the first intrinsic layer and the second intrinsic layer is 0.001-0.5 mm.
The invention also provides an electrostatic protection structure with the PIN diode, which comprises: the PIN diode power supply comprises a power supply end, a grounding end and an input/output interface end positioned between the power supply end and the grounding end, wherein at least one PIN diode is connected between the power supply end and the input/output interface end in series, and at least one PIN diode is connected between the input/output interface end and the grounding end in series.
Compared with the prior art, the technical scheme of the invention has the following advantages:
the forming method of the PIN diode of the invention forms a plurality of longitudinal stacking (or laminating) stacking structures on a substrate, and each stacking structure comprises: the PIN diode comprises a first semiconductor layer, a first intrinsic layer, a second semiconductor layer and a second intrinsic layer, wherein the first intrinsic layer is positioned on the first semiconductor layer, the second semiconductor layer is positioned on the first intrinsic layer, the second intrinsic layer is positioned on the second semiconductor layer, and the topmost stacked structure does not comprise the second intrinsic layer, namely, a longitudinal stacking method is adopted in the PIN diode, so that the formed PIN diode has a larger junction area on the same substrate area, the junction heat dissipation and flow conductivity are effectively enhanced, and the parasitic capacitance is reduced; and because the first semiconductor layer, the first intrinsic layer, the second semiconductor layer and the second intrinsic layer are in multi-layer, the properties of any first semiconductor layer, any first intrinsic layer, any second semiconductor layer and any second intrinsic layer, including doping concentration, grain size, thickness and the like, can be respectively regulated and controlled in the forming process, so that the flexibility is higher, and the reliability is improved.
Furthermore, an isolation layer is arranged in the substrate or the semiconductor substrate, and the PIN diode is formed on the isolation layer subsequently, so that the formed diode is electrically isolated from the substrate through the isolation layer, the Darlington effect is effectively reduced, and the direct current leakage current of the PIN diode is reduced. In this embodiment, the isolation layer is a shallow trench isolation structure.
The PIN diode comprises at least two stacked structures which are sequentially stacked and positioned on the substrate, wherein each stacked structure comprises: a first semiconductor layer doped with a first type of dopant ions; a first intrinsic layer on the first semiconductor layer; a second semiconductor layer on the first intrinsic layer, the second semiconductor layer being doped with a second type of dopant ions, the first type being different from the second type; a second intrinsic layer on the second semiconductor layer. The PIN diode formed on the same substrate area has larger junction area, so that the junction heat dissipation and flow guiding capacity is effectively enhanced, and the parasitic capacitance is reduced.
The electrostatic protection structure comprises the PIN diode, the PIN diode is connected with an input/output interface (I/O) of a circuit, and the PIN diode has a specific structure, so that the heat dissipation and the current conduction of the junction of the PIN diode are effectively enhanced, and the parasitic capacitance is reduced, so that the electrostatic protection capability of the electrostatic protection structure is enhanced.
Drawings
FIGS. 1-6 are schematic structural diagrams illustrating a process of forming a PIN diode according to an embodiment of the invention;
fig. 7 is a schematic structural diagram of an electrostatic protection structure according to an embodiment of the invention.
Detailed Description
As background, the reliability of the existing PIN diode electrostatic protection still needs to be improved.
Researches find that with the continuous reduction of the characteristic size of an integrated circuit, the area of an electrostatic protection polysilicon PIN diode is also continuously reduced, so that the heat dissipation reliability of a PN junction is weakened, the flow guiding reliability is reduced, and the electrostatic protection reliability is further continuously reduced; on the other hand, with the increase of the operating speed of the chip, especially on the chip such as DRAM that needs to read a large amount of data at high speed, the requirements for the parasitic capacitance and the dc leakage current of the electrostatic protection device are more strict.
Therefore, the invention provides a PIN diode, a forming method thereof and an electrostatic protection structure, wherein the PIN diode comprises at least two stacked structures which are sequentially stacked and positioned on a substrate, and each stacked structure comprises: a first semiconductor layer doped with a first type of dopant ions; a first intrinsic layer on the first semiconductor layer; a second semiconductor layer on the first intrinsic layer, the second semiconductor layer being doped with a second type of dopant ions, the first type of dopant ions being different from the second type of dopant ions; a second intrinsic layer on the second semiconductor layer. The PIN diode formed on the same substrate area has larger junction area, so that the junction heat dissipation and flow guiding capacity is effectively enhanced, and the parasitic capacitance is reduced.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In describing the embodiments of the present invention in detail, the drawings are not to be considered as being enlarged partially in accordance with the general scale, and the drawings are only examples, which should not be construed as limiting the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
Fig. 1-6 are schematic structural diagrams illustrating a process of forming a PIN diode according to an embodiment of the invention.
Referring to fig. 1, a substrate 201 is provided.
The substrate 201 serves as a platform for subsequent processes. In an embodiment, the base 201 is a semiconductor substrate, and the material of the semiconductor substrate may be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); or silicon-on-insulator (SOI), germanium-on-insulator (GOI); or may be other materials such as group iii-v compounds such as gallium arsenide. In this embodiment, the semiconductor substrate material is silicon.
In this embodiment, the isolation layer 202 is disposed in the substrate 201 or the semiconductor substrate, and the PIN diode is subsequently formed on the isolation layer 202, so that the formed PIN diode is electrically isolated from the substrate 201 by the isolation layer 202, thereby effectively reducing a darlington effect (the darlington effect is that a parasitic PNP triode and a parasitic NPN triode are formed by a first semiconductor layer and a second semiconductor layer stacked in multiple layers, which are subsequently formed, and the parasitic PNP triode and the parasitic NPN triode form a darlington structure, which can multiply an amplification current, and the darlington effect is an undesirable phenomenon in an electrostatic protection structure), and reducing a direct current leakage current of the PIN diode. In this embodiment, the isolation layer 202 is a shallow trench isolation structure.
In one embodiment, the forming process of the shallow trench isolation structure includes: forming a mask layer (not shown in the figure) on the semiconductor substrate, wherein the mask layer is provided with an opening exposing the surface of the semiconductor substrate; etching the semiconductor substrate along the opening to form a groove in the semiconductor substrate; forming an isolation material layer covering the mask layer and filling the groove; and flattening the isolation material layer until the surface of the semiconductor substrate is exposed, and forming a shallow trench isolation structure in the groove. The shallow trench isolation structure can be a single-layer or multi-layer (more than or equal to 2 layers) stacking structure. In an embodiment, the multi-layer stacked structure is a double-layer stacked structure, and includes a liner layer located on the sidewall and the bottom surface of the groove and a filling layer located on the substrate pad layer and filling the groove, where the liner layer may be made of silicon oxide, and the filling layer may be made of silicon nitride.
In other embodiments, the isolation layer may be formed on the surface of the substrate 201.
Referring to fig. 2, a first semiconductor layer 203 is formed on the substrate 201, and the first semiconductor layer 203 is doped with a first type of dopant ions.
The material of the first semiconductor layer 203 is silicon, germanium or silicon germanium. In this embodiment, the material of the first semiconductor layer 203 is silicon.
The first semiconductor layer 203 is doped with a first type of dopant ions, which are N-type dopant ions or P-type dopant ions. The P-type doped ions are one or more of boron ions, gallium ions or indium ions, and the N-type doped ions are one or more of phosphorus ions, arsenic ions or antimony ions. In this embodiment, the first type of doping ions doped in the first semiconductor layer 203 are P-type impurity ions.
In this embodiment, an in-situ doping chemical vapor deposition process may be used to form the first semiconductor layer 203. Specifically, when the first semiconductor layer 203 is formed by an in-situ doping cvd process, a silicon source gas and impurities are includedA mass source gas, wherein the silicon source gas is SiH4Or SiCl2H4The impurity source gas may be B according to the type of dopant ions2H6、BF3、PH3Or AsH3In this embodiment, the impurity source gas may be B2H6Or BF3。
After the first semiconductor layer 203 is formed, the first semiconductor layer 203 may be patterned.
Referring to fig. 3, a first intrinsic layer 204 is formed on the first semiconductor layer 203.
The material of the first intrinsic layer 204 is undoped or lightly doped (lightly doped) semiconductor material. In this embodiment, the material of the first intrinsic layer 204 is an undoped or lightly doped (lightly doped) semiconductor layer material.
The material of the first intrinsic layer 204 is silicon, germanium or silicon germanium. In this embodiment, the material of the first intrinsic layer 204 is silicon, and the forming process of the first intrinsic layer 204 is a chemical vapor deposition process.
In an embodiment, the leakage current is reduced by adjusting the thickness or (and) the concentration of doped impurity ions of the first intrinsic layer 204 and the subsequently formed second intrinsic layer 206 (described later with reference to fig. 3) to reduce the current amplification effect (darlington effect) caused by the darlington tube formed by the parasitic PNP transistor and the parasitic NPN transistor.
In a specific embodiment, the concentration of impurity ions in first intrinsic layer 204 and second intrinsic layer 206 is less than 1E17/cm3The size of crystal grains in the first intrinsic layer 204 and the second intrinsic layer 206 is smaller than 0.4um, the thickness of the first intrinsic layer 204 and the second intrinsic layer 206 is 0.001-0.5 mm, the current amplification effect brought by a Darlington tube formed by a parasitic PNP triode and a parasitic NPN triode can be well reduced by the PIN diode through the parameter setting of the first intrinsic layer 204 and the second intrinsic layer 206, the size of leakage current of the PIN diode is well controlled, meanwhile, the mobility of carriers of the PIN diode is mainly controlled by the mobility of carriers of grain boundaries, and the first intrinsic layer 204 and the second intrinsic layer 206 are used for controlling the mobility of the carriers of the grain boundariesThe influence of the mobility of the current carrier is small, so that the requirements of the PIN diode serving as the electrostatic protection device are better met, and the performance of the electrostatic protection device is improved.
With continued reference to fig. 3, a second semiconductor layer 205 is formed on the first intrinsic layer 204, the second semiconductor layer 205 being doped with a second type of dopant ions, the first type being different from the second type; a second intrinsic layer 206 is formed on the second semiconductor layer 205.
The material of the second semiconductor layer 205 is the same as that of the first semiconductor layer 203, and the material of the second semiconductor layer 205 may be silicon, germanium, or silicon germanium. In this embodiment, the material of the first semiconductor layer 203 is silicon.
The second semiconductor layer 205 is doped with a second type of dopant ions, which is N-type dopant ions or P-type dopant ions. The P-type doped ions are one or more of boron ions, gallium ions or indium ions, and the N-type doped ions are one or more of phosphorus ions, arsenic ions or antimony ions. In this embodiment, the second type of doping ions doped in the second semiconductor layer 205 are N-type impurity ions.
In this embodiment, an in-situ doping cvd process may be used to form the second semiconductor layer 205. Specifically, when the second semiconductor layer 205 is formed by an in-situ doping chemical vapor deposition process, the second semiconductor layer includes a silicon source gas and an impurity source gas, where the silicon source gas is SiH4Or SiCl2H4The impurity source gas may be B according to the type of dopant ions2H6、BF3、PH3Or AsH3In this embodiment, the impurity source gas may be PH3Or AsH3。
Referring to fig. 3, the second intrinsic layer 206 is the same material as the first intrinsic layer 201, and the material of the second intrinsic layer 206 is undoped or lightly doped (lightly doped) semiconductor material. The material of the second intrinsic layer 206 may be silicon, germanium, or silicon-germanium. In this embodiment, the material of the second intrinsic layer 206 is silicon, and the forming process of the second intrinsic layer 206 is a chemical vapor deposition process.
With continued reference to fig. 3, the steps of sequentially forming the first semiconductor layer 203, the first intrinsic layer 204, the second semiconductor layer 205, and the second intrinsic layer are repeated on the surface of the second intrinsic layer 206.
The steps of sequentially forming the first semiconductor layer 203, the first intrinsic layer 204, the second semiconductor layer 205, and the second intrinsic layer are repeated as in the aforementioned steps of forming the first semiconductor layer 203, the first intrinsic layer 204, the second semiconductor layer 205, and the second intrinsic layer 206.
The number of times of repeating the steps of sequentially forming the first semiconductor layer, the first intrinsic layer, the second semiconductor layer and the second intrinsic layer is at least 1, and when the steps of forming the first semiconductor layer, the first intrinsic layer, the second semiconductor layer and the second intrinsic layer are performed for the last time, only the first semiconductor layer, the first intrinsic layer and the second semiconductor layer are formed, and the second intrinsic layer at the topmost layer is not formed, so that the second semiconductor layer at the topmost layer can be used as one electrode of the PIN diode. In this embodiment, the number of times of repeating the steps of forming the first semiconductor layer, the first intrinsic layer, the second semiconductor layer, and the second intrinsic layer is 1, and since the second semiconductor layer 205 at the topmost layer is required to be one electrode of the PIN diode, the second intrinsic layer at the topmost layer is not formed.
In other embodiments, the steps of forming the first semiconductor layer, the first intrinsic layer, the second semiconductor layer, and the second intrinsic layer are repeated more than 1 time, and may be 2 times, 3 times, 4 times, or 5 times or other suitable times. In an embodiment, when the number of times of repeating the steps of forming the first semiconductor layer, the first intrinsic layer, the second semiconductor layer, and the second intrinsic layer is 2 times, the method specifically includes: defining a first semiconductor layer 203, a first intrinsic layer 204, a second semiconductor layer 205 and a second intrinsic layer 206, which have been formed on a substrate, as a first semiconductor layer, a first intrinsic layer, a first second semiconductor layer, a first second intrinsic layer; forming a first semiconductor layer, a first intrinsic layer, a second semiconductor layer and a second intrinsic layer, which are sequentially stacked, on the first and second semiconductor layers, and defining the second semiconductor layer, the first intrinsic layer, the second semiconductor layer and the second intrinsic layer; and forming a first semiconductor layer, a first intrinsic layer and a second semiconductor layer which are sequentially stacked on the second intrinsic layer, wherein the first semiconductor layer, the first intrinsic layer and the second semiconductor layer are defined as a third first semiconductor layer, a third first intrinsic layer and a third second semiconductor layer, and the 2 nd time is the last time of the repeating steps, and the third second intrinsic layer is not formed.
After the plurality of first semiconductor layers, the first intrinsic layer, the second semiconductor layer, and the second intrinsic layer are repeatedly formed, the plurality of stacked structures on the first semiconductor layer may be patterned to expose a portion of the surface of the first semiconductor layer, which is subsequently used to connect the interconnect structure.
In the invention, when forming the PIN diode by using the method, a plurality of diode stack structures 11 and second intrinsic layers 206 are formed, wherein the diode stack structures 11 are alternately stacked in the longitudinal direction, and each diode stack structure 11 comprises: the first semiconductor layer 203, the first intrinsic layer 204 positioned on the first semiconductor layer 203, and the second intrinsic layer 206 positioned between two adjacent diode stacked structures 11 of the second semiconductor layer 205 positioned on the first intrinsic layer 204 are provided, the second intrinsic layer 206 is used for connecting the diode stacked structures 11 up and down, the generation of parasitic triodes is prevented, the electrical performance of the PIN diode is improved, and because a longitudinal stacking method is adopted in the application, the formed PIN diode has a larger junction area on the same substrate area, so that the junction heat dissipation and flow conductivity are effectively enhanced, and the parasitic capacitance is reduced; and because the first semiconductor layer, the first intrinsic layer, the second semiconductor layer and the second intrinsic layer are in multi-layer, the properties of any first semiconductor layer, any first intrinsic layer, any second semiconductor layer and any second intrinsic layer, including doping concentration, grain size, thickness and the like, can be respectively regulated and controlled in the forming process, so that the flexibility is higher, and the reliability is improved.
Referring to fig. 4, a dielectric layer 208 is formed overlying the substrate and the surfaces of the aforementioned several stacks.
The dielectric layer is made of silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant (K less than or equal to 3.9), an ultra-low dielectric constant (K less than or equal to 2.5), other suitable materials, and/or combinations thereof.
The process for forming the dielectric layer 208 may include Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), plasma enhanced chemical vapor deposition (pecvd), atmospheric pressure CVD, low pressure CVD, high density plasma CVD, atomic layer CVD.
Referring to fig. 5, a first interconnect structure 209 and a second interconnect structure 210 are formed in the dielectric layer 208, the first interconnect structure 209 is electrically connected to the first semiconductor layer 203 (first layer first semiconductor layer) at the bottom layer, and the second interconnect structure 210 is electrically connected to the second semiconductor layer 205 at the top layer.
In this embodiment, the first semiconductor layer 203 at the bottom layer is used as one of the electrodes of the PIN diode, the first interconnection structure 209 formed in the dielectric layer 208 is electrically connected to the first semiconductor layer 203 at the bottom layer (the first semiconductor layer), the second semiconductor layer 205 at the top layer is used as the other electrode of the PIN diode, the second interconnection structure 210 formed in the dielectric layer 208 is electrically connected to the second semiconductor layer 205 at the top layer, so as to form the PIN diode in the series mode, and the PIN diode in the series mode can be turned on or off by applying a voltage to the first interconnection structure 209 and the second interconnection structure 210.
The material of the first interconnect structure 209 and the second interconnect structure 210 is metal, and the first interconnect structure 209 and the second interconnect structure 210 may include metal plugs and metal interconnect lines electrically connected to the metal plugs. The first interconnect structure 209 and the second interconnect structure 210 may be damascene structures.
In another embodiment, referring to fig. 6, after forming a plurality of stacked structures (a stacked structure formed by a plurality of first semiconductor layers, a plurality of first intrinsic layers, a plurality of second semiconductor layers, and a plurality of second intrinsic layers), the stacked structures may be etched, a plurality of step structures may be formed on at least one side of the stacked structures, each step structure may correspondingly expose a portion of a surface of the corresponding first semiconductor layer or second semiconductor layer, and then a third interconnection structure and a fourth interconnection structure may be conveniently formed to form a parallel PIN diode. Specifically, the stacked structure is etched and then formed so that the stacked structure has 4 steps, a first step exposes a part of the surface of the first semiconductor layer 203 (first layer first semiconductor layer) at the bottom layer, a second step exposes a part of the surface of the second semiconductor layer 205 (second layer second semiconductor layer) at the bottom layer, a third step exposes the surface of the second layer first semiconductor layer 203, and a fourth step exposes the surface of the second layer second semiconductor layer 205.
With continued reference to fig. 6, after the dielectric layer 208 is formed, a third interconnection structure 211 and a fourth interconnection structure 212 are formed in the dielectric layer 208, the third interconnection structure 211 electrically connects all the first semiconductor layers 203 together to serve as one electrode of the PIN diode, and the fourth interconnection structure connects all the second semiconductor layers 205 together to serve as the other electrode of the PIN diode to form the PIN diode in parallel mode. The parallel mode PIN diode can be turned on or off by applying a voltage across the third interconnect structure 211 and the fourth interconnect structure 212.
In an embodiment, the third interconnect structure 211 includes plugs correspondingly connected to each of the first semiconductor layers 203 and metal layers electrically connecting the plugs, and the fourth interconnect structure 212 includes plugs correspondingly connected to each of the second semiconductor layers 205 and metal layers electrically connecting the plugs.
An embodiment of the present invention further provides a PIN diode, referring to fig. 5, where the PIN diode 21 includes:
a substrate 201;
at least two-layer stacked structure 11 located on the substrate 201 and stacked in sequence, each layer of stacked structure 11 including: a first semiconductor layer 203, wherein the first semiconductor layer 203 is doped with doping ions of a first type; a first intrinsic layer 204 on the first semiconductor layer 203; a second semiconductor layer 205 on the first intrinsic layer 204, the second semiconductor layer 205 being doped with a second type of dopant ions, the first type being different from the second type; a second intrinsic layer 206 on the second semiconductor layer 205.
Specifically, the material of the first semiconductor layer 203 and the second semiconductor layer 205 is silicon, germanium or silicon germanium.
The first type doping ions and the second type doping ions are N type doping ions or P type doping ions.
The first intrinsic layer 203 and the second intrinsic layer 205 are made of the same material, and the first semiconductor layer 203 and the second semiconductor layer 205 are made of the same material.
In this embodiment, the first semiconductor layer 203 on the bottom layer is used as one of the electrodes of the PIN diode 21, and the second semiconductor layer on the top layer is used as the other electrode of the PIN diode 21, thereby forming a series-mode PIN diode. Specifically, still include: and a dielectric layer 208 covering the stacked structure 11 and the substrate 201, wherein a first interconnection structure 209 and a second interconnection structure 210 are formed in the dielectric layer 208, the first interconnection structure 209 is electrically connected with the first semiconductor layer 203 at the bottommost layer (first layer first semiconductor layer), and the second interconnection structure 210 is electrically connected with the second semiconductor layer 205 at the topmost layer.
In another embodiment, all of the first semiconductor layers 203 are electrically connected together as one of the electrodes of the PIN diode 21, and all of the second semiconductor layers 205 are connected together as the other electrode of the PIN diode 21, forming a parallel mode PIN diode. Specifically, referring to fig. 6, a side edge of the diode stack structures 11 has a plurality of step structures, and each step structure correspondingly exposes a portion of the surface of the corresponding first semiconductor layer or the second semiconductor layer. Specifically, the diode stack structures 11 have 4 steps, a first step exposes a portion of the surface of the first semiconductor layer 203 (the first layer of the first semiconductor layer) at the bottom layer, a second step exposes a portion of the surface of the second semiconductor layer 205 (the second layer of the second semiconductor layer) at the bottom layer, a third step exposes the surface of the second layer of the first semiconductor layer 203, and a fourth step exposes the surface of the second layer of the second semiconductor layer 205.
A third interconnection structure 211 and a fourth interconnection structure 212 are formed in the dielectric layer 208, the third interconnection structure 211 electrically connects all the first semiconductor layers 203 together to serve as one electrode of the PIN diode, and the fourth interconnection structure connects all the second semiconductor layers 205 together to serve as the other electrode of the PIN diode, so that the PIN diode in a parallel mode is formed.
In one embodiment, the substrate 201 has an isolation layer 202 on or in the substrate 201, and the PIN diode is located on the isolation layer.
In one embodiment, the concentration of impurity ions in the first and second intrinsic layers 203 and 205 is less than 1E17/cm3The size of the crystal grains in the first intrinsic layer 203 and the second intrinsic layer 205 is less than 0.4um, and the thickness of the first intrinsic layer 203 and the second intrinsic layer 205 is 0.001 to 0.5 mm.
It should be noted that other limitations or descriptions related to the PIN diode in this embodiment are not repeated in this embodiment, and please refer to corresponding limitations or descriptions of the PIN diode forming process in the foregoing embodiment.
An embodiment of the present invention further provides an electrostatic protection structure including the PIN diode described above, and with reference to fig. 7, the electrostatic protection structure includes: the electrostatic protection structure comprises a power supply end VDD, a ground end VSS and an input/output interface end I/O positioned between the power supply end VDD and the ground end VSS, wherein at least one PIN diode 21 is connected between the power supply end VDD and the input/output interface end I/O in series, and at least one PIN diode 21 is connected between the input/output interface end I/O and the ground end VSS in series.
In this embodiment, it is illustrated that the number of the PIN diodes 21 connected in series between the power source terminal VDD and the input/output interface terminal I/O is 2, and the number of the PIN diodes 21 connected in series between the input/output interface terminal I/O and the ground terminal VSS is 2, and in other embodiments, the number of the PIN diodes 21 connected in series may be other.
It should be noted that, for specific limitation or description of the PIN diode 21, reference is made to relevant limitation or description of corresponding parts of the foregoing embodiments, which is not repeated in this embodiment.
Although the present invention has been described with reference to the preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make variations and modifications of the present invention without departing from the spirit and scope of the present invention by using the methods and technical contents disclosed above.
Claims (18)
1. A method of forming a PIN diode, comprising:
providing a substrate;
forming a first semiconductor layer on the substrate, wherein the first semiconductor layer is doped with first type doping ions;
forming a first intrinsic layer on the first semiconductor layer;
forming a second semiconductor layer on the first intrinsic layer, the second semiconductor layer being doped with a second type of dopant ions, the first type of dopant ions being different from the second type of dopant ions;
forming a second intrinsic layer on the second semiconductor layer;
the steps of sequentially forming the first semiconductor layer, the first intrinsic layer, the second semiconductor layer and the second intrinsic layer are repeated on the surface of the second intrinsic layer.
2. The method of forming a PIN diode according to claim 1, wherein a material of the first semiconductor layer and the second semiconductor layer is silicon, germanium, or silicon germanium.
3. The method of forming a PIN diode according to claim 1 or 2, wherein the first type of dopant ions and the second type of dopant ions are N-type dopant ions or P-type dopant ions.
4. The method of forming a PIN diode according to claim 2, wherein the first intrinsic layer and the second intrinsic layer are the same material, and the first semiconductor layer and the second semiconductor layer are the same material.
5. The method for forming a PIN diode according to claim 1, wherein the number of times of repeating the steps of sequentially forming the first semiconductor layer, the first intrinsic layer, the second semiconductor layer, and the second intrinsic layer is at least 1.
6. The method of forming a PIN diode according to claim 1, wherein all of the first semiconductor layers are electrically connected together as one of the electrodes of the PIN diode, and all of the second semiconductor layers are connected together as the other electrode of the PIN diode, forming a parallel mode PIN diode.
7. The method for forming a PIN diode according to claim 1, wherein the PIN diode is formed in a series mode by using the first semiconductor layer at the lowermost layer as one of electrodes of the PIN diode and the second semiconductor layer at the uppermost layer as the other electrode of the PIN diode.
8. The method of forming a PIN diode according to claim 1, wherein an isolation layer is formed on or in the substrate, and the PIN diode is formed on the isolation layer.
9.The method of forming a PIN diode according to claim 1 wherein the concentration of impurity ions in the first intrinsic layer and the second intrinsic layer is less than 1E17/cm3The size of crystal grains in the first intrinsic layer and the second intrinsic layer is smaller than 0.4um, and the thickness of the first intrinsic layer and the second intrinsic layer is 0.001-0.5 mm.
10. A PIN diode, comprising:
a substrate;
at least two layers of stacked structures that are located range upon range of in proper order on the base, each layer of stacked structure all includes: a first semiconductor layer doped with a first type of dopant ions; a first intrinsic layer on the first semiconductor layer; a second semiconductor layer on the first intrinsic layer, the second semiconductor layer being doped with a second type of dopant ions, the first type of dopant ions being different from the second type of dopant ions; a second intrinsic layer on the second semiconductor layer.
11. The PIN diode of claim 10, wherein the material of the first semiconductor layer and the second semiconductor layer is silicon, germanium, or silicon germanium.
12. The PIN diode of claim 10 or 11, wherein the first type of dopant ions and the second type of dopant ions are N-type dopant ions or P-type dopant ions.
13. The PIN diode of claim 10, wherein the first intrinsic layer and the second intrinsic layer are the same material, and the first semiconductor layer and the second semiconductor layer are the same material.
14. The PIN diode of claim 10, wherein all of said first semiconductor layers are electrically connected together as one of the electrodes of the PIN diode and all of said second semiconductor layers are connected together as the other electrode of the PIN diode, forming a parallel mode PIN diode.
15. The PIN diode according to claim 10, wherein the PIN diode is formed in a series mode by using the first semiconductor layer at the lowermost layer as one of electrodes of the PIN diode and the second semiconductor layer at the uppermost layer as the other electrode of the PIN diode.
16. The PIN diode of claim 10, wherein the substrate has an isolation layer thereon or therein, the PIN diode being located on the isolation layer.
17. The PIN diode of claim 10, wherein the concentration of impurity ions in the first intrinsic layer and the second intrinsic layer is less than 1E17/cm3The size of crystal grains in the first intrinsic layer and the second intrinsic layer is smaller than 0.4um, and the thickness of the first intrinsic layer and the second intrinsic layer is 0.001-0.5 mm.
18. An electrostatic protection arrangement having a PIN diode according to any of claims 10 to 17, comprising: the PIN diode power supply comprises a power supply end, a grounding end and an input/output interface end positioned between the power supply end and the grounding end, wherein at least one PIN diode is connected between the power supply end and the input/output interface end in series, and at least one PIN diode is connected between the input/output interface end and the grounding end in series.
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