CN112289353A - Optimized MRAM system with ECC function and operation method thereof - Google Patents
Optimized MRAM system with ECC function and operation method thereof Download PDFInfo
- Publication number
- CN112289353A CN112289353A CN201910678834.0A CN201910678834A CN112289353A CN 112289353 A CN112289353 A CN 112289353A CN 201910678834 A CN201910678834 A CN 201910678834A CN 112289353 A CN112289353 A CN 112289353A
- Authority
- CN
- China
- Prior art keywords
- read
- register
- write
- data
- mram
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 30
- 238000012937 correction Methods 0.000 claims abstract description 6
- 230000006870 function Effects 0.000 description 10
- 230000005415 magnetization Effects 0.000 description 8
- 230000005291 magnetic effect Effects 0.000 description 5
- 230000008569 process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005294 ferromagnetic effect Effects 0.000 description 1
- 239000003302 ferromagnetic material Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000011017 operating method Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1673—Reading or sensing circuits or methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0625—Power saving in storage systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1653—Address circuits or decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1675—Writing or programming circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Quality & Reliability (AREA)
- Static Random-Access Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The present application provides an optimized MRAM system with ECC functionality and method of operating the same, avoiding frequently reading the whole internal word under the condition of using ECC, comprising a register, an error correction circuit and a control circuit, wherein the control circuit comprises a read-write operation module, a data write-back MRAM operation module and an address management module, when a short word is accessed from the outside, the corresponding long word is read into the register in a whole, short word read and write operations are performed on the register area, if the external word address can also match the internal long word address in the following cycle, can continue to read and write on the register area until the external word address of the new period can not be matched, then proceed the register write-back to MRAM, and read the data of the corresponding internal word address into the register, therefore, the power consumption for reading and writing the MRAM can be effectively reduced, and in addition, a complete reading and writing operation can be realized in the same period.
Description
Technical Field
The present application relates to a storage register technology, and more particularly, to an optimized MRAM system with ECC function and an operating method thereof, which belong to the field of computers and computer software.
Background
MRAM is a new memory and storage technology, it has the same fast random read-write characteristics as SRAM/DRAM, and also has the function of Flash memory to permanently retain data after power off. It is well known that DRAM and Flash are not compatible with standard CMOS semiconductor processes, but MRAM can be integrated into one chip by semiconductor processes and logic circuits.
The principle of MRAM is based on a structure called Magnetic Tunnel Junction (MTJ), which consists of two layers of ferromagnetic material, a reference layer with a fixed magnetization direction, and a memory layer with a variable magnetization direction, sandwiched between two very thin non-ferromagnetic insulating layers, the magnetization direction of the memory layer being parallel or anti-parallel to the reference layer. Due to quantum physical effects, current can pass through the middle tunnel barrier layer, but the resistance of the magnetic tunnel junction is related to the magnetization direction of the variable magnetization layer. The memory layer has a low resistance when the magnetization directions of the memory layer and the reference layer are parallel to each other, and a high resistance when the magnetization directions of the memory layer and the reference layer are antiparallel to each other. The process of reading MRAM is to measure the resistance of the magnetic tunnel junction, using the newer STT-MRAM technology, writing MRAM is also simpler, using a stronger current through the magnetic tunnel junction than reading for writing. A bottom-up current sets the variable magnetization layer in an anti-parallel direction with the fixed layer, and a top-down current sets it in a parallel direction.
The read-out circuit of an MRAM needs to detect the resistance of the MRAM memory cell. Since the resistance of the magnetic tunnel junction may drift due to manufacturing process, read and write times, temperature, etc., resulting in data errors, the read data bit is the opposite of the data bit that was last written. To solve this problem, an Error Checking and Correcting circuit (ECC) may be added to encode the data of a word and add some check bits to detect and correct the data Error. The reliability of MRAM needs ECC to support, under the condition of ECC, because ECC is used for coding, extra check bits are needed, and only 1 bit of check bits needs to be added when the original bits are doubled, so that the ECC coding of words with more bits is beneficial to improving the efficiency of storage space. However, this also creates a conflict: if the external word length is not consistent with the internal word length, the whole internal word needs to be read and written in order to read and write a short external word, and frequent ECC encoding and decoding and read and write operations occur, resulting in higher power consumption.
An ECC frame length adjusting method and apparatus thereof are disclosed in patent application No. 201610127678.5 (publication No. CN107168816A), which enable a modified ECC block to be written into a physical page of an NVM by truncating data from padding data of the ECC block, wherein the modified ECC block is composed of a user data unit, a part of the padding data, and check data; the modified ECC block is written to a physical page of the NVM. Meanwhile, the adjusting method further comprises reading the ECC block from a physical page of the NVM; modifying the ECC block by filling predetermined data in a designated portion of the padding data of the ECC block; carrying out ECC decoding on the modified ECC block to obtain information data; the user data unit is derived from the information data. The padding data is generated by using predetermined data, a predetermined random number generation method in which the result is repeatedly generated, and/or a random number seed. Or, a random number generation method and/or a random number seed selected according to the address of the physical page in the padding data is generated by using a predetermined random number generation method and/or a random number seed whose result can be repeatedly generated. By the method, multiple code rates can be supported in a single ECC engine, and the limit of the size of the physical page of the flash memory to the code rate is reduced.
However, the above patent processes ECC data at the page level, which has a large granularity, and in some cases, generates too many padding bits, wasting several times of storage space and power consumption. The applicant finds through research that the processing can be performed at a word level, and the processing mode has the following advantages: small granularity, easy operation and low power consumption.
Disclosure of Invention
In order to solve the current problems, the invention provides a register technology, which mainly solves the technical problem that the whole internal word needs to be read and written when the external word length is not consistent with the internal word length under the condition of using ECC, and avoids frequently reading the whole internal word by performing read-write operation on data capable of being matched with the address of the previous period on a register, the invention provides an optimized MRAM system with an ECC function, which comprises a register, an error correction circuit and a control circuit, wherein the control circuit comprises a read-write operation module, a data write-back MRAM operation module and an address management module, the address management module stores an address and acquires the external word address, judges whether the external word address is matched with the internal word address, and triggers the data write-back MRAM operation when the external word address is not matched with the internal word address in the register, the address management module acquires an external word address as a new address after data is written back to the MRAM, and the read-write operation module triggers the read-write operation on the register when the external word address is matched with the internal word address.
Furthermore, the register includes a first register set, a second register set, a third register set, a fourth register set, a read-write flag register set, and a write-back flag register set, where the first register set is used to store data interacted with the outside during reading and writing, the second register set is used to store data read from the MRAM, the third register set is used to store internal word addresses, and the fourth register set is used to store external word addresses.
Further, the length of the read/write flag register set is 1, the read/write flag register set is set to 1 or 0 during write operation, the read/write flag register set is correspondingly set to 0 or 1 during read operation, the length of the write-back flag register set is 1, the read/write flag register set is set to 1 or 0 when data needs to be written back to the MRAM, and the read/write flag register set is correspondingly set to 0 or 1 when data does not need to be written back to the MRAM.
Further, according to the actual circuit, the read-write flag register set selects to set the value to 0 or 1 as required, the default value of the read-write flag register set is 0, and the value becomes 1 as long as there is a write operation.
The application also provides an optimized operation method of the MRAM system with the ECC function, the system comprises a register, the register stores internal data and addresses of the internal data, the register performs read-write operation of the register and data write-back MRAM operation through a control circuit and manages data addresses, and the method comprises the following steps:
step 1) reading input signals, wherein the input signals comprise external read-write signals and external word addresses are obtained;
step 2) comparing the external word address with the internal word address in the register, and performing internal data read-write operation on the register when m bits before the external word address are the same as or correspond to m bits before the internal word address;
and 3) when m bits before the external word address are different from m bits before the internal word address, and the internal data on the register needs to be written back to the MRAM, writing the internal data on the register back to the MRAM, updating the internal word address in the register, acquiring corresponding data of the new internal word address according to the new internal word address, and performing read-write operation on the register.
Further, in step 3), when m bits before the external word address are different from m bits before the internal word address, data of the new address is read in through another register, and after the data of the new address is read in through the new memory, the data of the old address stored in the original register is stored in the MRAM.
Further, the offset value (offset) is considered when reading and writing the internal data in the register.
Further, the register includes a read-write flag register set and a write-back flag register set, the length of the read-write flag register set is 1, the read-write flag register set is set to 1 or 0 during write operation, the read-write flag register set is correspondingly set to 0 or 1 during read operation, the length of the write-back flag register set is 1, when data needs to be written back to the MRAM, the read-write flag register set is set to 1 or 0, and when data does not need to be written back to the MRAM, the read-write flag register set is correspondingly set to 0 or 1.
Furthermore, the register further comprises a first register set, a second register set, a third register set and a fourth register set, data which interact with the outside during reading and writing are stored in the first register set, data read from the MRAM are stored in the second register set, reading and writing operations are performed on the register sets through the second register set, internal word addresses are stored in the third register set, and external word addresses are stored in the fourth register set.
Further, updating the internal word address in the register includes writing an address m bits before the external word address into the internal word address, reading the corresponding data in the MRAM, and placing the read data in the internal data.
Further, in step 2), it is determined whether the internal data is updated, and the internal data in the register is written back to the MRAM if the internal data is updated.
For Memory read-write, the probability of sequential read-write is higher, when the system and the method are used, when an external access short word, the corresponding long word is read into the register integrally, the read-write operation of the short word is carried out on the register area, if the external word address of the later period can also be matched with the internal long word address, the read-write operation can be continuously carried out on the register area until the external word address of the new period can not be matched, then the register is written back to the MRAM, and the data of the new address is read into the register, so that the power consumption required by the read-write MRAM is effectively reduced, and in addition, a complete read-write operation can be realized in the same period.
Drawings
FIG. 1 is a schematic diagram of an optimized ECC-enabled MRAM system of the present application;
FIG. 2 is a flow chart of a method of operation of an optimized ECC-enabled MRAM system;
FIG. 3 is a flow chart of a method of operation of another embodiment of an optimized ECC-enabled MRAM system.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
In the following description, specific details are set forth describing some embodiments of the disclosure. It will be apparent, however, to one skilled in the art, that some embodiments may be practiced without some or all of these specific details. The specific embodiments disclosed herein are intended to be illustrative rather than restrictive. Although not specifically described herein, those skilled in the art will recognize that other elements are within the scope and spirit of the disclosure.
The invention will be described in further detail with reference to the following drawings and specific embodiments.
Referring to fig. 1, fig. 1 is a schematic diagram of an optimized MRAM system with ECC function according to the present application, which provides an optimized MRAM system with ECC function, the device comprises a register error correction circuit 2(ECC) and a control circuit 1, wherein the control circuit 1 comprises a read-write operation module 11, a data write-back MRAM operation module 12 and an address management module 13, the address management module 13 stores an address and acquires an external word address, judges whether the external word address is matched with an internal word address, the data write-back MRAM operation module 12 triggers data write-back MRAM operation when the external word address is not matched with the internal word address in a register, the address management module 13 acquires the external word address and converts the external word address into a new address after the data write-back MRAM operation, and reads corresponding MRAM data, and the read-write operation module 11 triggers a read-write operation on the register 10 when the external word address matches the internal word address.
Further, the register 10 includes a first register group for storing data that interacts with the outside at the time of reading and writing, a second register group for storing data read from the MRAM3 and performing reading and writing operations on this register group, a second register group for storing an internal word address, a third register group for storing an external word address, a fourth register group for storing an read-write flag register group, and a write-back flag register group (not shown in the drawings).
Further, the length of the read/write flag register set is 1, the read/write flag register set is set to 1 or 0 during write operation, the read/write flag register set is correspondingly set to 0 or 1 during read operation, the length of the write-back flag register set is 1, the read/write flag register set is set to 1 or 0 when data needs to be written back to the MRAM, and the read/write flag register set is correspondingly set to 0 or 1 when data does not need to be written back to the MRAM. And according to the actual circuit, the read-write mark register group selects to set the value to 0 or 1 according to the requirement, the default value of the read-write mark register group is 0, and the value is 1 as long as the write operation is available.
Referring to fig. 2, fig. 2 is a flow chart of an operation method of an optimized MRAM system with an ECC function, and the present application also provides an operation method of an optimized MRAM system with an ECC function, where the system includes a register and an error correction circuit 2(ECC), a register 10 stores internal data and addresses of the internal data, and performs a register read-write operation, a data write-back MRAM operation and manages data addresses through a control circuit, and the method includes the following steps: step 1) reading input signals, wherein the input signals comprise external read-write signals and external word addresses are obtained;
step 2) comparing the external word address with the internal word address in the register, and performing internal data read-write operation on the register when m bits before the external word address are the same as or correspond to m bits before the internal word address;
and 3) when m bits before the external word address are different from m bits before the internal word address, and the internal data on the register needs to be written back to the MRAM3, writing the internal data on the register back to the MRAM3, updating the internal word address in the register 10 after the data on the register 10 is written back to the MRAM3, acquiring corresponding data of a new internal word address according to the new internal word address, and performing read-write operation on the register 10.
Further, referring to fig. 3, fig. 3 is a flow chart of an operation method of another embodiment of the optimized MRAM system with ECC function, in the operation flow of fig. 3, step 3) selects that m bits before the external word address are different from m bits before the internal word address, data of a new address is read in through another set of registers, and after the new memory reads in the data of the new address, data of an old address stored in an original set of registers is stored in the MRAM.
Further, the offset value (offset) is considered when reading and writing the internal data in the register 10.
Further, the register 10 includes a read-write flag register set and a write-back flag register set, where the length of the read-write flag register set is 1, the read-write flag register set is 1 or 0 during write operation, the read-write flag register set is correspondingly set to 0 or 1 during read operation, the length of the write-back flag register set is 1, when data needs to be written back to the MRAM3, the read-write flag register set is set to 1 or 0, and when data does not need to be written back to the MRAM3, the read-write flag register set is correspondingly set to 0 or 1.
Further, the register 10 further includes a first register set, a second register set, a third register set, and a fourth register set, where data interacting with the outside during reading and writing is stored in the first register set, data read from the MRAM3 is stored in the second register set, and reading and writing operations are performed on this register set through the second register set, an internal word address is stored in the third register set, and an external word address is stored in the fourth register set.
Further, updating the internal word address in register 10 involves writing the m-bit address before the external word address to the internal word address, reading the corresponding data in MRAM3 and placing it in the internal data.
Further, step 2) includes determining whether the internal data is updated, and writing the internal data in the register back to the MRAM3 only if the internal data is updated.
DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION
Taking the internal word length a as 64 bits, the external word length b as 32 bits, the address bit length m as 10, the address bit length n of the available signal as 12, and the address bit length k of the actual signal as 11 as examples:
at programming time, for the signal: the outerData is set to the available external data bit, which is 64 the same length as the internal data bit length a.
outerAddr is the address bit of the available signal, with a length n-12.
The accutaladdrflag is an address/data length mark of an actual signal, and one method is as follows: the bit length is log2(n-m +1), rounded up, and is used to determine the address length/data bit length of the actual signal, as above, n-m is 2, the internal word address bits are 2 bits less than the address of the available signal, the needed accutaladdrflag is 1og2(3) is 2, and there are three cases: 01, a, m; 10, a/2, m + 1; 11, a/4, m + 2.
Considering the offset, even if the pin of the external data bit pin has a-64 bits D [0] -D [63], if the actual external word length is only 16 bits, data is input only from D [0] -D [15] regardless of the address, and the relationship between the data bit offset and the actual external data bit length and the address bit length of the actual signal is shown in the following table:
| acutalAddrFlag | data bit length of actual signal | Address bit length of real signal | Data bit offset indication |
| 00 | - | - | - |
| 01 | a | Front m position | Is free of |
| 10 | a/2 | Front m +1 bit | Last 1 bit of real address bit |
| 11 | a/4 | m +2 position | Last 2 bits of the real address bits |
The situation in the above table is one choice, and 00/01/10/11 corresponds to what kind of situation specifically, can freely select according to actual needs, and the person skilled in the art knows its specific arrangement mode, therefore does not carry out the specific description of the arrangement mode of other situations in the description.
The register comprises a first register group, a second register group, a third register group, a fourth register group, a read-write mark register group and a write-back mark register group, and for the setting, outerData is used as the register group with the length of a and used for storing data interacted with the outside during reading and writing; using innerData as a register group with the length of a for storing data read from the MRAM and performing read-write operation on the register group; taking innerAddr as a register group with the length of m as an internal word address; using outerAddr as a register group with the length of m +2 as an available external word address; reading or writing as a register external read/write signal (read 0, write 1); setting W/B to be a register with the length of 1 for recording whether an over-write operation exists on the current innerAddr or not, setting 1 as long as the over-write operation is performed on the current innerAddr, and writing the innerData back to the MRAM when the innerAddr is switched.
The register technology provided by the invention avoids frequently reading the whole internal word under the condition of using ECC, and comprises a register, an error correction circuit 2(ECC) and a control circuit 1, wherein the control circuit 1 comprises a read-write operation module 11, a data write-back MRAM operation module 12 and an address management module 13, when a short word is accessed from the outside, the corresponding long word is integrally read into the register, the read-write operation of the short word is carried out on a register area, if the external word address of the later period can also be matched with the internal long word address, the read-write operation can be continuously carried out on the register area until the external word address of the new period can not be matched, then the register is written back into the MRAM, and the data of the corresponding internal word address is read into the register, thereby effectively reducing the power consumption required by the read-write MRAM, and in addition, a complete read-write operation can be realized in the same period, in practical use, the invention can effectively reduce the frequency of reading and writing MRAM and ECC coding and decoding, and effectively reduce power consumption.
The relationships depicted in the drawings are for illustrative purposes only and are not to be construed as limiting the present patent, it being understood that the above examples of the present application are merely illustrative for clearly illustrating the present application and are not limitative of the embodiments of the present application. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present application shall be included in the protection scope of the claims of the present application.
Claims (10)
1. An optimized MRAM system with an ECC function comprises a register, an error correction circuit and a control circuit, and is characterized in that the control circuit comprises a read-write operation module, a data write-back MRAM operation module and an address management module, wherein the address management module stores an address and acquires an external word address, judges whether the external word address is matched with an internal word address, triggers the data write-back MRAM operation when the external word address is not matched with the internal word address in the register, acquires the external word address as a new address after the data write-back MRAM operation, and triggers the read-write operation on the register when the external word address is matched with the internal word address.
2. The optimized MRAM system with ECC function of claim 1, wherein the register comprises a first register set, a second register set, a third register set, a fourth register set, a read-write flag register set and a write-back flag register set, the first register set is used for storing data interacted with the outside during reading and writing, the second register set is used for storing data read from the MRAM, the third register set is used for storing an internal word address, and the fourth register set is used for storing an input external word address.
3. The optimized MRAM system with ECC function of claim 2, wherein the length of the read/write flag register set is 1, the read/write flag register set is 1 or 0 during write operation, the read/write flag register set is correspondingly set to 0 or 1 during read operation, the length of the write-back flag register set is 1, the read/write flag register set is set to 1 or 0 when data needs to be written back into MRAM, and the read/write flag register set is correspondingly set to 0 or 1 when data does not need to be written back into MRAM.
4. The optimized MRAM system with ECC function of claim 3, wherein, according to the actual circuit, the read/write flag register set selects to set the value to 0 or 1 according to the requirement, the default value of the read/write flag register set is 0, and becomes 1 as long as there is a write operation.
5. An optimized operation method of an MRAM system with ECC function, the system comprises a register, the register stores internal data and addresses of the internal data, and the register performs read-write operation of the register, data write-back operation of the MRAM and manages data addresses through a control circuit, the method is characterized by comprising the following steps:
step 1) reading input signals, wherein the input signals comprise external read-write signals and external word addresses are obtained;
step 2) comparing the external word address with the internal word address in the register, and performing internal data read-write operation on the register when m bits before the external word address are the same as or correspond to m bits before the internal word address;
and 3) when m bits before the external word address are different from m bits before the internal word address, and the internal data on the register needs to be written back to the MRAM, writing the internal data on the register back to the MRAM, updating the internal word address in the register, acquiring corresponding data of the new internal word address according to the new internal word address, and performing read-write operation on the register.
6. The method according to claim 5, wherein in step 3), when m bits before the external word address are different from m bits before the internal word address, the data of the new address is read in through another set of registers, and after the data of the new address is read in the new memory, the data of the old address stored in the original set of registers is stored in the MRAM.
7. The method according to claim 5, wherein the register includes a read/write flag register set and a write-back flag register set, the length of the read/write flag register set is 1, the read/write flag register set is set to 1 or 0 during write operation, the read/write flag register set is correspondingly set to 0 or 1 during read operation, the length of the write-back flag register set is 1, the read/write flag register set is set to 1 or 0 when data needs to be written back to the MRAM, and the read/write flag register set is correspondingly set to 0 or 1 when data does not need to be written back to the MRAM.
8. The method of claim 7, wherein the register further comprises a first register set, a second register set, a third register set, and a fourth register set, wherein data that interacts with the outside during reading and writing is stored in the first register set, data read from the MRAM is stored in the second register set, and reading and writing operations are performed on the register set through the second register set, and wherein an internal word address is stored in the third register set and an external word address is stored in the fourth register set.
9. The method of claim 8, wherein updating the internal word address in the register comprises writing an m-bit address before the external word address to the internal word address, and reading the corresponding data in the MRAM into the internal data.
10. The method of claim 5, further comprising determining whether the internal data is updated, and writing the internal data in the register back to the MRAM if the internal data is updated in step 2).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910678834.0A CN112289353B (en) | 2019-07-25 | 2019-07-25 | Optimized MRAM system with ECC function and operation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910678834.0A CN112289353B (en) | 2019-07-25 | 2019-07-25 | Optimized MRAM system with ECC function and operation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112289353A true CN112289353A (en) | 2021-01-29 |
| CN112289353B CN112289353B (en) | 2024-03-12 |
Family
ID=74419625
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910678834.0A Active CN112289353B (en) | 2019-07-25 | 2019-07-25 | Optimized MRAM system with ECC function and operation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112289353B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114726382A (en) * | 2022-05-16 | 2022-07-08 | 北京得瑞领新科技有限公司 | ECC frame length matching method and device, storage medium and solid state disk |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060282755A1 (en) * | 2005-05-31 | 2006-12-14 | Jong-Hoon Oh | Random access memory having ECC |
| US20070234182A1 (en) * | 2006-03-31 | 2007-10-04 | Wickeraad John A | Error checking and correction (ECC) system and method |
| CN101689141A (en) * | 2007-06-20 | 2010-03-31 | 富士通株式会社 | Cache memory device, arithmetic processing unit, and its control method |
| CN102339641A (en) * | 2010-07-23 | 2012-02-01 | 北京兆易创新科技有限公司 | Error checking and correcting verification module and data reading-writing method thereof |
| US20130124932A1 (en) * | 2011-11-14 | 2013-05-16 | Lsi Corporation | Solid-State Disk Manufacturing Self Test |
| US8634247B1 (en) * | 2012-11-09 | 2014-01-21 | Sandisk Technologies Inc. | NAND flash based content addressable memory |
| US20140149827A1 (en) * | 2012-11-27 | 2014-05-29 | Samsung Electronics Co., Ltd. | Semiconductor memory device including non-volatile memory, cache memory, and computer system |
| CN104412327A (en) * | 2013-01-02 | 2015-03-11 | 默思股份有限公司 | Built in self-testing and repair device and method |
| WO2015169245A1 (en) * | 2014-05-09 | 2015-11-12 | 华为技术有限公司 | Data caching method, cache and computer system |
| CN105702277A (en) * | 2010-12-17 | 2016-06-22 | 艾沃思宾技术公司 | Memory controller and method for interleaving DRAM and MRAM accesses |
| CN107423230A (en) * | 2016-05-20 | 2017-12-01 | 三星电子株式会社 | Memory module, there is its computing system and the method for testing its tag error |
| US20180090226A1 (en) * | 2016-09-27 | 2018-03-29 | Spin Transfer Technologies, Inc. | Device with dynamic redundancy registers |
| US20180253304A1 (en) * | 2017-03-03 | 2018-09-06 | International Business Machines Corporation | Dynamically selecting version of instruction to be executed |
-
2019
- 2019-07-25 CN CN201910678834.0A patent/CN112289353B/en active Active
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060282755A1 (en) * | 2005-05-31 | 2006-12-14 | Jong-Hoon Oh | Random access memory having ECC |
| US20070234182A1 (en) * | 2006-03-31 | 2007-10-04 | Wickeraad John A | Error checking and correction (ECC) system and method |
| CN101689141A (en) * | 2007-06-20 | 2010-03-31 | 富士通株式会社 | Cache memory device, arithmetic processing unit, and its control method |
| CN102339641A (en) * | 2010-07-23 | 2012-02-01 | 北京兆易创新科技有限公司 | Error checking and correcting verification module and data reading-writing method thereof |
| CN105702277A (en) * | 2010-12-17 | 2016-06-22 | 艾沃思宾技术公司 | Memory controller and method for interleaving DRAM and MRAM accesses |
| US20130124932A1 (en) * | 2011-11-14 | 2013-05-16 | Lsi Corporation | Solid-State Disk Manufacturing Self Test |
| US8634247B1 (en) * | 2012-11-09 | 2014-01-21 | Sandisk Technologies Inc. | NAND flash based content addressable memory |
| US20140149827A1 (en) * | 2012-11-27 | 2014-05-29 | Samsung Electronics Co., Ltd. | Semiconductor memory device including non-volatile memory, cache memory, and computer system |
| CN104412327A (en) * | 2013-01-02 | 2015-03-11 | 默思股份有限公司 | Built in self-testing and repair device and method |
| WO2015169245A1 (en) * | 2014-05-09 | 2015-11-12 | 华为技术有限公司 | Data caching method, cache and computer system |
| CN107423230A (en) * | 2016-05-20 | 2017-12-01 | 三星电子株式会社 | Memory module, there is its computing system and the method for testing its tag error |
| US20180090226A1 (en) * | 2016-09-27 | 2018-03-29 | Spin Transfer Technologies, Inc. | Device with dynamic redundancy registers |
| US20180253304A1 (en) * | 2017-03-03 | 2018-09-06 | International Business Machines Corporation | Dynamically selecting version of instruction to be executed |
Non-Patent Citations (2)
| Title |
|---|
| XIAOCHEN GUO .ETC: "Sanitizer：Mitigating the impact of expensive ECC checks on STT-MRAM based main memories", 《IEEE TRANSACTIONS ON COMPUTERS》, vol. 67, no. 6, pages 847 - 860 * |
| 何炎详等: "新型非易失性存储器架构的缓存优化方法综述", 《计算机研究与发展》, pages 1225 - 1241 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114726382A (en) * | 2022-05-16 | 2022-07-08 | 北京得瑞领新科技有限公司 | ECC frame length matching method and device, storage medium and solid state disk |
| CN114726382B (en) * | 2022-05-16 | 2022-08-09 | 北京得瑞领新科技有限公司 | ECC frame length matching method and device, storage medium and solid state disk |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112289353B (en) | 2024-03-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10198221B2 (en) | Methods of operating semiconductor memory devices with selective write-back of data for error scrubbing and related devices | |
| CN107393596B (en) | Semiconductor memory device and method of operating the same | |
| US10115446B1 (en) | Spin transfer torque MRAM device with error buffer | |
| US8589766B2 (en) | Codeword remapping schemes for non-volatile memories | |
| KR102002925B1 (en) | Memory module, memory system havint the same, and driving method thereof | |
| US10331345B2 (en) | Method and apparatus for reducing silent data errors in non-volatile memory systems | |
| US8839053B2 (en) | Error correcting pointers for non-volatile storage | |
| CN108122587A (en) | The erasure controller and semiconductor memory system of semiconductor memory system | |
| US20030023927A1 (en) | Method for error correction decoding in a magnetoresistive solid-state storage device | |
| CN106297895A (en) | Error correction circuit, semiconductor memory system and control method thereof | |
| US7152138B2 (en) | System on a chip having a non-volatile imperfect memory | |
| KR20140067819A (en) | Semiconductor memory device including non-volatile memory and cache memory and computer systam having the same | |
| Dan et al. | Implementing MLC NAND flash for cost-effective, high-capacity memory | |
| CN110660421B (en) | Magnetic random access memory with error correction and compression circuit | |
| US10552257B2 (en) | Adaptive error correction in memory devices | |
| Hong et al. | Ternary cache: Three-valued MLC STT-RAM caches | |
| US20210082483A1 (en) | Memory system | |
| US6853602B2 (en) | Hiding error detecting/correcting latency in dynamic random access memory (DRAM) | |
| US10204700B1 (en) | Memory systems and methods of operating semiconductor memory devices | |
| Micheloni et al. | Non-volatile memories for removable media | |
| CN112289353B (en) | Optimized MRAM system with ECC function and operation method thereof | |
| US7904786B2 (en) | Assisted memory system | |
| US7266732B2 (en) | MRAM with controller | |
| CN110660422A (en) | Cache system used in cooperation with error correction magnetic random access memory | |
| CN110931063A (en) | Semiconductor memory device with a plurality of memory cells |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |