CN112272812A - Power management device, electronic equipment and movable platform assembly - Google Patents

Abstract

A power management device, an electronic device and a movable platform assembly are provided, wherein the power management device can be applied to the electronic device, the electronic device comprises a system power supply and a processor, the power management device comprises a power-on control circuit and a power management chip, the power-on control circuit is connected with the system power supply and the power management chip, the power management chip is connected with the processor, the power-on control circuit can automatically generate a power-on control signal after the system power supply of the electronic device supplies power, and input the power-on control signal into the power management chip to trigger the power management chip to power on the processor, and can automatically generate the power-on control signal after the system power supply supplies power to complete the power-on of the processor system, so that the problem of normal power-on of the processor system in a scene of starting without keys is effectively solved.

Description

Power management device, electronic equipment and movable platform assembly

Technical Field

The present application relates to the field of electronic technologies, and in particular, to a power management device, an electronic apparatus, and a movable platform assembly.

Background

A Processor (e.g., an Application Processor (AP)) of an electronic device generally has a Power Management chip (PMIC) that provides Power and Power-on timing for operating the Processor system. As shown in fig. 1, an external trigger signal is required for powering on and booting an electronic device product, the external trigger signal is generally connected to a dedicated pin (e.g., a power-on trigger ONKEY pin) of the PMIC, and after the PMIC detects the external trigger signal, the PMIC turns on internal power-on logic to complete turning on of each power supply (power supply 1, power supply 2, power supply 3, … …, and power supply n) of the processor system. As shown in fig. 1, most of the current external trigger signals are implemented by pressing a key, however, in some application scenarios, the key is not applicable due to product requirements, and the key cannot be used for booting.

Disclosure of Invention

The embodiment of the application discloses a power management device, electronic equipment and a movable platform assembly, which can automatically generate a power-on control signal after a system power supply supplies power to complete the power-on of a processor system, thereby effectively solving the problem of normal power-on of the processor system in a scene of starting without using a key.

In a first aspect, an embodiment of the present application provides a power management apparatus, which is applied to an electronic device, where the electronic device includes a system power supply and a processor, the power management apparatus includes a power-on control circuit and a power management chip, where:

the power-on control circuit is connected with the system power supply and the power management chip, and the power management chip is connected with the processor;

the power-on control circuit is used for generating a power-on control signal after the system power supply supplies power, inputting the power-on control signal into the power management chip, and triggering the power management chip to power on the processor.

In a second aspect, an embodiment of the present application further provides an electronic device, including: a system power supply; a processor; and the power management apparatus of the first aspect, wherein the power management apparatus is configured to power up the processor after the system power supply supplies power.

In a third aspect, an embodiment of the present application further provides a movable platform assembly, including: a movable platform; the remote control terminal is used for controlling the movable platform;

wherein, the remote control terminal includes: a system power supply; a processor; and the power management apparatus of the first aspect, wherein the power management apparatus is configured to power up the processor after the system power supply supplies power.

The power management device provided by the embodiment of the application can be applied to electronic equipment, the electronic equipment comprises a system power supply and a processor, and the power management device comprises a power-on control circuit and a power management chip, wherein the power-on control circuit is connected with the system power supply and the power management chip, the power management chip is connected with the processor, and the power-on control circuit is used for generating a power-on control signal after the system power supply supplies power, inputting the power-on control signal into the power management chip to trigger the power management chip to power on the processor, and automatically generating the power-on control signal to complete the power-on of the processor system after the system power supply supplies power, so that the problem of normal power-on of the processor system in a scene of starting without using keys is effectively solved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without inventive labor.

FIG. 1 is a schematic circuit diagram of a power management scheme provided in the prior art;

fig. 2 is a schematic circuit diagram of a power management device according to an embodiment of the present disclosure;

fig. 3 is a schematic circuit structure diagram of a power-on control circuit according to an embodiment of the present disclosure;

fig. 4 is a schematic circuit structure diagram of another power-on control circuit provided in an embodiment of the present application;

FIG. 5 is a schematic circuit diagram of another power-on control circuit according to an embodiment of the present disclosure;

fig. 6 is a schematic circuit diagram of another power management device according to an embodiment of the present disclosure;

fig. 7 is a schematic diagram illustrating a variation of a terminal voltage of a capacitor in a power-on control circuit according to an embodiment of the present disclosure;

FIG. 8 is a timing diagram of a power management chip according to an embodiment of the present disclosure;

fig. 9 is a schematic waveform diagram of a power-on control signal generated by a power-on control circuit according to an embodiment of the present disclosure;

fig. 10 is a schematic circuit diagram of another power management device according to an embodiment of the present application;

fig. 11 is a schematic circuit structure diagram of an electronic device according to an embodiment of the present application;

fig. 12 is a schematic circuit diagram of a movable platform assembly according to an embodiment of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

The electronic device in the embodiment of the application can be a remote control terminal used for controlling movable platforms such as an unmanned aerial vehicle. The remote control terminal may be a remote controller, for example, one of the function modules of the remote controller includes a core board, an application processor AP in the mobile field such as a mobile phone is used on the core board, and the application processor corresponds to a power management chip PMIC matched with the application processor AP. When a key on the remote controller triggers the startup, after each functional module is powered on, the application processor can be powered on by another key of the remote controller. However, in such a usage scenario, it is obviously impossible for the user to accurately judge that the power-on of each functional module is completed, and then manually trigger through the key to generate the power-on trigger signal required by the application processor in time. Therefore, it is not suitable to power on the application processor by pressing the key, and it is urgently needed to provide a circuit design scheme capable of automatically generating a power-on trigger signal.

Fig. 2 is a schematic circuit structure diagram of a power management device according to an embodiment of the present disclosure. The power management apparatus 100 is applied to an electronic device, the electronic device includes a system power supply 200 and a processor 300, the power management apparatus 100 includes a power-on control circuit 1010 and a power management chip 1020, wherein:

the power-on control circuit 1010 is connected with the system power supply 200 and the power management chip 1020, and the power management chip 1020 is connected with the processor 300;

the power-on control circuit 1010 is configured to generate a power-on control signal after the system power supply 200 supplies power, and input the power-on control signal to the power management chip 1020, where the power-on control signal is used to trigger the power management chip 1020 to power on the processor 300.

Wherein the power-on control signal comprises a pulse signal from a low level to a high level.

Optionally, according to different types of the power management chip 1020 and requirements for the power-on control signal, the power-on control signal may also include a pulse signal from a high level to a low level, which is not limited in this embodiment of the present application.

Therefore, the power management device provided by the embodiment of the application comprises the power-on control circuit and the power management chip, wherein the power-on control circuit can automatically generate a power-on control signal after a system power supply of the electronic equipment supplies power, the power-on control signal is input into the power management chip, the power management chip powers on the processor after the power-on control signal meets the trigger condition, the power-on control signal can be automatically generated after the system power supply supplies power to complete the power-on of the processor system, and the problem of normal power-on of the processor system in the scene of starting the electronic equipment without using keys is effectively solved.

Optionally, the power-on control circuit 1010 may be specifically implemented by two resistor-capacitor RC charging and discharging circuits. Wherein, the corresponding time constants between each RC circuit in the two RC circuits are different so as to generate the power-on control signal. Specifically, each RC circuit is connected to the system power supply 200, and after the system power supply 200 supplies power, in the charging process of each RC circuit, due to different time constants, the voltage variation modes and/or voltage variation time sequences of the two RC circuits are different, so that the power-on control signal can be generated. It is understood that the power-on control circuit 1010 may also include other components or circuits, which are not specifically limited herein.

Optionally, as shown in fig. 3, the two RC circuits may specifically include a first RC circuit 1011 and a second RC circuit 1013, and the power-on control circuit 1010 further includes a switch element 1012. The switch element 1012 is connected between the first RC circuit 1011 and the second RC circuit 1013, both the first RC circuit 1011 and the second RC circuit 1013 are connected to the system power supply 200 (not shown in the figure), the second RC circuit 1013 is connected to the power management chip 1020 (not shown in the figure), and the first RC circuit 1011 and the second RC circuit 1013 can generate the power-on control signal during the charging process after the system power supply 200 is powered by the switch element 1012.

Optionally, the specific connection manner of the switching element 1012 and the first RC circuit 1011 and the second RC circuit 1013 may be: a first terminal of the switching element 1012 is connected between the resistor and the capacitor of the first RC circuit 1011, a second terminal of the switching element 1012 is connected between the resistor and the capacitor of the second RC circuit 1013, and a third terminal of the switching element 1012 is grounded.

Optionally, the switching element 1012 includes a transistor or a Metal Oxide Semiconductor (MOS) transistor.

Optionally, an output end of the second RC circuit 1013 is connected to a power-on control pin (for example, a power-on trigger ONKEY pin) of the power management chip 1020, an output end of the second RC circuit 1013 is located between a resistor and a capacitor of the second RC circuit 1013, and an output end of the second RC circuit 1013 is used for generating a power-on control signal in a charging process of the first RC circuit 1011 and the second RC circuit 1013 after the system power supply 200 supplies power, and inputting the power-on control signal to the power management chip 1020 through the power-on control pin.

Optionally, as shown in fig. 4, the power-on control circuit 1010 further includes a discharge loop 1014. The discharging circuit 1014 is connected in parallel with the first RC circuit 1011, and the discharging circuit 1014 is configured to discharge the first RC circuit 1011 after the system power supply 200 is powered off, so as to ensure that the first RC circuit 1011 and the second RC circuit 1013 can generate the power-on control signal again in the charging process through cooperation of the switching element 1012 after the system power supply 200 is powered off next time, thereby ensuring circuit reliability.

Optionally, the discharge loop 1014 includes a diode and a resistor, and the diode and the resistor included in the discharge loop 1014 are connected in parallel with the resistor of the first RC circuit 1011.

Optionally, the time constant of the first RC circuit 1011 is greater than the time constant of the second RC circuit 1013, which means that the terminal voltage of the capacitor of the second RC circuit 1013 reaches the voltage of the system power supply 200 before the terminal voltage of the capacitor of the first RC circuit 1011, so as to generate the power-on control signal meeting the requirement.

Optionally, the first time length corresponding to the first RC circuit 1011 minus the second time length corresponding to the second RC circuit 1013 is greater than or equal to the preset time length. The first time period is a time period required for the terminal voltage of the capacitor of the first RC circuit 1011 to reach the on voltage of the switching element 1012 from the start of power supply of the system power supply 200, and the second time period is a time period required for the terminal voltage of the capacitor of the second RC circuit 1013 to reach the voltage of the system power supply 200 from the start of power supply of the system power supply 200.

Optionally, the preset time duration is a shortest time duration required by the processor 300 from the power-on start to the power-on success, so as to ensure that the generated power-on control signal can meet a requirement of completing the power-on of the processor 300.

Optionally, as shown in fig. 5, the two RC circuits may specifically include a third RC circuit 1015 and a fourth RC circuit 1016, and the power-on control circuit 1010 further includes a logic gate circuit 1017. The input end of the logic gate circuit 1017 is connected to the third RC circuit 1015 and the fourth RC circuit 1016, the third RC circuit 1015, the fourth RC circuit 1016 and the logic gate circuit 1017 are all connected to the system power supply 200 (not shown in the figure), and the output end of the logic gate circuit 1017 is connected to the power management chip 1020 (not shown in the figure). After the system power supply 200 is powered, the output terminal of the logic gate circuit 1017 may generate the power-up control signal during the charging process of the third RC circuit 1015 and the fourth RC circuit 1016.

Optionally, the specific connection manner of the logic gate circuit 1017 with the third RC circuit 1015 and the fourth RC circuit 1016 may be: one input terminal of the logic gate circuit 1017 is connected between the resistor and the capacitor of the third RC circuit 1015, the other input terminal of the logic gate circuit 1017 is connected between the resistor and the capacitor of the fourth RC circuit 1016, the resistor of the third RC circuit 1015 is connected to the system power supply 200, and the capacitor of the fourth RC circuit 1016 is connected to the system power supply 200.

Optionally, the logic gate circuit 1017 comprises an and circuit.

Optionally, an output end of the logic gate circuit 1017 is connected to a power-on control pin of the power management chip 1020, and an output end of the logic gate circuit 1017 is configured to generate the power-on control signal, and input the power-on control signal to the power management chip 1020 through the power-on control pin.

Optionally, the power-on control circuit 1010 further includes a discharging loop. The discharging circuit is connected in parallel with the third RC circuit 1015, and the discharging circuit is used for discharging the third RC circuit 1015 after the system power supply 200 is powered off, so as to ensure that the third RC circuit 1015 and the fourth RC circuit 1016 can generate the power-on control signal again in the charging process through the cooperation of the logic gate circuit 1017 after the system power supply 200 is powered off next time, and ensure the reliability of the circuit.

Optionally, the discharge loop comprises a diode. A diode is connected in parallel with the resistance of the third RC circuit 1015.

Optionally, the time constant of the third RC circuit 1015 is smaller than the time constant of the fourth RC circuit 1016, meaning that the voltage drop between the resistor and the capacitor of the fourth RC circuit 1016 takes longer to reach a low level than the voltage across the capacitor of the third RC circuit 1015 reaches the voltage of the system power supply, thereby generating a satisfactory power-on control signal.

Optionally, the fourth time duration corresponding to the fourth RC circuit 1016 minus the third time duration corresponding to the third RC circuit 1015 is greater than or equal to the preset time duration. Wherein the third time period is a time period required for the terminal voltage of the capacitor of the third RC circuit 1015 to reach the voltage of the system power supply 200 from the power supply of the system power supply 200, and the fourth time period is a time period required for the voltage between the resistor and the capacitor of the fourth RC circuit 1016 to be lowered to a low level from the voltage of the system power supply 200 from the power supply of the system power supply 200.

Optionally, the preset time duration is a shortest time duration required by the processor 300 from the power-on start to the power-on success, so as to ensure that the generated power-on control signal can meet a requirement of completing the power-on of the processor 300.

Optionally, as shown in fig. 6, the schematic diagram is a circuit structure of another power management device provided in the embodiment of the present application, where:

the resistor R1, the capacitor C1, the MOS transistor Q1, the resistor R2, the capacitor C2, the diode D1, and the resistor R3 form the power-on control circuit 1010 of the power management device.

Specifically, the resistor R1 and the capacitor C1 form a first RC circuit 1011 of the power-on control circuit 1010, the MOS transistor Q1 serves as a switching element 1012 of the power-on control circuit 1010, the resistor R2 and the capacitor C2 form a second RC circuit 1013 of the power-on control circuit 1010, the diode D1 and the resistor R3 form a discharge circuit 1014 of the power-on control circuit 1010, and the N-channel MOS transistor is taken as an example of the Q1 in the figure.

One end of each of the first RC circuit 1011 and the second RC circuit 1013 is connected to a system power supply VSYS, the other end of each of the first RC circuit 1011 and the second RC circuit 1013 is connected to ground, a point B of an output end of the second RC circuit 1013 (located between R2 and C2) is connected to an upper electric control pin (i.e., an upper trigger ONKEY pin) of the power management chip PMIC, a Gate (Gate, G) of Q1 as a switching element 1012 is connected to a point a between R1 and C1 of the first RC circuit 1011, a Drain (Drain, D) of the switching element 1012 is connected to a point B of an output end of the second RC circuit 1013, a Source (Source, S) of the switching element 1012 is connected to ground, a D1 of the discharge circuit 1014 is connected in parallel with R1 of the first RC circuit 1011, one end of R3 of the discharge circuit 1014 is connected to the system power supply VSYS, and the other end is connected to ground.

Wherein the time constant of the first RC circuit 1011 is greater than the time constant of the second RC circuit 1013.

The first time length corresponding to the first RC circuit 1011 minus the second time length corresponding to the second RC circuit 1013 is greater than or equal to the preset time length. The first time length is a time length required for the terminal voltage (i.e., voltage at point a) of the capacitor C1 of the first RC circuit 1011 to reach the turn-on voltage of the Q1 from the start of power supply of the system power supply VSYS, the second time length is a time length required for the terminal voltage (i.e., voltage at point B) of the capacitor C2 of the second RC circuit 1013 to reach the voltage of the system power supply VSYS from the start of power supply of the system power supply VSYS, and the preset time length is the shortest time length required for the processor of the electronic device to successfully power on from the start of power on.

The specific circuit working principle is as follows:

(1) at the moment when the system power supply VSYS just supplies power, the initial voltage at the point a is 0V because the voltage across the capacitor C1 cannot be transient, and Q1 is not conductive, and similarly, the initial voltage at the point B is 0V because the voltage across the capacitor C2 cannot be transient.

(2) Since the time constant of the first RC circuit 1011 is greater than that of the second RC circuit 1013, the voltage at point B is pulled to the system power VSYS voltage earlier than the voltage at point a, and point B generates a rising edge signal earlier.

(3) When R1 and C1 are charged to make the voltage at point a reach the turn-on voltage Vth of Q1, Q1 is turned on, and the voltage at point B is pulled down to 0V, during which point B automatically generates a pulse signal (i.e., the power-on control signal) from low level to high level.

(4) When the system power supply VSYS is powered off, the discharge loop 1014 formed by D1 and R3 discharges the first RC circuit 1011, so that the voltage at point a is slowly discharged to 0V, to ensure that the initial voltage at point a is still 0V at the moment when the system power supply VSYS supplies power next time, and the first RC circuit 1011 and the second RC circuit 1013 can automatically generate the power-on control signal at point B again in the charging process, so as to ensure the reliability of the circuits.

Fig. 7 is a schematic diagram illustrating a change in terminal voltage of the capacitor during charging and discharging of the first RC circuit 1011 and the second RC circuit 1013. As can be seen from fig. 7, at time t1, the system power supply VSYS starts to supply power, the voltage at point B is pulled to the voltage of the system power supply VSYS earlier than the voltage at point a, at time t2, the voltage at point a reaches the turn-on voltage Vth of Q1, Q1 is turned on, the voltage at point B is pulled down to 0V, and at time t3, the voltage at point a is pulled to the voltage of the system power supply VSYS. It can be understood that by adjusting parameters of the components R1, R2, C1, C2, Q1 and the like, a time period from when the voltage of the point B voltage is pulled down to 0V to when the voltage of the system power source VSYS is pulled down is greater than or equal to a minimum time period required for a processor of the electronic device to successfully power up from the start of power up, or, a time period required for the voltage of the point a voltage to be pulled down to the turn-on voltage of the point Q1 from the start of power up of the system power source VSYS minus a time period required for the voltage of the point B voltage to be pulled down to the system power source VSYS reaches a minimum time period required for the processor of the electronic device to successfully power up from the start of power up.

Optionally, as shown in fig. 8, a power-on timing diagram of a power management chip provided in the embodiment of the present application is shown, where: after the power-on control signal is generated and input to the power-on trigger pin of the power management chip, a certain duration (e.g., 100ms) of the Debounce is provided first, then the power-on control signal is maintained at a high level, each unit of the processor system is powered on successively (including the reference power VREF, the core power VCORE, the central processor power VARM, the graphics processor power VGPU, and the input/output interface power VIO1/VIO2), and the power-on control signal needs to maintain the high level until the last unit of the processor system is powered on (e.g., the input/output interface power VIO1/VIO2) so that the processor system is powered on successfully, and thus, the duration during which the power-on control signal is maintained at the high level needs to reach a certain duration before the processor system is powered on completely.

It should be noted that, with reference to fig. 8, the preset time duration (i.e., the shortest time duration required from the power-on start to the power-on success of the processor of the electronic device) specifically includes 100ms (i.e., the time duration of Debounce) for enabling the PMIC to enter the power-on timing, and the time duration required for all units of the processor system to complete power-on. Here, 100ms is only a schematic illustration, and the specific value is related to the type of the power management chip.

As shown in fig. 9, the waveform diagram is the actually measured waveform diagram of the power-on control signal generated at the point B of the second RC circuit 1013, after the system power supply VSYS supplies power, the voltage at the point B is pulled to the voltage of the system power supply VSYS, when the voltage at the point a reaches the turn-on voltage Vth of the point Q1, the point Q1 is turned on, the voltage at the point B is pulled down to 0V, and in this process, the point B generates the power-on control signal meeting the trigger condition. Wherein, the triggering condition is that: the pulse signal from low level to high level, and the time length of the pulse signal required for maintaining high level reaches the shortest time length required by the processor of the electronic device from power-on to successful power-on.

Optionally, after the other circuit modules of the electronic device are powered on successfully, the system power VSYS corresponding to the processor and the power management device in the embodiment of the present application is powered on, and then the power-on control logic described in the embodiment of the present application is executed.

It should be noted that parameter values and circuit connection modes of components such as R1, R2, C1, C2, and Q1 in the circuit shown in fig. 6 are not unique, and may be flexibly designed according to the waveform requirement of the power management chip on the power-on control signal, and the embodiment of the present application is not limited.

Optionally, as shown in fig. 10, the schematic diagram is a circuit structure of another power management device provided in the embodiment of the present application, where:

the resistor R1, the capacitor C1, the resistor R2, the capacitor C2, the AND gate (AND) circuit U1, AND the diode D1 constitute the power-on control circuit 1010 of the power management device.

Specifically, the resistor R1 and the capacitor C1 form a third RC circuit 1015 of the power-on control circuit 1010, the resistor R2 and the capacitor C2 form a fourth RC circuit 1016 of the power-on control circuit 1010, and the diode D1 forms a discharge circuit of the power-on control circuit 1010.

One end of the third RC circuit 1015 and one end of the fourth RC circuit 1016 are both connected to the system power supply VSYS, specifically, the resistor R1 of the third RC circuit 1015 is connected to the system power supply VSYS, and the capacitor C2 of the fourth RC circuit 1016 is connected to the system power supply VSYS. The other terminals of the third RC circuit 1015 and the fourth RC circuit 1016 are both connected to GND, the input terminal 1 of the and circuit U1 is connected to a point a between the resistor R1 and the capacitor C1 of the third RC circuit 1015, and the input terminal 2 of the and circuit U1 is connected to a point B between the resistor R2 and the capacitor C2 of the fourth RC circuit 1016. An output end 4 of the and circuit U1 is connected to a power-on control pin (e.g., a power-on trigger ONKEY pin) of the PMIC, a power source positive end 5 of the and circuit U1 is connected to a system power supply VSYS, a power source negative end 3 of the and circuit U1 is grounded to GND, and a diode D1 is connected in parallel to a resistor R1 of the third RC circuit 1015.

Optionally, the time constant of the third RC circuit 1015 is smaller than the time constant of the fourth RC circuit 1016.

Wherein the fourth time duration corresponding to the fourth RC circuit 1016 minus the third time duration corresponding to the third RC circuit 1015 is greater than or equal to the preset time duration. Wherein the third time period is a time period required for the terminal voltage (i.e., voltage at point a) of the capacitor C1 of the third RC circuit 1015 to reach the voltage of the system power supply VSYS from the start of power supply of the system power supply VSYS, the fourth time period is a time period required for the voltage (i.e., voltage at point B) between the resistor R2 and the capacitor C2 of the fourth RC circuit 1016 to decrease from the voltage of the system power supply VSYS to a low level from the start of power supply of the system power supply VSYS, and the preset time period is a shortest time period required for a processor of the electronic device to successfully power on from the start of power on.

The specific circuit working principle is as follows:

(1) at the moment when the system power supply VSYS just supplies power, since the voltages at the two ends of the capacitors C1 and C2 cannot be changed in transient, the initial voltage at point a is 0V, the initial voltage at point B is the voltage of the system power supply VSYS, and since U1 is an and circuit, the output of the output terminal C of the and circuit U1 is at a low level.

(2) Since the time constant of the third RC circuit 1015 is smaller than that of the fourth RC circuit 1016, the voltage at the a-dot voltage pulled to the system power supply VSYS becomes high, and then the voltage at the B-dot voltage falls to low.

(3) During the period when the voltage at point a changes to high and the voltage at point B also changes to high, the output terminal C of the and circuit U1 goes high, at which time the voltage at point a is stable and the capacitor C2 of the fourth RC circuit 1016 is still charging.

(4) When the voltage at the point B drops to a low level after the capacitor C2 of the fourth RC circuit 1016 finishes charging, and the voltage at the point a is still high, the output of the output terminal C of the and circuit U1 is low, so that the output level of the output terminal C of the and circuit U1 changes to: low-high-low, resulting in a satisfactory power-up control signal.

It should be noted that parameter values and circuit connection modes of components such as R1, R2, C1, C2, and U1 in the circuit shown in fig. 10 are not unique, and may be flexibly designed according to the waveform requirement of the power management chip on the power-on control signal, and the embodiment of the present application is not limited.

Therefore, the power-on control circuit can be built by using discrete components, the power-on control signal is automatically generated after the power supply of the system power supply, the conventional key trigger signal is replaced, the power-on control circuit is suitable for completing the power-on trigger starting function in various scenes without keys, and the problem of normal power-on of the processor system in scenes without keys is effectively solved. In addition, this application embodiment utilizes discrete components and parts to build power-on control circuit, does not use integrated chip directly to produce power-on control signal violently, has also reduced the probability that hardware makes mistakes when reducing product cost, guarantees product stability.

Fig. 11 is a schematic circuit structure diagram of an electronic device according to an embodiment of the present disclosure. The electronic device 10 includes the system power supply 200, the processor 300, and the aforementioned power management apparatus 100, wherein:

the power management apparatus 100 is configured to power up the processor 300 after the system power supply 200 supplies power.

Optionally, the electronic device 10 includes, but is not limited to, a remote control device.

Optionally, the remote control device is a remote control terminal of a movable platform, for example, the movable platform includes an unmanned aerial vehicle, an unmanned vehicle, and the corresponding remote control terminal includes a remote controller.

Fig. 12 is a schematic circuit diagram of a movable stage assembly according to an embodiment of the present disclosure. The movable platform assembly includes a remote control terminal 20 and a movable platform 30, wherein:

and a remote control terminal 20 for controlling the movable platform 30.

The remote control terminal 20 includes a system power supply 200, a processor 300, and the power management device 100, where the power management device 100 is configured to power up the processor 300 after the system power supply 200 supplies power.

In summary, in the embodiment of the present application, after the power-on of each functional module is completed after the remote controller for controlling the mobile platform such as the unmanned aerial vehicle is started, the power-on trigger signal required by the application processor therein can be automatically and accurately generated through the power management device, so that the currently commonly used key trigger signal is effectively replaced, and the problem of normal power-on of the processor system in a scene where the key start-up cannot be performed is solved. In addition, the power management device of the embodiment of the application is built by utilizing discrete components and parts, and does not directly use an integrated chip violently, so that the product cost is reduced, the probability of hardware errors is reduced, and the product stability is ensured. Furthermore, the number of keys is reduced, and the space layout and simplified design of the electronic equipment applying the power management device are facilitated.

The power management device, the electronic device, and the movable platform assembly provided in the embodiments of the present application are described in detail above, and specific examples are applied herein to explain the principles and implementations of the present application, and the descriptions of the above embodiments are only used to help understand the core ideas of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims (22)

1. The utility model provides a power management device, is applied to electronic equipment, electronic equipment includes system power and treater, its characterized in that, power management device includes power-on control circuit and power management chip, wherein:

the power-on control circuit is connected with the system power supply and the power management chip, and the power management chip is connected with the processor;

the power-on control circuit is used for generating a power-on control signal after the system power supply supplies power, inputting the power-on control signal into the power management chip, and triggering the power management chip to power on the processor.

2. The apparatus of claim 1, wherein the power-up control circuit comprises two RC circuits, wherein respective time constants of the two RC circuits are different to generate the power-up control signal.

3. The apparatus of claim 2, wherein the two RC circuits comprise a first RC circuit and a second RC circuit, the power-up control circuit further comprising a switching element, wherein:

the switch element is connected between the first RC circuit and the second RC circuit, the first RC circuit and the second RC circuit are both connected with the system power supply, and the second RC circuit is connected with the power management chip.

4. The apparatus of claim 3, wherein a first terminal of the switching element is connected between the resistor and the capacitor of the first RC circuit, a second terminal of the switching element is connected between the resistor and the capacitor of the second RC circuit, and a third terminal of the switching element is grounded.

5. The apparatus of claim 3 or 4, wherein the switching element comprises a transistor or a metal oxide semiconductor field effect MOS transistor.

6. The apparatus of claim 3, wherein an output of the second RC circuit is connected to a power-on control pin of the power management chip, and wherein the output of the second RC circuit is located between a resistor and a capacitor of the second RC circuit;

and the output end of the second RC circuit is used for generating the power-on control signal and inputting the power-on control signal into the power management chip through the power-on control pin.

7. The apparatus of claim 3, wherein the power-up control circuit further comprises a discharge loop, wherein:

the discharge loop is connected in parallel with the first RC circuit;

and the discharge loop is used for discharging the first RC circuit after the system power supply is powered off.

8. The apparatus of claim 7, wherein the discharge circuit comprises a diode and a resistor, the discharge circuit comprising the diode and the resistor connected in parallel with the resistor of the first RC circuit.

9. The apparatus of claim 3, wherein a time constant of the first RC circuit is greater than a time constant of the second RC circuit.

10. The apparatus of claim 9, wherein a first duration corresponding to the first RC circuit minus a second duration corresponding to the second RC circuit is greater than or equal to a preset duration;

the first time length is a time length required for the terminal voltage of the capacitor of the first RC circuit to reach the starting voltage of the switch element from the system power supply, and the second time length is a time length required for the terminal voltage of the capacitor of the second RC circuit to reach the voltage of the system power supply from the system power supply.

11. The apparatus of claim 2, wherein the two RC circuits comprise a third RC circuit and a fourth RC circuit, the power-up control circuit further comprising a logic gate circuit, wherein:

the input end of the logic gate circuit is connected with the third RC circuit and the fourth RC circuit, the third RC circuit, the fourth RC circuit and the logic gate circuit are all connected with the system power supply, and the output end of the logic gate circuit is connected with the power management chip.

12. The apparatus of claim 11, wherein one input of the logic gate circuit is connected between the resistor and the capacitor of the third RC circuit, and another input of the logic gate circuit is connected between the resistor and the capacitor of the fourth RC circuit, the resistor of the third RC circuit being connected to the system power supply, and the capacitor of the fourth RC circuit being connected to the system power supply.

13. The apparatus of claim 11 or 12, wherein the logic gate circuit comprises an and gate circuit.

14. The apparatus of claim 11, wherein an output of the logic gate circuit is connected to a power-up control pin of the power management chip;

and the output end of the logic gate circuit is used for generating the power-on control signal and inputting the power-on control signal into the power management chip through the power-on control pin.

15. The apparatus of claim 11, wherein a time constant of the third RC circuit is less than a time constant of the fourth RC circuit.

16. The apparatus of claim 15, wherein a fourth time corresponding to the fourth RC circuit minus a third time corresponding to the third RC circuit is greater than or equal to a preset time;

the third time period is a time period required for the terminal voltage of the capacitor of the third RC circuit to reach the voltage of the system power supply from the system power supply, and the fourth time period is a time period required for the voltage between the resistor and the capacitor of the fourth RC circuit to be reduced to a low level from the voltage of the system power supply from the system power supply.

17. The apparatus according to claim 10 or 16, wherein the preset duration is a shortest duration required from the power-on start to the power-on success of the processor.

18. The apparatus of claim 1, wherein the power-up control signal comprises a pulse signal from a low level to a high level.

19. An electronic device, comprising:

a system power supply;

a processor;

the power management device of any of claims 1-18, the power management device to power up the processor after the system power supply.

20. The electronic device of claim 19, wherein the electronic device comprises a remote control device.

21. The electronic device of claim 20, wherein the remote control device is a remote control terminal of a movable platform.

22. A movable platform assembly, comprising:

a movable platform;

the remote control terminal is used for controlling the movable platform;

wherein, the remote control terminal includes:

a system power supply;

a processor;

the power management device of any of claims 1-18, the power management device to power up the processor after the system power supply.

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