CN112270408A - Heterogeneous system simulator framework and generation, access and main cycle operation method thereof - Google Patents
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Abstract
The invention provides a method for generating a heterogeneous system simulator frame, a method for accessing the heterogeneous system simulator frame, a method for operating a main cycle of the heterogeneous system simulator frame and the heterogeneous system simulator frame. The simulator frame of the heterogeneous system takes a bus connected with each module as a core, and each operation unit and peripheral equipment are conveniently and quickly connected together through a standardized bus interface, so that the heterogeneous system simulation with bus clock as precision is realized. The interfaces of the module connected to the bus are divided into a main interface and a slave interface, and the same module can selectively contain both interfaces or only one of the interfaces. The master interface may initiate bus access on its own, while the slave interface defines the response when the device is accessed. Through the framework, a user can neglect the structural difference among the modules and easily complete the construction of the heterogeneous system simulator.
Description
Technical Field
The invention relates to the technical field of computers. The invention particularly relates to a heterogeneous system simulator framework and a generation, access and main cycle operation method thereof.
Background
After an exponential growth of the semiconductor industry for over half a century, the number of transistors that a single chip can integrate has far exceeded 10 billion, enough to easily place an entire system on a small chip. As moore's law moves toward the limit, people have to look at the pure upgrading process to explore the processor architecture. Symmetric multiprocessor architectures, large and small core architectures, heterogeneous systems, and a variety of processor platforms are layered in a large variety. The layout rules of the symmetric multiprocessor and the large and small core architecture are ordered, and in the heterogeneous system, besides the traditional general-purpose processor, various special computing modules such as a Graphic Processing Unit (GPU), a Digital Signal Processor (DSP), a Field Programmable Gate Array (FPGA), a neural network accelerator and the like are also included, so that the complexity is greatly increased.
The heterogeneous system has no mature and reliable simulator frame so far, can be built again only according to development requirements, not only has huge workload, but also cannot be well integrated among modules because of no uniform interface, cannot reach the simulation precision of a clock level, and even can influence the simulation accuracy. Thus, a heterogeneous simulator framework is needed that requires only a small amount of code to integrate the various modules together.
Disclosure of Invention
The invention aims to provide a method for generating a heterogeneous system simulator frame, a method for accessing the heterogeneous system simulator frame, a method for operating a main loop of the heterogeneous system simulator frame and the heterogeneous system simulator frame.
The simulator frame of the heterogeneous system takes a bus connected with each module as a core, and all operation units and peripheral equipment are conveniently and quickly connected together through a standardized bus interface, so that the heterogeneous system simulation with bus clock as precision is realized. The interfaces of the module connected to the bus are divided into a main interface and a slave interface, and the same module can selectively contain both interfaces or only one of the interfaces. The master interface may initiate bus access on its own, while the slave interface defines the response when the device is accessed. Through the framework, a user can neglect the structural difference among the modules and easily complete the construction of the heterogeneous system simulator.
The invention provides a method for generating a heterogeneous system simulator framework, wherein a simulator can call a parameter parser. The parameter parser registers a parameter list and a corresponding parameter processing function that can be supported by the simulator. The heterogeneous system simulator framework is capable of configuring a plurality of sub-modules onto a bus.
A plurality of sub-modules each containing a slave interface class. And a plurality of slave interface type definition submodules receive corresponding response information after bus access.
The simulator frame generation method of the heterogeneous system comprises the following steps:
step S101, the parameter analyzer analyzes the initialization parameters of the simulator according to the command line.
And step S102, the simulator calls an initialization function of the submodule according to the initialization parameter.
Step S103, acquiring sub-module initialization configuration parameters by the sub-module initialization function. And configuring the system resources of the simulator according to the simulator initialization configuration parameters. And configuring the system resources of the sub-modules according to the sub-module initialization configuration parameters.
In step S104, a bus is generated. The bus has a registration function. Multiple slave interface classes may be added to the device list of the bus by the registration function.
In step S105, a bus master interface is generated. The bus master interface is a bus handle.
In an embodiment of the method for generating a heterogeneous system simulator frame according to the present invention, step S101 further includes: step S100, a start command line is acquired. The launch command line has a simulator name and simulator parameters.
In another embodiment of the method for generating a heterogeneous system simulator frame of the present invention, the sub-module registration parameters include: the starting address of the sub-module, the length of the sub-module and the slave interface class information.
The invention provides an access method of a simulator framework of a heterogeneous system, which comprises the simulator framework generated by the simulator framework generation method of the heterogeneous system. The access method of the heterogeneous system simulator framework comprises the following steps:
step S201, when the access device accesses the bus through the bus master interface.
Step S202, the bus inquires the current sub-module corresponding to the access address in the bus registration list according to the initial address and the length of each sub-module, if the sub-module meeting the conditions is inquired, the access address subtracts the base address of the module, and then the bus transmits the access request to the sub-module. If not, a bus access warning message is sent out.
In an embodiment of the method for accessing a heterogeneous system simulator framework according to the present invention, step S202 includes:
in step S2021, a corresponding access request function is called through the bus handle. The access request function includes: passing the target address parameter of the access, the type parameter of the access, the length parameter of the access and the pointer parameter of the data.
Step S2022, determining whether the access request function called by the bus handle and the current access address are in the bus registry, and obtaining the corresponding sub-module according to the sub-module registration parameter. And if so, requesting to access the submodule. If not, a bus access warning message is sent out.
In a third aspect of the present invention, a method for main loop operation of a simulator frame of a heterogeneous system is provided, which includes the simulator frame generated by the simulator frame generation method of the heterogeneous system in the present invention. The response message includes a loop processing function. A main loop method of a heterogeneous system simulator framework comprises the following steps:
step S301, obtaining the registration sequence of the current sub-module according to the bus registration table.
In step S302, an access frequency threshold is obtained. The access time threshold is the number of sub-module interfaces which can be accessed simultaneously in the period of the main loop.
Step S303, in a period of a main cycle, circularly calling the processing function of the sub-module according to the registration sequence of the sub-module.
And S304, judging whether the bus access frequency of the current main cycle is smaller than an access frequency threshold value, if so, generating access success information. If not, access failure information is generated.
In another embodiment of the method for operating a main loop of a heterogeneous system simulator frame according to the present invention, step S303 further includes:
step S3031, if the debug interrupt instruction is acquired, the operation in the main loop is interrupted.
In a fourth aspect of the invention, a heterogeneous system simulator framework is provided, wherein the simulator is capable of invoking a parameter parser. The parameter parser registers a parameter list and a corresponding parameter processing function that can be supported by the simulator. The heterogeneous system simulator framework is capable of configuring a plurality of sub-modules onto a bus.
A plurality of sub-modules each containing a slave interface class. And a plurality of slave interface type definition submodules receive corresponding response information after bus access.
The simulator framework of the heterogeneous system includes:
an initialization module configured to a parameter parser parses initialization parameters of the simulator according to the command line.
And the submodule initialization function acquisition module is configured to call the initialization function of the submodule by the simulator according to the initialization parameter.
And the system resource configuration module is configured to obtain the initialization configuration parameters of the sub-module by the sub-module initialization function. And configuring the system resources of the simulator according to the simulator initialization configuration parameters. And configuring the system resources of the sub-modules according to the sub-module initialization configuration parameters.
A bus having a registration function. Multiple slave interface classes may be added to the device list of the bus by the registration function. The bus master interface is a bus handle.
In one embodiment of the heterogeneous system simulator framework of the present invention, the plurality of sub-modules comprises a riscv open source core sub-module, a RAM memory sub-module, and a DEBUG log print sub-module.
The following will further explain the characteristics, technical features, advantages and implementations of the heterogeneous system simulator framework, the access method of the heterogeneous system simulator framework, the main cycle operation method of the heterogeneous system simulator framework and the heterogeneous system simulator framework in a clear and understandable manner by referring to the accompanying drawings.
Drawings
Fig. 1 is a flow chart for explaining a method for generating a heterogeneous system simulator framework according to an embodiment of the present invention.
Fig. 2 is a flowchart for explaining a method for generating a heterogeneous system simulator framework according to another embodiment of the present invention.
Fig. 3 is a flowchart for explaining an access method of a heterogeneous system simulator framework in an embodiment of the present invention.
Fig. 4 is a flowchart for explaining a main loop operation method of a heterogeneous system simulator framework in an embodiment of the present invention.
Fig. 5 is a schematic diagram illustrating the components of a heterogeneous system simulator framework according to an embodiment of the present invention.
FIG. 6 is a system diagram illustrating a simulator in one embodiment of the invention.
Fig. 7 is a schematic diagram for explaining an operation flow of the simulator in still another embodiment of the present invention.
Detailed Description
In order to more clearly understand the technical features, objects and effects of the present invention, embodiments of the present invention will now be described with reference to the accompanying drawings, in which the same reference numerals indicate the same or structurally similar but functionally identical elements.
"exemplary" means "serving as an example, instance, or illustration" herein, and any illustration, embodiment, or steps described as "exemplary" herein should not be construed as a preferred or advantageous alternative. For the sake of simplicity, the drawings only schematically show the parts relevant to the present exemplary embodiment, and they do not represent the actual structure and the true scale of the product.
The invention provides a method for generating a heterogeneous system simulator framework, wherein a simulator can call a parameter parser. The parameter parser registers a parameter list and a corresponding parameter processing function that can be supported by the simulator. The heterogeneous system simulator framework is capable of configuring a plurality of sub-modules onto a bus.
A plurality of sub-modules that generate a slave interface class. And receiving corresponding response information after bus access from the definition submodule in the interface class.
As shown in fig. 1, the method for generating a simulator framework of a heterogeneous system includes:
step S101, the initialization parameter is analyzed.
In this step, the parameter analyzer analyzes the initialization parameters of the simulator according to the command line.
Step S102, obtaining an initialization function of the sub-module.
In this step, the simulator calls the initialization function of the sub-module according to the initialization parameter.
Step S103, configuring system resources.
In this step, the sub-module initialization function obtains sub-module initialization configuration parameters. And configuring the system resources of the simulator according to the simulator initialization configuration parameters. And configuring the system resources of the sub-modules according to the sub-module initialization configuration parameters.
Step S104, configuring the bus.
In this step, a bus is generated. The bus has a registration function. Multiple slave interface classes may be added to the device list of the bus by the registration function.
In step S105, a bus master interface is generated.
In this step, a bus master interface is generated. The bus master interface is a bus handle.
As shown in fig. 2, in an embodiment of the method for generating a heterogeneous system simulator frame according to the present invention, step S101 further includes:
step S100, a start command line is acquired.
In this step, a start command line is obtained. The launch command line has a simulator name and simulator parameters.
In another embodiment of the method for generating a heterogeneous system simulator frame of the present invention, the sub-module registration parameters include: the starting address of the sub-module, the length of the sub-module and the slave interface class information.
As shown in fig. 3, a second aspect of the present invention provides an access method for a simulator framework of a heterogeneous system, including a simulator framework generated by the simulator framework generation method of the heterogeneous system. The access method of the heterogeneous system simulator framework comprises the following steps:
in step S201, a bus registry is acquired.
In this step, the access device accesses the bus through the bus master interface.
Step S202, judging the corresponding current sub-module.
In this step, the bus queries the current sub-module corresponding to the access address in the bus registration list according to the starting address and the length of each sub-module, and if a sub-module meeting the conditions is queried, the bus subtracts the base address of the module from the access address and transmits an access request to the sub-module. If not, a bus access warning message is sent out.
As shown in fig. 3, in an embodiment of the method for accessing a heterogeneous system simulator framework according to the present invention, step S202 includes:
in step S2021, a corresponding access request function is called through the bus handle.
In this step, the corresponding access request function is called through the bus handle. The access request function includes: passing the target address parameter of the access, the type parameter of the access, the length parameter of the access and the pointer parameter of the data.
Step S2022, determining the corresponding current sub-module according to the bus handle.
In this step, whether the access request function called by the bus handle and the current access address are in the bus registry or not is judged, and the corresponding sub-module is obtained through the sub-module registration parameter. And if so, requesting to access the submodule. If not, a bus access warning message is sent out.
As shown in fig. 4, according to a third aspect of the present invention, a method for main loop operation of a simulator framework of a heterogeneous system is provided, which includes a simulator framework generated by the simulator framework generation method of a heterogeneous system in the present invention. The response message includes a loop processing function.
A main loop method of a heterogeneous system simulator framework comprises the following steps:
step S301, obtaining the registration sequence of the current sub-module according to the bus registration table.
In step S302, an access frequency threshold is acquired.
In this step, an access number threshold is obtained. The access time threshold is the number of sub-module interfaces which can be accessed simultaneously in the period of the main loop.
Step S303, the number of access times of the current main loop is acquired.
In this step, in a cycle of a main cycle, the processing function of the sub-module is called circularly according to the registration sequence of the sub-module.
And S304, judging the threshold value of the access times.
In this step, it is determined whether the bus access frequency of the current main cycle is less than an access frequency threshold, and if so, access success information is generated. If not, access failure information is generated.
As shown in fig. 4, in another embodiment of the method for operating the main loop of the heterogeneous system simulator framework according to the present invention, step S303 further includes:
in step S3031, the operation of the main cycle is interrupted.
In this step, if a debug interrupt instruction is acquired, the operation in the main loop is interrupted.
A fourth aspect of the present invention, as shown in FIG. 5, provides a heterogeneous system simulator framework, where the simulator can invoke a parameter parser. The parameter parser registers a parameter list and a corresponding parameter processing function that can be supported by the simulator. The heterogeneous system simulator framework is capable of configuring a plurality of sub-modules onto a bus.
A plurality of sub-modules that generate a slave interface class. And receiving corresponding response information after bus access from the definition submodule in the interface class.
The simulator framework of the heterogeneous system includes: the system comprises a bus 10, an initialization module 20, a sub-module initialization function acquisition module 30, a system resource configuration module 40 and a generation module 50.
An initialization module 20 configured to be a parameter parser parses initialization parameters of the simulator according to the command line.
A sub-module initialization function acquisition module 30 configured to invoke the initialization function of the sub-module according to the initialization parameters.
A system resource configuration module 40 configured to obtain sub-module initialization configuration parameters for the sub-module initialization function. And configuring the system resources of the simulator according to the simulator initialization configuration parameters. And configuring the system resources of the sub-modules according to the sub-module initialization configuration parameters.
The bus 10 has a registration function. Multiple slave interface classes may be added to the device list of the bus by the registration function. The bus master interface is a bus handle.
In one embodiment of the heterogeneous system simulator framework of the present invention, the plurality of sub-modules comprises a riscv open source core sub-module, a RAM memory sub-module, and a DEBUG log print sub-module.
In another embodiment of the present invention, a simulator framework oriented to heterogeneous systems is provided, where a bus capable of connecting all modules is used as a core, and a sub-module is integrated onto the bus through several operations, such as replacing access operations as a bus master interface, encapsulating a slave interface module for responding to bus access, registering a slave module onto the bus, and the like. The operation cores and peripheral devices with various different architectures can be simply and quickly integrated together through the method, and the development of the heterogeneous system simulator is greatly simplified.
The whole simulator frame consists of the following parts:
a) parameter parsing and module initialization part
b) Simulator bus
c) Loop control of simulator
d) Debugging module of simulator
e) Operation information control module of simulator
Content of part a:
the simulator generated by the simulator framework is started in a command line mode, and the starting command is as follows: simulator name + [ simulator parameters ]. Wherein the simulator parameters are selectable. The framework firstly registers a parameter list supported by a simulator and a corresponding parameter processing function into a parameter resolver, the supported parameter formats are-x (x is the name of the parameter) and-x is y (x is the name of the parameter, and y is the value of the parameter), then the input of a command line is acquired from a system, then the parser is used for parsing the input parameter to obtain the configuration parameters (such as the size of a simulator RAM, an instruction subset supported by riscv and the like) required by the simulator initialization, the initialization function of each submodule is called to perform initialization operation on the module (such as allocating the memory of the RAM, initializing the riscv core and the like), and finally each module is registered on a bus.
Second, content of part b:
as shown in fig. 6, the respective sub-modules (riscv open source core, RAM, DEBUG log print module, etc.) are connected together through a bus.
The simulator needs to configure the data length that can be obtained by a single access of the bus, the number of interfaces that can be accessed simultaneously in the same period, and the like during initialization.
Before the submodule is accessed into the bus, a slave interface class is required to be created, the response of the submodule when the submodule receives bus access is defined in the slave interface class, the operation which is required to be triggered is mainly carried out by bus reading and bus writing (if the RAM is read, the content on the corresponding address of the RAM is returned, and if UART is written, characters are output to a console), data can be transmitted through a pointer and 0 is returned after one successful access; a non-zero error code is returned for the failed access.
After the slave interface class is created, the slave modules can be accessed into the bus using the registration function of the bus. The registration (i.e. access) of a submodule requires the input of the start address of the submodule, the length of the submodule and the call pointer 3 parameters from the interface class. The bus master interface is a unique bus handle, and a module to be connected with the bus master interface must store the bus handle during initialization and initiate bus access through the bus handle when entering a master loop.
When one device accesses the bus through the main interface, the bus firstly queries the module corresponding to the access address in the registration list of the device according to the initial address and the length of each module, and if the module with the condition is queried, the access address subtracts the base address of the module, and then the access request is transmitted to the sub-module; if the corresponding module cannot be queried, a bus access warning is issued and a corresponding non-zero error code is returned. The slave modules that are accessed cannot access the bus in reverse in the slave interface class, and the bus access must be performed in the master cycle.
The access of a bus needs to call a corresponding access request function through a bus handle, and the accessed target address, the accessed type, the accessed length and the pointer of data are transferred through the function with 4 parameters.
Third, content of part c:
the framework has a main loop, when the initialization operation of each module of the simulator is completed, the simulator enters the main loop, and the circular processing function of each sub-module is called circularly in the main loop according to the registration sequence of the sub-modules. And each iteration of the main loop is equivalent to one clock period running in hardware, so that the simulation precision of the simulator is ensured. The read-write interface of the bus can be called in the main loop, if the access times of the bus in the current clock cycle do not exceed the allowable times (namely the number of interfaces that can be accessed simultaneously in the same cycle of the bus), a zero value is returned to indicate that the access is successful, otherwise, the access is failed, and the retry is needed in the next iteration.
Fourthly, content of the part d:
the framework is provided with a simple debugging module, the console can enter a debugging mode by inputting ctrl + C, and the debugging module can interrupt the operation of the main loop at the moment. In the debug mode, a debug instruction can be input in the console to read data on the bus or modify the value of a certain address, and the debugger can be configured to detect the value of a certain address on the bus during the cycle and interrupt the main cycle running mode according to the change of the value. These functions can basically meet the requirements of most applications.
Fifth, content of part e:
the framework is accompanied by an operation information control module by means of which the opening and interruption of operation information can be configured using command lines. The control rules for running the information may be specified using regular expressions, each rule containing two parts, one part being the name of the module and the other part being the type of information, the two parts being used': ' spaced apart. Useful information can be screened out from a large amount of operation information through a combination of a plurality of control rules and output to the console.
The invention has the advantages that:
1) the interface commonality is strong: various modules such as CPU, GPU and other operation cores and UART, SDRAM, and other peripheral devices can be connected to the bus.
2) The interface is succinct: typically only 100 lines of code are required to add a module to the simulator.
3) The efficiency is high: the whole framework only needs to carry out a small amount of processing when accessing the bus, and does not occupy too much operation time.
4) Approximate clock-level simulation accuracy: the whole simulator can achieve the simulation precision of an approximate clock level (the specific precision depends on the realization of sub-modules), and is suitable for most research tasks.
5) The functions are complete: the simulator is provided with a parameter analysis module, a debugging module and an operation information control module, and is suitable for most simulator applications.
It should be understood that although the present description is described in terms of various embodiments, not every embodiment includes only a single embodiment, and such description is for clarity purposes only, and those skilled in the art will recognize that the embodiments described herein as a whole may be suitably combined to form other embodiments as will be appreciated by those skilled in the art.
The above-listed detailed description is only a specific description of a possible embodiment of the present invention, and they are not intended to limit the scope of the present invention, and equivalent embodiments or modifications made without departing from the technical spirit of the present invention should be included in the scope of the present invention.
Claims (9)
1. The method for generating the heterogeneous system simulator framework is characterized in that the simulator can call a parameter parser; the parameter analyzer registers a parameter list which can be supported by the simulator and a parameter processing function corresponding to the parameter list; the heterogeneous system simulator framework is capable of configuring a plurality of sub-modules onto a bus;
the plurality of sub-modules each containing a slave interface class; the slave interface type definition sub-modules receive corresponding response information after bus access;
the simulator framework generation method of the heterogeneous system comprises the following steps:
step S101, the parameter analyzer analyzes the initialization parameters of the simulator according to the command line;
step S102, the simulator calls an initialization function of the submodule according to the initialization parameter;
step S103, the sub-module initialization function obtains sub-module initialization configuration parameters; configuring system resources of the simulator according to the simulator initialization configuration parameters; configuring system resources of the sub-modules according to the sub-module initialization configuration parameters;
step S104, generating a bus; said bus having a registration function; the slave interface classes are added to a device list of the bus by the registration function;
step S105, generating a bus main interface; the bus master interface is a bus handle.
2. The generation method according to claim 1, wherein the step S101 further includes:
step S100, a starting command line is obtained; the start command line has a simulator name and simulator parameters.
3. The generation method of claim 2, wherein the sub-module registering parameters comprises: the starting address of the sub-module, the length of the sub-module and the slave interface class information.
4. An access method for a heterogeneous system simulator framework, comprising a simulator framework generated by the simulator framework generation method for a heterogeneous system according to any one of claims 1 to 3;
the access method of the heterogeneous system simulator framework comprises the following steps:
step S201, when the access device accesses the bus through the bus main interface;
step S202, the bus inquires the current sub-module corresponding to the access address in the bus registration list according to the initial address and the length of each sub-module, if the sub-module meeting the conditions is inquired, the access address subtracts the base address of the module, and then the bus transmits the access request to the sub-module; if not, a bus access warning message is sent out.
5. The access method according to claim 4, wherein the step S202 comprises:
step S2021, calling a corresponding access request function through the bus handle; the access request function includes: transmitting an accessed target address parameter, an accessed type parameter, an accessed length parameter and a pointer parameter of data;
step S2022, judging whether the corresponding sub-modules can be obtained through sub-module registration parameters according to the access request function called by the bus handle and the current access address in the bus registry; if yes, requesting to access the sub-module; if not, a bus access warning message is sent out.
6. A main loop operation method of a heterogeneous system simulator frame, comprising a simulator frame generated by the simulator frame generation method of a heterogeneous system according to any one of claims 1 to 3; the response information comprises a cyclic processing function; the main circulation method of the heterogeneous system simulator framework comprises the following steps:
step S301, acquiring the registration sequence of the current sub-module according to the bus registration table;
step S302, obtaining an access frequency threshold; the access time threshold is the number of sub-module interfaces which can be accessed simultaneously in the period of the main cycle;
step S303, circularly calling the processing function of the sub-module according to the registration sequence of the sub-module in a period of a main cycle;
s304, judging whether the bus access frequency of the current main cycle is smaller than the access frequency threshold value, if so, generating access success information; if not, access failure information is generated.
7. The main loop operation method according to claim 6, wherein the step S303 further comprises:
step S3031, if a debug interrupt instruction is acquired, the operation in the main loop is interrupted.
8. A heterogeneous system simulator framework, wherein the simulator is capable of invoking a parameter parser; the parameter analyzer registers a parameter list which can be supported by the simulator and a parameter processing function corresponding to the parameter list; the heterogeneous system simulator framework is capable of configuring a plurality of sub-modules onto a bus;
the plurality of sub-modules each containing a slave interface class; the slave interface type definition sub-modules receive corresponding response information after bus access;
the simulator framework of the heterogeneous system comprises:
an initialization module configured to the parameter parser parses initialization parameters of the simulator according to the command line;
a sub-module initialization function acquisition module configured to call the initialization function of the sub-module by the simulator according to the initialization parameter;
a system resource configuration module configured to obtain sub-module initialization configuration parameters for the sub-module initialization function; configuring system resources of the simulator according to the simulator initialization configuration parameters; configuring system resources of the sub-modules according to the sub-module initialization configuration parameters;
a bus, said bus having a registration function; the slave interface classes are added to a device list of the bus by the registration function; the bus master interface is a bus handle.
9. The heterogeneous system simulator framework of claim 8, wherein the plurality of sub-modules comprises a riscv open source kernel sub-module, a RAM memory sub-module, and a DEBUG log print sub-module.
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