CN112242837A - DSI3 data bus short-circuit prevention driving circuit with double current limitation - Google Patents
DSI3 data bus short-circuit prevention driving circuit with double current limitation Download PDFInfo
- Publication number
- CN112242837A CN112242837A CN202010503957.3A CN202010503957A CN112242837A CN 112242837 A CN112242837 A CN 112242837A CN 202010503957 A CN202010503957 A CN 202010503957A CN 112242837 A CN112242837 A CN 112242837A
- Authority
- CN
- China
- Prior art keywords
- transistor
- terminal
- node
- mpo
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/02—Details
- H04B3/36—Repeater circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Amplifiers (AREA)
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Abstract
The invention relates to a driver circuit (TR) for a data bus at its output (Out). The drive circuit comprises a switching transistor (MPO), a first current limiting device (M27, M28, M218, M36, M33, MPOref) A second current limiting device (M66, M73, MPH)clmp) A first voltage supply line (Vbatt) and a reference potential line (GND). The switching transistor (MPO) is set and/or set to a potential which pulls the data bus at its output (Out) towards the first voltage supply line (VbatH) IN dependence on the input signal (IN). First current limiting means (M27, M28, M218, M36, M33, MPO)ref) The current through the switching transistor (MPO) is limited. Reference potential line(s) in the drive circuit (TR) (TR)GND) and the output terminal (Out), the second current limiting means (M66, M73, MPH)clmp) The current flowing through the switching transistor (MPO) is limited and adjusted to a current value different from 0A. Thus, the control capability is maintained even during the opening process and in the event of a short circuit.
Description
Technical Field
The invention relates to a driver circuit TR with a switching transistor MPO for controlling a data bus connected to an output Out of the driver circuit TR.
Background
The DSI3 data bus is used in many automotive sensor systems to transfer data between sensors and control devices. To prevent a short circuit, the driver for the data bus must be current limited. Here, the problem is that the operating voltage is relatively high and the level is dependent on the operating voltage and independent of the reference potential.
Disclosure of Invention
It is therefore an object of the present invention to provide a solution which does not have the above-mentioned drawbacks of the prior art and which has other advantages.
The object of the invention is to limit the current of a switching transistor MPO, preferably a P-channel field effect transistor. Although the first terminal of the switching transistor MPO is at a relatively high potential (e.g., 30V) of the first voltage supply line VbatH, a simple digital transistor having no insulation strength in this region should be able to be used. Importantly, the current limitation of the transistor current of the switching transistor MPO must start very quickly and without oscillation due to the low impedance of the line. This is the object of the present invention.
This object is solved by a device according to the description herein.
Solution scheme
During the receive phase, the switching transistor MPO clamps the DSI3 bus at the output Out of the driver circuit TR to the potential of the first voltage supply line VbatH. This receiving phase of the DSI3 bus is characterized by an input current signal at the output Out of the driver circuit TR. This means that, based on the reference potential of the reference potential line GND, current is drawn from the switching transistor MPO via the output terminal Out in the circuit of the drive circuit TR. In the DSI3 bus, the signal current may have three values of 0A, 12mA, and 24 mA. Furthermore, a positive current value always corresponds to the current flowing Out of the circuit at the output Out. In addition to this signal current, there is also a DC current of 0 to 40 mA.
Normal mode of operation
The switching transistor MPO is typically a P-channel MOS field effect transistor serving as a switch. The switching transistor MPO is operated such that its gate voltage is switched between 0V and a defined potential.
The definition potential VR is set as a voltage drop across the first resistor R7V. The voltage drop across the first resistor R7V corresponds to the voltage value VRWert＝IrefWertImage factor R7VWert. The mirror factor of the current mirror is preferably 1: 10. The reference current Iref is preferably about 10 μ a. Since the switching transistor MPO preferably has a gate of 5V on its gate-source path, the first resistor R7V is preferably dimensioned in the following manner: based on the potential of the first voltage supply line VbatH, for example, about 4.8V is preferably set as the definition potential VR. Therefore, the potential at the sixth node K6 is subsequently determined. This is the normal mode of operation.
Implementation of current limiting
Since the switching transistor MPO is large in order to meet the requirements, no element can be connected in series with the switching transistor MPO. Therefore, current limitation cannot be achieved by inserting a current limiting function into the current path of the switching transistor MPO that meets the requirements. In addition, a particularly important requirement is that the on-resistance of the switching transistor MPO is, for example, only about 1.5 Ohm. This cannot generally be achieved by connecting other functional elements in series with the switching transistor MPO.
In contrast, the mechanism for limiting current interferes with the current flowing through the first resistor R7V via the first source follower transistor M128 and the second source follower transistor M33. Therefore, the definition potential VR is changed by current limitation. Therefore, the gate-source voltage of the switching transistor MPO is also changed, and thus the current flowing through the switching transistor MPO is also changed.
The first source follower transistor M128 has no effect on the current limitation. However, it intervenes in the same way to switch the switching transistor MPO to the power-off state. Therefore, the first source follower transistor M128 has a switching function for switching operation of the switching transistor MPO. The first source follower transistor M128 is used for switching operations, and the second source follower transistor M33 ensures intervention in one of the two current limiting means for the current flowing through the first resistor R7V.
The second current limiting means is composed of a third transistor M66, a bridge resistor R, a fourth transistor M73, and a fifth transistor MPHclmpAnd (4) forming.
The mode of operation of the current limiting means for the current flowing through the switching transistor MPO will be discussed below.
Current limiting device 1
A part of the first current limiting means (hereinafter referred to as current limiting means 1) monitors the current flowing through the switching transistor MPO. This is done by copying the drain voltage of the switching transistor MPO to a parallel model transistor MPO having the same gate voltage and the same source voltagerefAnd (4) completing. The sixth transistor M27, The seventh transistor M28, and The first Current source M218 and The second Current source M36 form a so-called Current conveyor circuit, see Current conveyor-a novel circuit building block (The Current conveyor building block) published in kennes smith (Kenneth c. smith), alder sedela (Adel Sedra) at proc.ieee 56 volume 1368-1369, or "Current conveyor-a variant, application and Hardware implementation (Current-a harware) published in Springer publication ISBN 978-3-319-35049-3, 2015.
The first current source M218 generates a defined potential at the gate of the seventh transistor M28 as a P-channel transistor together with the sixth transistor M27 as a MOS diode. The current flowing through the seventh transistor M28 is determined by the second current source M36. This therefore generates a gate-source voltage on the seventh transistor M28, and copies the drain potential of the switching transistor MPO to the model transistor MPOrefOf the substrate.
The current from above satisfies the current source current of the second current source M36 located below the eighth transistor M37. The potential of the common fourth node K4 of the eighth transistor M37 and the second current source M36 drives the second source follower transistor M33, which draws more or less current from the first resistor R7V. The parasitic input capacitance of the common fourth node K4 of the eighth transistor M37 and the second current source M36 is charged or discharged by a transistor current of the eighth transistor M37 and a current difference of the second current source M36.
The mirror ratio is selected so that the current limit value of the P-channel switching transistor MPO may preferably be, for example, 10 μ a to 84 mA.
Current limiting device 2
Only the above-described current limiting device 1 is insufficient. That is, if the output terminal Out of the drive circuit TR is shorted to the reference potential of the reference potential line GND due to an operation error or a process error of a workshop, for example, the voltage drop across the sixth transistor M27 and the first current source M218 approaches 0V. In case such a short circuit cannot be ruled out, therefore, the control loop of the current limiting device 1 described above will no longer function.
In the case of such a short circuit with a very low voltage drop, the cross-over resistor R will, due to the short circuit, draw current from the fifth transistor MPH via the output Out of the driver circuit TRclmpAnd the current mirror formed by the third transistor M66 is pulled toward the reference potential of the reference potential line GND.
Through a fifth transistor MPHclmpAnd a third transistor M66, which is another current mirror transistor, feeds a resistance current across the resistor R to the gate node of the switching transistor MPO. This resistance current across the resistor R therefore reduces the gate-source voltage of the switching transistor MPO, thereby reducing the conductivity of the switching transistor MPO. Thereby controlling the switching transistor MPO. In the current limiting device 2, the current limit value of the current flowing through the switching transistor MPO is set by the resistance value across the resistor R.
Improvements in current limiting devices 2
According to the invention, a modification of the current limiting device 2 can be considered:
the foldback characteristic (foldback charakterstrik) may be set by the fourth transistor M73. This means that in the case of a short circuit, a reduced short-circuit current is defined, so that the power loss of the P-channel switching transistor MPO is minimized. The advantage is that on the one hand no damaging current flows through the switching transistor MPO, and on the other hand the control loop can continue to function.
Characteristic of the invention
There is still a problem in turning on the circuit. At the beginning, the output Out of the drive circuit TR is at the reference potential of the reference potential line GND. Because the bus capacitance is large, the transient of the opening process at the output Out of the driver circuit TR is shortened. Thus, at start-up, the current limiting device 2 is active and prevents the circuit from starting. In order to avoid this, a fourth transistor M73 is additionally inserted, and the fourth transistor M73 can ensure the start-up of the entire circuit even if there is an operating current limiting device 2.
For this reason, in the case where the output terminal Out of the driving circuit TR is short-circuited to the reference potential of the reference potential line GND, the fourth transistor M73 can ensure a minimum current, so that the control loop still receives a valid control signal when a condition similar to the opening of the short-circuit occurs.
The circuit also differs from the prior art in that the potential within the circuit is defined by a first resistor R7V. A resistor like the first resistor R7V is a well-defined, highly scalable process element in CMOS semiconductor processes that can provide any voltage within a certain range and has a stable current.
Although the switching transistor MPO is large, the circuit speed is very fast since only current is used.
For example, the current flowing through the first resistor R7V may be corrected relatively quickly, preferably at 100 μ Α and 48kOhm, without stability problems.
The proposed circuit is characterized in that the gate potential of the switching transistor MPO is generated by means of a first resistor R7V and a bandgap circuit, not shown here, which generates a reference current Iref via a conversion resistor RS for converting a bandgap voltage into the reference current Iref. The first resistor R7V and the transfer resistor RS should be of the same type (e.g., polysilicon resistors) on the crystal of the common integrated circuit, and preferably similar (matched). Thereby, the band gap voltage based on the reference potential of the reference potential line GND can be converted into the defined potential VR based on the potential of the first voltage power supply line VbatH, wherein the voltage difference between the defined potential VR (the gate potential of the switching transistor MPO) and the potential of the first voltage power supply line VbatH is determined by the ratio between the resistance value of the conversion resistor RS and the resistance value of the first resistor R7V.
The eighth transistor M37 is generally not required for the claimed function of the disclosed invention. As a cascode transistor, the eighth transistor only protects the second current source M36 from overvoltage. In the case of a pure 5V embodiment, the eighth transistor M37 is redundant and is preferably not used. Accordingly, the thirteenth node K13 is not required, and may be replaced by the fourth node K4 after the eighth transistor M37 is removed. The second terminal of the seventh transistor M28 is a fourth node K4.
The thirteenth transistor M38 is generally not required for the claimed function of the disclosed invention. As a cascode transistor, the thirteenth transistor only protects the first current source M218 from overvoltage. In the case of a pure 5V embodiment, the thirteenth transistor M38 is redundant and is preferably not used. Accordingly, the twelfth node K12 is not required, and may be replaced by the seventh node K7 after the thirteenth transistor M38 is removed. The first current source M218 is directly connected to the second terminal of the sixth transistor M27 via the seventh node K7.
Advantages of the invention
In the proposed circuit, no amplifier and feedback control are used to limit the current. Furthermore, this means that there is no control loop with oscillation capability. Thus, this is an accurate control, not a regulation.
The advantages of the present invention are not limited thereto.
Drawings
Fig. 1 shows a circuit according to the invention.
Fig. 2 shows a circuit according to the invention without cascode transistors M37, M38.
Detailed Description
Fig. 1 shows a circuit according to the invention.
The description is based on what is claimed from here on.
The invention relates to a driver circuit TR for a data bus, having at its output Out a switching transistor MPO, a first current limiting means M27, M28, M218, M36, M37, M38, M33, MPOrefA second current limiting device M66, M73, MPHclmpA first voltage supply line Vbatt and a reference potential line GND. The switching transistor MPO is set and/or set to a potential for pulling the data bus at the output terminal Out towards the voltage supply line VbatH IN dependence on the input signal IN. First current limiting devices M27, M28, M218, M36, M37, M38, M33, MPOrefR limits the current through the switching transistor MPO. Second current limiting devices M66, M73, MPHclmpR also limits the current through the switching transistor MPO. However, the second current limiting means are mainly arranged for limiting this current in case of a short circuit between the reference potential line GND and the output Out of the drive circuit TR. In order to be able to maintain the regulation, the second current limiting means limit or regulate the current through the switching transistor MPO to a current value different from 0A.
A specific embodiment of the driver circuit TR has at least the following components, which can be replaced individually and/or in groups by functionally equivalent interconnections of the functional elements. This also applies to the nodes. The list of functional elements includes:
-a reference potential line GND;
-a first voltage supply line VbatH;
-an input signal IN;
-a first node K1;
-a second node K2;
-a third node K3;
-a fourth node K4;
-a fifth node K5;
-a sixth node K6;
-a seventh node K7;
-an eighth node K8;
-an eleventh node K11;
-a twelfth node K12;
-a thirteenth node K13;
-a switching transistor MPO;
model transistor MPOref；
-a third transistor M66;
-a fourth transistor M73;
-fifth transistor MPHclmp；
-a sixth transistor M27;
-a seventh transistor M28;
-an eighth transistor M37;
-a thirteenth transistor M38;
-a ninth transistor M394;
a tenth transistor M173;
-an eleventh transistor M395;
a twelfth transistor M184;
a first source follower transistor M128;
-a second source follower transistor M33;
-a first current source M218;
-a second current source M36;
-an output terminal Out;
-a cross-over resistance R;
a first resistance R7V.
The terminals of the functional element are defined below:
the switching transistor MPO has a first terminal, a second terminal, and a control terminal.
Model transistor MPOrefHaving a first terminal, a second terminal and a control terminal.
The third transistor M66 has a first terminal, a second terminal, and a control terminal.
The fourth transistor M73 has a first terminal, a second terminal, and a control terminal.
Fifth transistor MPHclmpHaving a first terminal, a second terminal and a control terminal.
The sixth transistor M27 has a first terminal, a second terminal, and a control terminal.
The seventh transistor M28 has a first terminal, a second terminal, and a control terminal.
The eighth transistor M37 has a first terminal, a second terminal, and a control terminal.
The ninth transistor M394 has a first terminal, a second terminal, and a control terminal.
The tenth transistor M173 has a first terminal, a second terminal, and a control terminal.
The eleventh transistor M395 has a first terminal, a second terminal, and a control terminal.
The twelfth transistor M184 has a first terminal, a second terminal, and a control terminal.
The thirteenth transistor M38 has a first terminal, a second terminal, and a control terminal.
The first source follower transistor M128 has a first terminal, a second terminal, and a control terminal.
The second source follower transistor M33 has a first terminal, a second terminal, and a control terminal.
The first current source M218 has a first terminal and a second terminal.
The second current source M36 has a first terminal and a second terminal.
The cross-over resistor R has a first terminal and a second terminal.
The first resistor R7V has a first terminal and a second terminal.
The connection of the functional elements defined previously and provided with the properties to each other will be explained below. The topology of the circuit shown in fig. 1 is described herein in text. If the functionality described above is retained, a different topology may be used. For example, it is conceivable to provide a lead resistance or the like.
The connection relationships are listed below.
The switching transistor MPO is connected to the first voltage power supply line VbatH through a first terminal thereof.
The switching transistor MPO is connected via its second terminal to the output terminal Out.
The switching transistor MPO is connected to the sixth node K6 through its control terminal.
Model transistor MPOrefIs connected via its first terminal to the first voltage supply line VbatH.
Model transistor MPOrefAnd is connected through its second terminal to the eleventh node K11.
Model transistor MPOrefAnd is connected to the sixth node K6 through its control terminal.
The third transistor M66 is connected to the first voltage power supply line VbatH through a first terminal thereof.
The third transistor M66 is connected to the eighth node K8 through a second terminal thereof.
The third transistor M66 is connected to the fifth node K5 through a control terminal thereof.
The fourth transistor M73 is connected to the eighth node K8 through a first terminal thereof.
The fourth transistor M73 is connected to the sixth node K6 through a second terminal thereof.
The fourth transistor M73 is connected to the sixth node K6 through its control terminal.
Fifth transistor MPHclmpIs connected via its first terminal to the first voltage supply line VbatH.
Fifth transistor MPHclmpAnd is connected through its second terminal to the fifth node K5.
Fifth transistor MPHclmpAnd is connected to the fifth node K5 through its control terminal.
The sixth transistor M27 is connected by its first terminal to the output terminal Out.
The sixth transistor M27 is connected to the seventh node K7 through a second terminal thereof.
The sixth transistor M27 is connected to the seventh node K7 through a control terminal thereof.
The seventh transistor M28 is connected to the eleventh node K11 through a first terminal thereof.
The seventh transistor M28 is connected to the thirteenth node K13 through a second terminal thereof. If the eighth transistor M37 is not used, the second terminal of the seventh transistor M28 is directly connected to the fourth node K4 and is not indirectly connected through the eighth transistor M37.
The seventh transistor M28 is connected to the seventh node K7 through a control terminal thereof.
The eighth transistor M37 is connected to the fourth node K4 through a first terminal thereof.
The eighth transistor M37 is connected to the thirteenth node K13 through a second terminal thereof.
The eighth transistor M37 is connected to the second voltage power supply line VbatL through a control terminal thereof.
The ninth transistor M394 is connected to the second node K2 through a first terminal thereof.
The ninth transistor M394 is connected to the first node K1 through a second terminal thereof.
The ninth transistor M394 is connected to the first node K1 through a control terminal thereof.
The tenth transistor M173 is connected to the reference potential line GND through a first terminal thereof.
The tenth transistor M173 is connected through a second terminal thereof to the second node K2.
The tenth transistor M173 is connected to the second node K2 through a control terminal thereof.
The eleventh transistor M395 is connected to the third node K3 through a first terminal thereof.
The eleventh transistor M395 is connected to the sixth node K6 through a second terminal thereof.
The eleventh transistor M395 is connected to the first node K1 through a control terminal thereof.
The twelfth transistor M184 is connected to the reference potential line GND through a first terminal thereof.
The twelfth transistor M184 is connected through a second terminal thereof to the third node K3.
The twelfth transistor M184 is connected to the second node K2 through a control terminal thereof.
The thirteenth transistor M38 is connected to the twelfth node K12 through a first terminal thereof.
The thirteenth transistor M38 is connected to the seventh node K7 through a second terminal thereof.
The thirteenth transistor M38 is connected to the second voltage power supply line VbatL through a control terminal thereof.
The first source follower transistor M128 is connected to the third node K3 through a first terminal thereof.
The first source follower transistor M128 is connected through a second terminal thereof to the fifth node K5.
The first source follower transistor M128 is connected to the input signal IN through its control terminal.
The second source follower transistor M33 is connected to the third node K3 through a first terminal thereof.
The second source follower transistor M33 is connected through its second terminal to the second voltage supply line VbatL.
The second source follower transistor M33 is connected through its control terminal to the fourth node K4.
A first terminal of the first current source M218 is connected to the twelfth node K12. If the thirteenth transistor M38 is not used, the first terminal of the first current source M218 is directly connected to the seventh node K7 and is not indirectly connected through the thirteenth transistor M38.
A second terminal of the first current source M218 is connected to the reference potential line GND.
A first terminal of the second current source M36 is connected to the fourth node K4.
A second terminal of the second current source M36 is connected to the reference potential line GND.
A first terminal of the cross-over resistor R is connected to the fifth node K5.
A second terminal of the cross-over resistor R is connected to the output terminal Out.
A first terminal of the first resistor R7V is connected to a sixth node K6.
A second terminal of the first resistor R7V is connected to the first voltage supply line VbatH.
The reference current Iref from the exemplary bandgap circuit BG is fed to the first node K1.
Referring to fig. 1, an exemplary bandgap circuit BG is explained below.
The differential amplifier OP is connected to the tenth node K10 through its positive input terminal. The tenth node K10 is held at the reference potential Vref by a reference voltage source. The differential amplifier OP is connected through its output terminal to a control terminal of the third bandgap transistor Q3. The differential amplifier OP is powered by a second voltage supply line VbatL, which is typically at a significantly lower potential than the first voltage supply line VbatH.
A first terminal of the third bandgap transistor Q3 is connected to a ninth node K9. A second terminal of the third bandgap transistor Q3 is connected to a fourteenth node K14.
The conversion resistor RS converts the voltage at the ninth node K9 into a current. Here, a differential amplifier OP and a source follower (a form of a third band gap transistor Q3 adjusts the voltage at the ninth node K9 in accordance with the potential at the tenth node K10 via a fifteenth node K15. therefore, the control terminal of the third band gap transistor Q3 is connected to a fifteenth node K15.
The current mirror composed of the first bandgap transistor Q1 and the second bandgap transistor Q2 reflects the current flowing from the second voltage supply line VbatL into the conversion resistor RS via the first bandgap transistor Q1 as the reference current Iref of the driving circuit TR through the second bandgap transistor Q2.
An equivalent bandgap circuit may be used.
Fig. 2 shows a circuit according to the invention without cascode transistors M37, M38. This corresponds to the requirements.
The reference numerals are explained below.
BG represents a bandgap circuit;
GND denotes a reference potential line;
iref denotes a reference current;
IN represents an input signal;
k1 denotes a first node;
k2 denotes a second node;
k3 denotes a third node;
k4 denotes a fourth node;
k5 denotes a fifth node;
k6 denotes a sixth node;
k7 denotes a seventh node;
k8 denotes an eighth node;
k9 denotes a ninth node;
k10 denotes a tenth node;
k11 denotes an eleventh node;
k12 denotes a twelfth node;
k13 denotes a thirteenth node;
k14 denotes a fourteenth node;
k15 denotes a fifteenth node;
m27 denotes a sixth transistor. The sixth transistor is, for example, a P-channel transistor;
m28 denotes a seventh transistor. The seventh transistor is, for example, a P-channel transistor;
m33 denotes a second source follower transistor, which is, for example, an N-channel transistor;
m36 denotes a second current source;
m37 denotes an eighth transistor. The eighth transistor is, for example, an N-channel transistor;
m38 denotes a thirteenth transistor. The thirteenth transistor is, for example, an N-channel transistor;
m66 denotes a third transistor. The third transistor is, for example, a P-channel transistor;
m73 denotes a fourth transistor. The fourth transistor is, for example, a P-channel transistor;
m128 denotes a first source follower transistor, which is, for example, an N-channel transistor;
m173 denotes a tenth transistor. The tenth transistor is, for example, an N-channel transistor;
m184 denotes a twelfth transistor. The twelfth transistor is, for example, an N-channel transistor;
m218 denotes a first current source;
m394 denotes a ninth transistor. The ninth transistor is, for example, an N-channel transistor;
m395 denotes an eleventh transistor. The eleventh transistor is, for example, an N-channel transistor;
MPHclmpa fifth transistor is shown. The fifth transistor is, for example, a P-channel transistor;
MPO denotes a switching transistor, for example a P-channel field effect transistor for driving the DSI3 data bus at output Out;
MPOrefrepresenting a model transistor. The model transistor is, for example, a P-channel transistor;
OP denotes a differential amplifier;
out denotes the output of the drive circuit TR;
q1 denotes a first transistor of the bandgap circuit BG. The first transistor of the bandgap circuit BG is, for example, a P-channel transistor;
q2 denotes a second transistor of the bandgap circuit BG. The second transistor of the bandgap circuit BG is, for example, a P-channel transistor;
q3 denotes a third transistor of the bandgap circuit BG. The third transistor of the band gap circuit BG is, for example, an N-channel transistor;
r represents a bridge resistor;
R7V represents a first resistance;
RS represents a conversion resistor in the band gap circuit BG;
TR denotes a drive circuit;
VbatH denotes a first voltage supply line of the driving circuit TR for supplying power to the driving circuit TR. The first voltage supply line generally has a significantly increased potential (for example, 30V) with respect to the reference potential of the reference potential line GND, compared with the second voltage supply line VbatL for supplying power to the bandgap circuit BG;
VbatL denotes a second voltage supply line of the driver circuit TR for supplying power to the bandgap circuit BG. The second voltage supply line typically has a significantly reduced potential (e.g., 5V) with respect to the reference potential of the reference potential line GND, compared to the first voltage supply line VbatH for supplying power to the drive circuit TR;
VR represents a potential defined in accordance with the potential of the first voltage power supply line VbatH;
vref denotes a reference voltage.
Claims (3)
1. A driver circuit (TR) for a data bus at an output (Out) thereof, comprising:
a switching transistor (MPO);
first current limiting device (M27, M28, M218, M36, M33, MPO)ref)；
Second current limiting device (M66, M73, MPH)clmp)；
A first voltage supply line (Vbatt); and
a reference potential line (GND),
wherein the switching transistor (MPO) is set and/or arranged to pull the data bus at the output (Out) to a potential of the first voltage supply line (Vbatt) IN dependence on an input signal (IN),
wherein the first current limiting device (M27, M28, M218, M36, M33, MPO)ref) Limiting the current flowing through the switching transistor (MPO), and
wherein said second current limiting means (M66, M73, MPH) in case of a short circuit between said reference potential line (GND) and said output terminal (Out) of said drive circuit (TR)clmp) The current flowing through the switching transistor (MPO) is limited and regulated to a current value different from 0A.
2. A drive circuit, comprising:
a reference potential line (GND);
a first voltage supply line (Vbatt);
a second voltage supply line (Vbatt L);
an input signal (IN);
a first node (K1);
a second node (K2);
a third node (K3);
a fourth node (K4);
a fifth node (K5);
a sixth node (K6);
a seventh node (K7);
an eighth node (K8);
an eleventh node (K11);
a thirteenth node (K13);
a switching transistor (MPO);
model transistor (MPO)ref)；
A third transistor (M66);
a fourth transistor (M73);
fifth transistor (MPH)clmp)；
A sixth transistor (M27);
a seventh transistor (M28);
a ninth transistor (M394);
a tenth transistor (M173);
an eleventh transistor (M395);
a twelfth transistor (M184);
a first source follower transistor (M128);
a second source follower transistor (M33);
a first current source (M218);
a second current source (M36);
an output terminal (Out);
a bridge resistor (R);
a first resistance (R7V);
wherein the switching transistor (MPO) has a first terminal, a second terminal and a control terminal,
wherein the model transistor (MPO)ref) Having a first terminal, a second terminal and a control terminal,
wherein the third transistor (M66) has a first terminal, a second terminal, and a control terminal,
wherein the fourth transistor (M73) has a first terminal, a second terminal, and a control terminal,
wherein the fifth transistor (MPH)clmp) Having a first terminal, a second terminal and a control terminal,
wherein the sixth transistor (M27) has a first terminal, a second terminal, and a control terminal,
wherein the seventh transistor (M28) has a first terminal, a second terminal, and a control terminal,
wherein the ninth transistor (M394) has a first terminal, a second terminal, and a control terminal,
wherein the tenth transistor (M173) has a first terminal, a second terminal, and a control terminal,
wherein the eleventh transistor (M395) has a first terminal, a second terminal, and a control terminal,
wherein the twelfth transistor (M184) has a first terminal, a second terminal, and a control terminal,
wherein the first source follower transistor (M128) has a first terminal, a second terminal, and a control terminal,
wherein the second source follower transistor (M33) has a first terminal, a second terminal, and a control terminal,
wherein the first current source (M218) has a first terminal and a second terminal,
wherein the second current source (M36) has a first terminal and a second terminal,
wherein the cross-over resistance (R) has a first terminal and a second terminal,
wherein the first resistor (R7V) has a first terminal and a second terminal,
wherein a first terminal of the switching transistor (MPO) is connected to the first voltage supply line (Vbatt),
wherein a second terminal of the switching transistor (MPO) is connected to the output (Out),
wherein a control terminal of the switching transistor (MPO) is connected to the sixth node (K6),
wherein the model transistor (MPO)ref) Is connected to the first voltage supply line (VbatH),
wherein the model transistor (MPO)ref) Is connected to the eleventh node (K11),
wherein the model transistor (MPO)ref) Is connected to the sixth node (K6),
wherein a first terminal of the third transistor (M66) is connected to the first voltage supply line (Vbatt),
wherein a second terminal of the third transistor (M66) is connected to the eighth node (K8),
wherein a control terminal of the third transistor (M66) is connected to the fifth node (K5),
wherein a first terminal of the fourth transistor (M73) is connected to the eighth node (K8),
wherein a second terminal of the fourth transistor (M73) is connected to the sixth node (K6),
wherein a control terminal of the fourth transistor (M73) is connected to the sixth node (K6),
wherein the fifth transistor (MPH)clmp) Is connected to the first voltage supply line (VbatH),
wherein the fifth transistor (MPH)clmp) Is connected to the fifth node (K5),
wherein the fifth transistor (MPH)clmp) Is connected to the fifth node (K5),
wherein a first terminal of the sixth transistor (M27) is connected to the output terminal (Out),
wherein a second terminal of the sixth transistor (M27) is connected to the seventh node (K7),
wherein a control terminal of the sixth transistor (M27) is connected to the seventh node (K7),
wherein a first terminal of the seventh transistor (M28) is connected to the eleventh node (K11),
wherein a second terminal of the seventh transistor (M28) is directly or indirectly connected to the fourth node (K4),
wherein a control terminal of the seventh transistor (M28) is connected to the seventh node (K7),
wherein a first terminal of the ninth transistor (M394) is connected to the second node (K2),
wherein a second terminal of the ninth transistor (M394) is connected to the first node (K1),
wherein a control terminal of the ninth transistor (M394) is connected to the first node (K1),
wherein a first terminal of the tenth transistor (M173) is connected to the reference potential line (GND),
wherein a second terminal of the tenth transistor (M173) is connected to the second node (K2),
wherein a control terminal of the tenth transistor (M173) is connected to the second node (K2),
wherein a first terminal of the eleventh transistor (M395) is connected to the third node (K3),
wherein a second terminal of the eleventh transistor (M395) is connected to the sixth node (K6),
wherein a control terminal of the eleventh transistor (M395) is connected to the first node (K1),
wherein a first terminal of the twelfth transistor (M184) is connected to the reference potential line (GND),
wherein a second terminal of the twelfth transistor (M184) is connected to the third node (K3),
wherein a control terminal of the twelfth transistor (M184) is connected to the second node (K2),
wherein a first terminal of the first source follower transistor (M128) is connected to the third node (K3),
wherein a second terminal of the first source follower transistor (M128) is connected to the fifth node (K5),
wherein a control terminal of the first source follower transistor (M128) is connected to the input signal (IN),
wherein a first terminal of the second source follower transistor (M33) is connected to the third node (K3),
wherein a second terminal of the second source follower transistor (M33) is connected to the second voltage supply line (Vbatt L),
wherein a control terminal of the second source follower transistor (M33) is connected to the fourth node (K4),
wherein a first terminal of the first current source (M218) is directly or indirectly connected to the seventh node (K7),
wherein a second terminal of the first current source (M218) is connected to the reference potential line (GND),
wherein a first terminal of the second current source (M36) is connected to the fourth node (K4),
wherein a second terminal of the second current source (M36) is connected to the reference potential line (GND),
wherein a first terminal of the flying resistor (R) is connected to the fifth node (K5),
wherein a second terminal of the cross-over resistance (R) is connected to the output terminal (Out),
wherein a first terminal of the first resistor (R7V) is connected to the sixth node (K6),
wherein a second terminal of the first resistor (R7V) is connected to the first voltage supply line (Vbatt H), and
wherein a reference current (Iref) is fed to the first node (K1).
3. The drive circuit according to claim 2, wherein,
wherein the first current limiting means comprises the sixth transistor (M27), the seventh transistor (M28), the first current source (M218), the second current source (M36), the second source follower transistor (M33) and the model transistor (MPO)ref)，
Wherein the second current limiting means comprises the third transistor (M66), the fourth transistor (M73), the fifth transistor (MPH)clmp) And the bridge resistor (R),
wherein the switching transistor (MPO) is set and/or arranged to pull the data bus at the output (Out) to a potential of the first voltage supply line (Vbatt) IN dependence on the input signal (IN),
wherein the first current limiting device (M27, M28, M218, M36, M33, MPO)ref) Limiting the current flowing through the switching transistor (MPO), and
wherein said second current limiting means (M66, M73, MPH) in case of a short circuit between said reference potential line (GND) and said output terminal (Out) of said drive circuit (TR)clmp) The current flowing through the switching transistor (MPO) is limited and regulated to a current value different from 0A.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102019119603.5 | 2019-07-19 | ||
| DE102019119603.5A DE102019119603B4 (en) | 2019-07-19 | 2019-07-19 | Short-circuit proof driver circuit for a DSI3 data bus with double current limitation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112242837A true CN112242837A (en) | 2021-01-19 |
Family
ID=74093249
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010503957.3A Pending CN112242837A (en) | 2019-07-19 | 2020-06-05 | DSI3 data bus short-circuit prevention driving circuit with double current limitation |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN112242837A (en) |
| DE (1) | DE102019119603B4 (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10110140C1 (en) * | 2001-03-02 | 2003-02-06 | Infineon Technologies Ag | Overload protection circuit for line drivers |
| DE10251473B3 (en) * | 2002-11-05 | 2004-06-17 | Siemens Ag | Protection circuit for protection against overvoltage for a CAN bus transceiver |
| DE102017111544B4 (en) * | 2017-05-26 | 2020-06-25 | Elmos Semiconductor Aktiengesellschaft | Combined PSI5 / DSI3 data interface for a mixed installation of sensors with PSI5 and PSI3 data bus interface in sensor systems |
-
2019
- 2019-07-19 DE DE102019119603.5A patent/DE102019119603B4/en active Active
-
2020
- 2020-06-05 CN CN202010503957.3A patent/CN112242837A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| DE102019119603A1 (en) | 2021-01-21 |
| DE102019119603B4 (en) | 2022-05-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7602162B2 (en) | Voltage regulator with over-current protection | |
| US7339775B2 (en) | Overcurrent protection circuit and DC power supply | |
| US7466115B2 (en) | Soft-start circuit and method for power-up of an amplifier circuit | |
| CN101341453B (en) | Constant voltage circuit and method of controlling output voltage of constant voltage circuit | |
| KR101632327B1 (en) | Low drop out(ldo) bypass voltage regulator | |
| US20070057660A1 (en) | Low-dropout voltage regulator | |
| CN113765508B (en) | High voltage gate drive current source | |
| US20170155315A1 (en) | Power Regulator | |
| US7928708B2 (en) | Constant-voltage power circuit | |
| US10571941B2 (en) | Voltage regulator | |
| US11106229B2 (en) | Semiconductor integrated circuit including a regulator circuit | |
| US8570098B2 (en) | Voltage reducing circuit | |
| US20100207591A1 (en) | Voltage regulator | |
| TW201935168A (en) | Overcurrent limiting circuit, overcurrent limiting method, and power supply circuit | |
| US8471548B2 (en) | Power supply circuit configured to supply stabilized output voltage by avoiding offset voltage in error amplifier | |
| US20080136384A1 (en) | Capacitor-free linear voltage regulator for integrated controller area network transceivers | |
| CN112242837A (en) | DSI3 data bus short-circuit prevention driving circuit with double current limitation | |
| US10423188B1 (en) | Voltage generating circuit for improving stability of bandgap voltage generator | |
| US20220244770A1 (en) | Usb power delivery interface | |
| US20210041486A1 (en) | Apparatus and system for wide-range current sensing | |
| JP2012211600A (en) | Positioner | |
| JP2011248467A (en) | Hot-line insertion/exertion control circuit | |
| US20100060249A1 (en) | Current-restriction circuit and driving method therefor | |
| TWI825604B (en) | Power sourcing equipment and power supply control method | |
| CN114089799B (en) | Low-dropout voltage regulator and control method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |