CN112234094B - 金属氧化物半导体器件及其制造方法 - Google Patents
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Abstract
本发明提供了一种金属氧化物半导体器件及其制造方法,所述器件包括:基底;从所述基底的上表面延伸至其内的具有第一掺杂类型的源区;位于所述基底上表面的栅极结构,所述栅极结构至少裸露所述源区,以及位于所述基底上表面的具有第一掺杂类型的半导体层,所述半导体层被作为所述器件的部分耐压区,其中,所述源区位于所述栅极结构的第一侧,所述半导体层位于所述栅极结构的第二侧,所述栅极结构的第一侧和第二侧相对。本发明的金属氧化物半导体器件及其制造方法不仅减小了器件尺寸,且制造工艺简单,与CMOS工艺兼容。
Description
技术领域
本发明涉及半导体技术领域,更具体地,涉及一种金属氧化物半导体器件及其一种金属氧化物半导体器件的制造方法。
背景技术
目前两种主流的功率MOSFET分别为LDMOS器件和沟槽MOS器件。在高压功率集成电路中,常采用高压LDMOS器件满足耐高压、实现功率控制等方面的要求。但为了满足高耐压,LDMOS器件的漂移区长度一般都设置的比较长,这样不仅增大了器件的导通电阻,还增大了器件的尺寸。而沟槽MOS器件可以减小器件的尺寸,但其工艺比较复杂且与CMOS工艺不兼容。
发明内容
有鉴于此,本发明的目的在于提供一种金属氧化物半导体器件及其制造方法,以解决上述问题。
根据本发明的第一方面,提供一种金属氧化物半导体器件,包括:基底;从所述基底的上表面延伸至其内的具有第一掺杂类型的源区;位于所述基底上表面的栅极结构,所述栅极结构至少裸露所述源区,以及位于所述基底上表面的具有第一掺杂类型的半导体层,所述半导体层被作为所述器件的部分耐压区,其中,所述源区位于所述栅极结构的第一侧,所述半导体层位于所述栅极结构的第二侧,所述栅极结构的第一侧和第二侧相对。
优选地,还包括从所述基底的上表面延伸至其内的具有第二掺杂类型的体区,所述源区位于所述体区中,所述栅极结构至少覆盖部分所述体区。
优选地,在所述基底中,至少同时与所述基底的上表面,所述体区和所述半导体层接触的区域具有第一掺杂类型。
优选地,所述半导体层被作为所述金属氧化物半导体器件的漏区。
优选地,还包括第一掺杂类型的漂移区。
优选地,所述漂移区与所述半导体层接触,所述漂移区位于所述基底中。
优选地,当所述基底为第二掺杂类型时,所述体区与所述接触区接触。
优选地,所述基底包括所述漂移区,所述体区位于所述漂移区中。
优选地,所述半导体层和所述栅极结构之间通过隔离层隔离。
优选地,所述半导体层和所述栅极结构之间通过高温氧化形成的氧化层隔离。
优选地,根据所述器件的耐压要求,调节所述半导体层沿所述器件垂直方向的厚度。
优选地,所述器件的耐压要求越高,设置所述半导体层沿所述器件垂直方向的厚度越大。
优选地,根据所述器件的耐压要求,调节所述隔离层沿所述器件横向方向的宽度。
优选地,所述器件的耐压要求越高,设置所述隔离层沿所述器件横向方向的宽度越大。
优选地,还包括覆盖所述基底上表面以及所述栅极结构上表面的层间介质,所述隔离层与所述层间介质和所述栅极结构接触。
优选地,所述半导体层被设置为多晶硅。
优选地,所述半导体层被设置为外延硅。
根据本发明的第二方面,提供一种金属氧化物半导体器件的制造方法,包括:提供一基底,形成从所述基底的上表面延伸至其内的具有第一掺杂类型的源区;形成位于所述基底的上表面的栅极结构,所述栅极结构至少裸露所述源区,以及形成位于所述基底的上表面的具有第一掺杂类型的半导体层,所述半导体层被作为所述器件的部分耐压区,其中,所述源区位于所述栅极结构的第一侧,所述半导体层位于所述栅极结构的第二侧,所述栅极结构的第一侧和第二侧相对。
优选地,在所述基底中,至少同时与所述基底的上表面,所述体区和所述半导体层接触的区域具有第一掺杂类型。
优选地,还包括形成从所述基底的上表面延伸至其内的具有第二掺杂类型的体区,所述源区位于所述体区中,所述栅极结构至少覆盖部分所述体区。
优选地,还包括形成覆盖所述基底上表面以及所述栅极结构上表面的层间介质,所述层间介质具有裸露所述栅极结构第二侧的所述基底的上表面的通孔。
优选地,形成所述半导体层的方法包括:在所述通孔中沉积多晶硅;以及采用化学机械抛光工艺去除多余的多晶硅使得多晶硅的上表面与所述层间介质的上表面齐平,以形成所述半导体层。
优选地,在所述通孔中通过外延工艺生长硅以形成所述半导体层。
优选地,在形成所述半导体层之前,还包括在所述通孔中形成覆盖所述层间介质和所述栅极结构侧壁的隔离层,所述隔离层将所述半导体层和所述栅极结构隔离。
优选地,形成所述隔离层的方法包括:在所述通孔中沉积绝缘层,以及采用各向异性的刻蚀工艺刻蚀所述绝缘层以形成覆盖所述层间介质和所述栅极结构侧壁的隔离层。
优选地,所述隔离层被设置为高温氧化层。
优选地,形成所述栅极结构和所述层间介质的方法包括:在所述基底的上表面形成栅氧化层,在所述栅氧化层上形成栅极导体,所述栅极导体至少裸露所述源区的上表面;形成覆盖所述基底的上表面和所述栅极导体上表面的介质层;刻蚀部分所述介质层,所述栅氧化层和所述栅极导体以形成所述层间介质和所述栅极结构,所述栅极结构包括所述栅氧化层和栅极导体。
优选地,其中,还包括形成第一掺杂类型的漂移区。
优选地,其中,所述漂移区与所述半导体层接触,所述漂移区形成在所述基底中。
优选地,所述基底包括所述漂移区,所述体区形成在所述漂移区中。
根据本发明提供的金属氧化物半导体器件及其制造方法,所述器件通过在基底上表面形成半导体层以作为器件的部分耐压区,替代漂移区承受部分高压,则可以减小漂移区的长度,进而减小器件的尺寸和器件的导通电阻。另外,因为所述半导体层位于基底的上表面,其与层间介质的高度相同,并未增加额外的面积。
本发明提供的金属氧化物半导体器件及其制造方法,相对于现有的 LDMOS,其减小了器件的尺寸和器件的导通电阻,其他性能与LDMOS 接近;相对于现有的沟槽MOS,其工艺简单,且与CMOS工艺兼容。
附图说明
通过以下参照附图对本发明实施例的描述,本发明的上述以及其他目的、特征和优点将更为清楚,在附图中:
图1示出根据本发明的第一实施例的金属氧化物半导体器件;
图2示出根据本发明的第二实施例的金属氧化物半导体器件;
图3a-3d示出根据本发明的实施例的制造金属氧化物半导体器件的方法的各个阶段的截面图。
具体实施方式
以下将参照附图更详细地描述本发明。在各个附图中,相同的元件采用类似的附图标记来表示。为了清楚起见,附图中的各个部分没有按比例绘制。此外,可能未示出某些公知的部分。为了简明起见,可以在一幅图中描述经过数个步骤后获得的半导体结构。
应当理解,在描述器件的结构时,当将一层、一个区域称为位于另一层、另一个区域“上面”或“上方”时,可以指直接位于另一层、另一个区域上面,或者在其与另一层、另一个区域之间还包含其它的层或区域。并且,如果将器件翻转,该一层、一个区域将位于另一层、另一个区域“下面”或“下方”。
如果为了描述直接位于另一层、另一个区域上面的情形,本文将采用“A直接在B上面”或“A在B上面并与之邻接”的表述方式。在本申请中,“A直接位于B中”表示A位于B中,并且A与B直接邻接,而非A位于B中形成的掺杂区中。
在本申请中,术语“冲丝”是指在引线框上固定晶片以及进行引线键合之后,在注入封装料的过程中,彼此相邻的引线由于封装料的冲击而彼此接触导致短路的现象。
在下文中描述了本发明的许多特定的细节,例如器件的结构、材料、尺寸、处理工艺和技术,以便更清楚地理解本发明。但正如本领域的技术人员能够理解的那样,可以不按照这些特定的细节来实现本发明。
本发明公开了一种金属氧化物半导体器件,包括:基底;从所述基底的上表面延伸至其内的具有第一掺杂类型的源区;位于所述基底上表面的栅极结构,所述栅极结构至少裸露所述源区,以及位于所述基底上表面的具有第一掺杂类型的半导体层,所述半导体层被作为所述器件的部分耐压区,其中,所述源区位于所述栅极结构的第一侧,所述半导体层位于所述栅极结构的第二侧,所述栅极结构的第一侧和第二侧相对。所述器件还包括从所述基底的上表面延伸至其内的具有第二掺杂类型的体区,所述源区位于所述体区中,所述栅极结构至少覆盖部分所述体区。在所述基底中,至少同时与所述基底的上表面,所述体区和所述半导体层接触的区域具有第一掺杂类型。
如图1示出根据本发明的第一实施例的金属氧化物半导体器件。
如图1所示,所述金属氧化物半导体器件包括基底101,源区104,栅极结构,以及半导体层109。所述源区104从所述基底101的上表面延伸至其内,所述源区104具有第一掺杂类型;所述栅极结构位于所述基底101的上表面,所述栅极结构至少裸露所述源区104,所述栅极结构包括栅氧化层105和栅极导体106;所述半导体层109具有第一掺杂类型,并位于所述基底101的上表面上。其中,所述源区104位于所述栅极结构的第一侧,所述半导体层109位于所述栅极结构的第二侧,所述栅极结构的第一侧和第二侧相对。在本实施例中,所述基区101被设置为第二掺杂类型。所述半导体层109位于所述基底的上表面,被作为所述金属氧化物半导体器件的漏区,同时作为所述器件的部分耐压区。所述第一掺杂类型为N型或P型中的一种,所述第二掺杂类型为N型或 P型中的另一种。
所述器件还包括位于所述基底101中的具有第一掺杂类型的漂移区 103,所述漂移区103与所述半导体层109接触,所述漂移区103从所述半导体层109处延伸至栅极结构的部分下方,所述漂移区103与所述源区104之间隔开一段距离以作为所述器件的沟道区域。
优选地,所述器件还包括位于从所述基底101的上表面延伸至其内的具有第一掺杂类型的体区102,其中,所述源区104位于所述体区102 中。所述栅极结构至少覆盖部分所述体区102,位于所述栅极结构下方的部分体区为所述器件的沟道区域。所述漂移区103和体区102接触。
在另一实施例中,在所述基底中还可以设置第一掺杂类型的掺杂区,所述体区,所述源区和所述漂移区都位于所述掺杂区中,其中,所述漂移区103可以与所述体区102不接触。
在另一实施例中,如图2所示,所述基底被设置为第一掺杂类型的漂移区201,所述体区102和所述源区104位于所述漂移区201中。进一步地,所述器件还包括位于所述基底201(漂移区)下的衬底200。
需要注意的是,所述基底中的结构并不限于上述几种结构,本领域的技术人员可根据器件要求具体设置。
所述器件还包括覆盖所述基底101上表面和所述栅极结构上表面的层间介质107,以及用于隔离所述栅极结构和所述半导体层109的隔离层108。在本实施中,所述层间介质107,所述隔离层108以及所述半导体层109的上表面齐平。
另外,所述器件还可以包括位于所述基底101上表面并与所述栅氧化层接触的场氧层,所述漂移区103延伸至所述场氧层的下方,所述栅极导体还可延伸至所述场氧上面充当场板,以提高器件的击穿电压。
根据本发明提供的金属氧化物半导体器件,当器件承受高压时,耗尽层会从漂移区103延伸至半导体层109中,使得漂移区103和半导体层109作为高阻区来承受高压。因此可以根据器件的耐压要求,设置所述半导体层109沿所述器件垂直方向的厚度,所述器件的耐压越高,设置所述半导体层109沿所述器件垂直方向的厚度越厚。本发明中的所述半导体层109作为器件的部分耐压区,替代漂移区103承受部分高压,则可以减小漂移区103的长度,进而可以减小器件的尺寸和器件的导通电阻。另外,半导体层109位于基底的上表面,其与层间介质的高度相同,并需要根据不同电压要求,改变层间介质高度。
需要注意的是,由于半导体层109承受的电压比较高,而栅极结构上的电压一般较低,因此需要用隔离层108隔离所述半导体层109和栅极结构。可以根据器件的耐压要求,设置所述隔离层108的质量和宽度,以防止其被击穿。在本实施例中,所述隔离层108可以优选为高温氧化层(HTO),当然,本领域的技术人员也可采用其他隔离层,在此不做限制。所述器件的耐压要求越高,设置所述隔离层108沿所述器件横向方向的宽度越大。
本发明提供的金属氧化物半导体器件,相对于现有的LDMOS,其减小了器件的尺寸和器件的导通电阻,其他性能与LDMOS接近;相对于现有的沟槽MOS,其工艺简单,且与CMOS工艺兼容。
本发明还提供了一种形成金属氧化物半导体器件的方法,包括:提供一基底,形成从所述基底的上表面延伸至其内的具有第一掺杂类型的源区;形成位于所述基底的上表面的栅极结构,所述栅极结构至少裸露所述源区,以及形成位于所述基底的上表面的具有第一掺杂类型的半导体层,所述半导体层被作为所述器件的部分耐压区,其中,所述源区位于所述栅极结构的第一侧,所述半导体层位于所述栅极结构的第二侧,所述栅极结构的第一侧和第二侧相对。
图3a-3d示出根据本发明的实施例的制造金属氧化物半导体器件的方法的各个阶段的截面图。具体的步骤如下:
如图3a所示,提供一基底301,所述基底301为第二掺杂类型;形成从所述基底301的上表面延伸至其内的具有第二掺杂类型的体区302;形成从所述基底301的上表面延伸至其内的具有第一掺杂类型的源区 304,所述源区304位于所述体区302中;以及形成从所述基底301的上表面延伸至其内的具有第一掺杂类型的漂移区303。其中,所述漂移区 303和所述体区302接触。
在另一实施例中,在所述基底301中还可以形成第一掺杂类型的掺杂区,所述体区302,所述源区304和所述漂移区303都形成在所述掺杂区中,其中,所述漂移区303可以与所述体区302不接触。
在另一实施例中,还可以设置所述基底301为第一掺杂类型的漂移区,在所述基底301(漂移区)中形成具有第二掺杂类型的体区302和具有第一掺杂类型的源区304。进一步地,所述基底301的底面还包括一衬底。
需要注意的是,所述基底中的结构并不限于上述三种结构,本领域的技术人员可根据器件要求具体设置。
在所述基底301的上表面形成栅氧化层305,在所述栅氧化层305 的上形成栅极导体306,以及形成覆盖所述栅氧化层305和所述栅极导体306的层间介质307。其中,所述栅极导体至少覆盖部分所述体区302,裸露所述源区304。在其他实施例中,所述栅氧化层305也可被刻蚀与所述栅极导体的侧壁对齐,裸露所述源区304,然后所述层间介质307 覆盖所述基底的上表面以及所述栅极导体的上表面。
如图3b所示,刻蚀所述层间介质307和所述栅氧化层305和栅极导体306以形成通孔,所述通孔暴露所述栅极结构第二侧的所述基底的上表面,即所述漂移区303的部分表面。在本实施例中,被刻蚀后的所述栅氧化层305和栅极导体306组成所述栅极结构。在其他实施例中,也可以在形成所述栅氧化层305和栅极导体306之后,直接将其刻蚀形成至少暴露源区和通孔的栅极结构,然后形成覆盖所述基底上表面和栅极结构的层间介质,并刻蚀所述层间介质以形成所述通孔。当然,所述栅极结构和所述层间介质的形成方法和步骤顺序并不限于此。
如图3c所示,在所述通孔中形成与所述层间介质307和所述栅极结构接触的隔离层308。所述隔离层308用于隔离所述栅极结构和后续工艺形成的半导体层。具体地,在所述通孔中沉积绝缘层,以及采用各向异性的刻蚀工艺刻蚀所述绝缘层以形成覆盖所述层间介质和所述栅极结构侧壁的隔离层308。所述隔离层308优选为高温工艺形成的氧化层 (HTO,high-temperature oxidation)。
如图3d所示,在所述通孔中填充半导体层309。所述半导体层309 优选为多晶硅。具体地,形成所述半导体层309的方法包括:在所述通孔中沉积多晶硅;以及采用化学机械抛光工艺去除多余的多晶硅使得多晶硅的上表面与所述层间介质的上表面齐平,以形成所述半导体层309。可选地,所述半导体层也可通过在所述通孔中采用外延工艺生长硅的方法形成。
应当说明的是,在本文中,诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来,而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且,术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含,从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素,而且还包括没有明确列出的其他要素,或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下,由语句“包括一个……”限定的要素,并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
依照本发明实施例如上文所述,这些实施例并没有详尽叙述所有的细节,也不限制该发明仅为所述的具体实施例。显然,根据以上描述,可作很多的修改和变化。本说明书选取并具体描述这些实施例,是为了更好地解释本发明的原理和实际应用,从而使所属技术领域技术人员能很好地利用本发明以及在本发明基础上的修改使用。本发明仅受权利要求书及其全部范围和等效物的限制。
Claims (31)
1.一种金属氧化物半导体器件,包括:
基底;
从所述基底的上表面延伸至其内的具有第一掺杂类型的源区;
位于所述基底上表面的栅极结构,所述栅极结构至少裸露所述源区,以及
位于所述基底上表面的具有第一掺杂类型的半导体层,所述半导体层被作为所述器件的部分耐压区,
其中,所述半导体层与所述半导体器件的漂移区接触,所述漂移区位于所述基底中;
所述源区位于所述栅极结构的第一侧,所述半导体层位于所述栅极结构的第二侧,所述栅极结构的第一侧和第二侧相对;
所述半导体层和所述栅极结构之间隔离设置。
2.根据权利要求1所述的器件,其中,还包括从所述基底的上表面延伸至其内的具有第二掺杂类型的体区,所述源区位于所述体区中,所述栅极结构至少覆盖部分所述体区。
3.根据权利要求2所述的器件,其中,在所述基底中,至少同时与所述基底的上表面,所述体区和所述半导体层接触的区域具有第一掺杂类型。
4.根据权利要求1所述的器件,其中,所述半导体层被作为所述金属氧化物半导体器件的漏区。
5.根据权利要求2所述的器件,其中,所述漂移区被配置为第一掺杂类型。
6.根据权利要求5所述的器件,其中,当所述基底为第一掺杂类型时,所述基底被配置为所述漂移区,所述体区位于所述漂移区中。
7.根据权利要求6所述的器件,其中,还包括衬底,所述衬底位于所述基底的下表面。
8.根据权利要求2所述的器件,其中,当所述基底为第二掺杂类型时,所述漂移区位于所述基底中,所述体区与所述漂移区接触。
9.根据权利要求2所述的器件,其中,还包括第一掺杂类型的掺杂区,所述体区,所述源区和所述漂移区均位于所述掺杂区中,所述漂移区与所述体区不接触。
10.根据权利要求1所述的器件,其中,所述半导体层和所述栅极结构之间通过隔离层隔离。
11.根据权利要求1所述的器件,其中,所述半导体层和所述栅极结构之间通过高温氧化形成的氧化层隔离。
12.根据权利要求1所述的器件,其中,根据所述器件的耐压要求,调节所述半导体层沿所述器件垂直方向的厚度。
13.根据权利要求12所述的器件,其中,所述器件的耐压要求越高,设置所述半导体层沿所述器件垂直方向的厚度越大。
14.根据权利要求10所述的器件,其中,根据所述器件的耐压要求,调节所述隔离层沿所述器件横向方向的宽度。
15.根据权利要求14所述的器件,其中,所述器件的耐压要求越高,设置所述隔离层沿所述器件横向方向的宽度越大。
16.根据权利要求10所述的器件,其中,还包括覆盖所述基底上表面以及所述栅极结构上表面的层间介质,所述隔离层与所述层间介质和所述栅极结构接触。
17.根据权利要求1所述的器件,其中,所述半导体层被设置为多晶硅。
18.根据权利要求1所述的器件,其中,所述半导体层被设置为外延硅。
19.一种金属氧化物半导体器件的制造方法,包括:
提供一基底,
形成从所述基底的上表面延伸至其内的具有第一掺杂类型的源区;
形成位于所述基底的上表面的栅极结构,所述栅极结构至少裸露所述源区,以及
形成位于所述基底的上表面的具有第一掺杂类型的半导体层,所述半导体层被作为所述器件的部分耐压区,
其中,所述半导体层与所述半导体器件的漂移区接触,所述漂移区位于所述基底中;
所述源区位于所述栅极结构的第一侧,所述半导体层位于所述栅极结构的第二侧,所述栅极结构的第一侧和第二侧相对;
所述半导体层和所述栅极结构之间隔离设置。
20.根据权利要求19所述的方法,其中,还包括形成从所述基底的上表面延伸至其内的具有第二掺杂类型的体区,所述源区位于所述体区中,所述栅极结构至少覆盖部分所述体区。
21.根据权利要求20所述的方法,其中,在所述基底中,至少同时与所述基底的上表面,所述体区和所述半导体层接触的区域具有第一掺杂类型。
22.根据权利要求19所述的方法,其中,还包括形成覆盖所述基底上表面以及所述栅极结构上表面的层间介质,所述层间介质具有裸露所述栅极结构第二侧的所述基底的上表面的通孔。
23.根据权利要求22所述的方法,其中,形成所述半导体层的方法包括:
在所述通孔中沉积多晶硅;以及
采用化学机械抛光工艺去除多余的多晶硅使得多晶硅的上表面与所述层间介质的上表面齐平,以形成所述半导体层。
24.根据权利要求22所述的方法,其中,在所述通孔中通过外延工艺生长硅以形成所述半导体层。
25.根据权利要求22所述的方法,其中,在形成所述半导体层之前,还包括在所述通孔中形成覆盖所述层间介质和所述栅极结构侧壁的隔离层,所述隔离层将所述半导体层和所述栅极结构隔离。
26.根据权利要求25所述的方法,其中,形成所述隔离层的方法包括:
在所述通孔中沉积绝缘层,以及
采用各向异性的刻蚀工艺刻蚀所述绝缘层以形成覆盖所述层间介质和所述栅极结构侧壁的隔离层。
27.根据权利要求25所述的方法,其中,所述隔离层被设置为高温氧化层。
28.根据权利要求22所述的方法,其中,形成所述栅极结构和所述层间介质的方法包括:
在所述基底的上表面形成栅氧化层,
在所述栅氧化层上形成栅极导体,所述栅极导体至少裸露所述源区的上表面;
形成覆盖所述基底的上表面和所述栅极导体上表面的介质层;
刻蚀部分所述介质层,所述栅氧化层和所述栅极导体以形成所述层间介质和所述栅极结构,所述栅极结构包括所述栅氧化层和栅极导体。
29.根据权利要求21所述的方法,其中,还包括在所述基底中,形成第一掺杂类型的漂移区,所述漂移区与所述半导体层接触。
30.根据权利要求21所述的方法,其中,所述基底被配置为第一掺杂类型,并被配置为所述漂移区,所述体区形成在所述漂移区中。
31.根据权利要求28所述的方法,其中,还包括,在所述基底下方形成衬底。
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