CN112230880B - Data transmission control method and device, FPGA and medium - Google Patents
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Abstract
The application discloses a data transmission control method, a device, an FPGA and a medium, wherein the method comprises the following steps: transmitting a data frame to a second kernel of the receiving end FPGA; receiving an ACK response frame sent by the second kernel; and controlling the data flow of a local data transmission port according to the receiving credit use field, the frame response sequence number, the residual space size of the buffer memory of the receiving end and the locally stored transmitting credit consumption data in the ACK response frame, wherein the transmitting credit consumption data represents the data quantity transmitted to the second kernel by the first kernel. Therefore, the data transmission of the sending end can be automatically controlled according to the condition of the receiving end, the bandwidth can be fully utilized, and the data loss is avoided.
Description
Technical Field
The application relates to the technical field of Field Programmable Gate Array (FPGA), in particular to a data transmission control method, a data transmission control device, an FPGA and a medium.
Background
With the vigorous development of technologies such as big data, internet of things, mobile interconnection, cloud computing and the like, a large amount of data needs to be processed and analyzed in real time with high efficiency, and as analysis, processing and the like of the data occupy a large amount of server resources, the heterogeneous acceleration platform becomes a main selection direction, so that related data calculation can be unloaded to the heterogeneous acceleration platform for processing. With the rapid development of FPGA (Field Programmable Gate Array field programmable gate array) devices, a new implementation way is provided for the application of a heterogeneous acceleration platform.
By utilizing the parallel and low-delay characteristics of the FPGA, a large amount of data to be calculated can be unloaded from the CPU to the kernel of the FPGA for calculation, and the data to be calculated can be distributed to the kernel of each FPGA for calculation in a distributed network. In the data transmission process, if there is no flow control, the interconnected FPGA kernel may cause data loss or extremely large memory consumption, and may also consume the overall processing bandwidth. Therefore, in the data transmission process of realizing multipath kernel interconnection, the flow control can ensure that the data flow cannot cause serious congestion, and the reliable transmission mechanism can ensure the correctness of the data.
As shown in fig. 1, the existing data flow control method is to implement static current limiting similar to a speed limiter at a transmitting end, and after the data volume is transmitted from the transmitting end, the data volume is transmitted to the speed limiter to perform rate control, and after the data transmission rate is adjusted, the data volume is transmitted to a receiving end. For example, the rate of the sending end is 2MB/s, but after the current limiting of the speed limiter, the rate of the Buffer (Buffer) sent to the sending end can be reduced to 1MB/s, so that the data is transmitted in the network and the data received by the receiving end are all transmitted at 1MB/s, and the rate of the sending end and the rate of the receiving end are matched, so that the data can be stably transmitted.
The inventor finds that the following technical problems may exist in the prior art, and because the receiving end does not know the maximum speed which can be born, the speed of the speed limiter needs to be manually modified according to the situation at any time, and the receiving end may dynamically fluctuate at any time, so that the receiving end cannot be adjusted in time, and the condition of negligence of flow exists, so that the bandwidth cannot be fully utilized. If the sending rate of the sending end is too large, the data received by the receiving end is lost, and if the sending rate of the sending end is too small, the waste of bandwidth use is caused.
Disclosure of Invention
In view of the above, an object of the present application is to provide a data transmission control method, apparatus, FPGA, and medium, which can automatically control data transmission of a transmitting end according to a receiving end, and can fully utilize bandwidth without causing data loss. The specific scheme is as follows:
in a first aspect, the present application discloses a data transmission control method, applied to a first kernel of a sender FPGA, including:
transmitting a data frame to a second kernel of a receiving end FPGA, wherein the data frame comprises a frame request sequence number, and the frame request sequence number represents the number of data frames transmitted to the second kernel by the first kernel;
Receiving an ACK response frame sent by the second kernel, wherein the ACK response frame comprises a receiving credit use field, a frame response sequence number and a receiving end buffer residual space size, the receiving credit use field represents the data quantity sent by the first kernel and received by the second kernel, and the frame response sequence number represents the data frame quantity sent by the first kernel and received by the second kernel;
and controlling the data flow of a local data transmission port according to the receiving credit use field, the frame response sequence number, the residual space size of the receiving end buffer memory and the locally stored transmitting credit consumption data, wherein the transmitting credit consumption data represents the data quantity transmitted to the second kernel by the first kernel.
Optionally, the sending the data frame to the second kernel of the receiving end FPGA includes:
adding 1 to the locally stored frame request sequence number to obtain a current frame request sequence number, and adding the current frame request sequence number to a data frame to be transmitted;
accumulating the number of data bytes in the data frame to be transmitted to the transmission credit consumption data;
and sending the data frame to be sent to a second kernel of a receiving end FPGA, so that after the second kernel receives the data frame, comparing a current frame request sequence number in the data frame with a locally stored expected frame sequence number, adding 1 to a frame response sequence number in the second kernel when the current frame request sequence number is consistent with the locally stored expected frame sequence number, and accumulating the number of bytes received by using data of the receiving credit in the second kernel, wherein the expected frame sequence number represents the frame request sequence number which the second kernel is expected to currently receive.
Optionally, the receiving the ACK response frame sent by the second kernel includes:
receiving an ACK response frame sent by the second kernel after caching data corresponding to the data frame to be sent to a receiving end;
and/or receiving an ACK response frame sent by the second kernel according to a preset time interval.
Optionally, the controlling the data flow of the local data sending port according to the receiving credit using field, the frame response sequence number, the remaining space size of the buffer memory of the receiving end and the locally stored sending credit consumption data includes:
comparing the received credit usage data in the received credit usage field with locally stored transmitted credit consumption data;
and if the receiving credit use data in the receiving credit use field is smaller than the locally stored sending credit consumption data, controlling the data flow of the local data sending port according to the frame response sequence number and the size of the residual buffer space of the receiving end.
Optionally, the controlling the data flow of the local data sending port according to the frame response sequence number and the size of the remaining buffer space of the receiving end includes:
Determining a target data frame which is sent by the first kernel and is not received in the second kernel according to the frame response sequence number and the size of the residual buffer space of the receiving end;
and re-sending the target data frame to the second kernel.
Optionally, the determining, according to the frame response sequence number and the size of the remaining buffer space of the receiving end, the target data frame that is sent by the first kernel and not received by the second kernel includes:
determining a first target data frame which is sent by the first kernel and is not received in the second kernel according to the frame response sequence number;
judging whether the size of the residual buffer space of the receiving end is smaller than or equal to a preset buffer space size threshold value;
and if the size of the residual buffer space of the receiving end is smaller than or equal to a preset buffer space size threshold value, determining a second target data frame with the data quantity equal to the size of the residual buffer space of the receiving end from the first target data frame.
Optionally, the determining, according to the frame response sequence number, the first target data frame that is sent by the first kernel and is not received in the second kernel includes:
reading a first pointer value from a preset RAM by taking the frame response serial number as an address, wherein the pointer value of data corresponding to each frame request serial number is stored in the preset RAM by taking the frame request serial number as the address;
Comparing the first pointer value with a second pointer value of a preset FIFO;
and if the first pointer value is inconsistent with the current second pointer value of a preset FIFO, taking the data from the data corresponding to the first pointer value to the data corresponding to the second pointer value in the preset FIFO as a first target data frame, wherein the preset FIFO is used for storing the data sent to the second kernel by the first kernel.
In a second aspect, the present application discloses a data transmission control device, applied to a first kernel of a sender FPGA, including:
the data frame sending module is used for sending data frames to a second kernel of the receiving end FPGA, wherein the data frames comprise frame request sequence numbers, and the frame request sequence numbers represent the number of the data frames sent to the second kernel by the first kernel;
an ACK response frame receiving module, configured to receive an ACK response frame sent by the second kernel, where the ACK response frame includes a receiving credit usage field, a frame response sequence number, and a size of a remaining space of a buffer of a receiving end, where the receiving credit usage field indicates a data amount sent by the first kernel and received by the second kernel, and the frame response sequence number is used to indicate a data frame amount sent by the first kernel and received by the second kernel;
And the flow control module is used for controlling the data flow of a local data transmission port according to the receiving credit use field, the frame response sequence number, the residual space size of the buffer memory of the receiving end and the locally stored transmitting credit consumption data, wherein the transmitting credit consumption data represents the data quantity transmitted to the second kernel by the first kernel.
In a third aspect, the present application discloses an FPGA comprising:
a storage unit and a processing unit;
wherein the storage unit is used for storing a computer program;
the processing unit is configured to execute the computer program to implement the foregoing disclosed data transmission control method.
In a fourth aspect, the present application discloses a computer readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the data transmission control method disclosed above.
As can be seen, the method includes sending a data frame to a second kernel of a receiving end FPGA, where the data frame includes a frame request sequence number, where the frame request sequence number indicates a number of data frames that the first kernel has sent to the second kernel, and receiving an ACK response frame sent by the second kernel, where the ACK response frame includes a receive credit usage field, a frame response sequence number, and a size of a remaining space of a buffer of the receiving end, where the receive credit usage field indicates a number of data sent by the first kernel that the second kernel has received, and the frame response sequence number indicates a number of data frames sent by the first kernel that the second kernel has received, and then the data flow of a local data sending port may be controlled according to the receive credit usage field, the frame response sequence number, the size of remaining space of the buffer of the receiving end, and locally stored transmit credit consumption data, where the transmit credit consumption data indicates a number of data sent by the first kernel to the second kernel. In view of this, after the first kernel of the sending end FPGA sends the data frame to the second kernel of the receiving end FPGA, the first kernel of the sending end FPGA receives the ACK response frame returned by the second kernel of the receiving end FPGA, so that the data volume and the number of data frames sent by the second kernel already received by the first kernel can be obtained from the received ACK response frame, and then the data volume of the data sending port corresponding to the first kernel is controlled by combining the data volume already sent by the first kernel recorded in the first kernel itself, so that the first kernel of the sending end FPGA can combine the data volume already sent by the second kernel and the received data volume fed back by the second kernel recorded by itself to see whether the second kernel receives all the data volumes already sent, so that the data volume of the first kernel can be controlled according to the situation of the receiving end, and the data transmission of the sending end can be automatically controlled without causing data loss.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a conventional data transmission control;
fig. 2 is a flow chart of a data transmission control method disclosed in the present application;
FIG. 3 is a schematic diagram of an FPGA connection disclosed in the present application;
FIG. 4 is a schematic diagram of an FPGA connection disclosed in the present application;
fig. 5 is a flowchart of a specific data transmission control method disclosed in the present application;
fig. 6 is a flowchart of a specific data transmission control method disclosed in the present application;
fig. 7 is a schematic structural diagram of a data transmission control device according to the present disclosure;
fig. 8 is a schematic diagram of an FPGA structure according to the present disclosure.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
At present, the data flow control method between interconnected kernel realizes static current limiting similar to a speed limiter at a transmitting end, and after data volume is transmitted from the transmitting end, the data volume is firstly transmitted to the speed limiter for rate control, and after the data transmission rate is adjusted, the data volume is transmitted to a receiving end. For example, the rate of the sending end is 2MB/s, but after the current limiting of the speed limiter, the rate of the Buffer (Buffer) sent to the sending end can be reduced to 1MB/s, so that the data is transmitted in the network and the data received by the receiving end are all transmitted at 1MB/s, and the rate of the sending end and the rate of the receiving end are matched, so that the data can be stably transmitted. The receiving end does not know the maximum speed which can be born, so the speed of the speed limiter needs to be manually modified at any time according to the situation, the receiving end can dynamically fluctuate at any time, so that the receiving end cannot be adjusted in time, the condition of negligence of flow exists, and the bandwidth cannot be fully utilized. If the sending rate of the sending end is too large, the data received by the receiving end is lost, and if the sending rate of the sending end is too small, the waste of bandwidth use is caused. In view of this, the present application provides a data transmission control method, which can automatically control data transmission of a transmitting end according to the condition of a receiving end, and can fully utilize bandwidth without causing data loss.
Referring to fig. 2, the embodiment of the application discloses a data transmission control method, which is applied to a first kernel of a sending end FPGA, and includes:
step S11: and sending a data frame to a second kernel of the receiving end FPGA, wherein the data frame comprises a frame request sequence number, and the frame request sequence number represents the number of data frames sent to the second kernel by the first kernel.
Referring to fig. 3, the FPGAs may be directly interconnected. Referring to fig. 4, the FPGAs may also be interconnected by a switch.
In a specific implementation process, the first kernel sends a data frame to a second kernel of the receiving end FPGA, where header information of the data frame generally includes a frame type, a frame request sequence number, and ID (identity) information. The frame type indicates whether the current frame is a data frame or an ACK response frame, the frame request sequence number indicates the number of data frames that the first kernel has transmitted to the second kernel, and the ID information includes ID information of the transmitting end FPGA, ID information of the first kernel, ID information of the receiving end FPGA, and ID information of the second kernel. The sending end FPGA can comprise a plurality of kernel, and the receiving end FPGA can also comprise a plurality of kernel.
Specifically, sending a data frame to a second kernel of the receiving end FPGA includes: adding 1 to the locally stored frame request sequence number to obtain a current frame request sequence number, and adding the current frame request sequence number to a data frame to be transmitted; accumulating the number of data bytes in the data frame to be transmitted to the transmission credit consumption data; and sending the data frame to be sent to a second kernel of a receiving end FPGA, so that after the second kernel receives the data frame, comparing a current frame request sequence number in the data frame with a locally stored expected frame sequence number, adding 1 to a frame response sequence number in the second kernel when the current frame request sequence number is consistent with the locally stored expected frame sequence number, and accumulating the number of bytes received by using data of the receiving credit in the second kernel, wherein the expected frame sequence number represents the frame request sequence number which the second kernel is expected to currently receive.
According to the configured receiving end ID information, a first kernel of the sending end FPGA starts to send a data frame to a second kernel of the corresponding receiving end FPGA, the first kernel performs accumulation operation on a frame request sequence number when each data frame is sent, the value is added into a frame request sequence number field of frame header information, and the number of bytes sent is accumulated internally, namely credit consumption data is sent.
And the second kernel of the receiving end is internally provided with an expected frame sequence number (starting from 0), the frame request sequence number of the frame is compared with the expected frame sequence number when a frame of data is received, if the frame request sequence number is the same as the expected frame sequence number, the frame receiving buffer is used for buffering the frame and the frame response sequence number is added with 1, and if the frame response sequence number is not the same, the frame is discarded and the expected frame sequence number keeps the original value between the frames. When the correct frame request sequence number is received, then the number of bytes in the frame is received over the receive credit usage data accumulation in the second kernel.
Step S12: and receiving an ACK response frame sent by the second kernel, wherein the ACK response frame comprises a receiving credit use field, a frame response sequence number and a receiving end buffer residual space size, the receiving credit use field represents the data quantity sent by the first kernel and received by the second kernel, and the frame response sequence number represents the data frame quantity sent by the first kernel and received by the second kernel.
After the second kernel receives the data frame sent by the first kernel, if the frame request sequence number in the data frame received this time is different from the frame request sequence number in the data frame received before, an ACK response frame is sent to the first kernel, and/or the ACK response frame is sent to the first kernel according to a preset time interval. The receiving the ACK response frame sent by the second kernel includes: receiving an ACK response frame sent by the second kernel after caching data corresponding to the data frame to be sent to a receiving end; and/or receiving an ACK response frame sent by the second kernel according to a preset time interval. The ACK response frame comprises a receiving credit use field, a frame response sequence number and a receiving end buffer residual space size, wherein the receiving credit use field represents the data quantity sent by the first kernel and received by the second kernel, the frame response sequence number represents the data frame quantity sent by the first kernel and received by the second kernel, and in addition, the ACK response frame also comprises ID information, including ID information of a receiving end FPGA, kernel information of the receiving end FPGA and ID information of a sending end FPGA, and when the second kernel sends the ACK response frame to the first kernel, the kernel of the receiving end FPGA is the first kernel, and the kernel of the sending end FPGA is the second kernel.
Step S13: and controlling the data flow of a local data transmission port according to the receiving credit use field, the frame response sequence number, the residual space size of the receiving end buffer memory and the locally stored transmitting credit consumption data, wherein the transmitting credit consumption data represents the data quantity transmitted to the second kernel by the first kernel.
After receiving the ACK response frame, the first kernel may control a data flow of a local data transmission port according to the reception credit usage field, the frame response sequence number, the size of the remaining space of the buffer memory of the receiving end, and the locally stored transmission credit consumption data, where the transmission credit consumption data indicates an amount of data that the first kernel has transmitted to the second kernel.
That is, the first kernel may perform data flow control operations such as retransmission control according to the receiving credit usage field, the frame response sequence number, the size of the remaining buffer space of the receiving end, and the locally stored transmission credit consumption data.
As can be seen, the method includes sending a data frame to a second kernel of a receiving end FPGA, where the data frame includes a frame request sequence number, where the frame request sequence number indicates a number of data frames that the first kernel has sent to the second kernel, and receiving an ACK response frame sent by the second kernel, where the ACK response frame includes a receive credit usage field, a frame response sequence number, and a size of a remaining buffer space of a receiving end, where the receive credit usage field indicates a number of data that the first kernel has received by the second kernel, and the frame response sequence number is used to indicate a number of data frames that the first kernel has received by the second kernel, and then the data flow of a local data sending port may be controlled according to the receive credit usage field, the frame response sequence number, the size of remaining buffer space of the receiving end, and locally stored transmit credit consumption data, where the transmit credit consumption data indicates the number of data that the first kernel has sent to the second kernel. In view of this, after the first kernel of the sending end FPGA sends the data frame to the second kernel of the receiving end FPGA, the first kernel of the sending end FPGA receives the ACK response frame returned by the second kernel of the receiving end FPGA, so that the data volume and the number of data frames sent by the second kernel already received by the first kernel can be obtained from the received ACK response frame, and then the data volume of the data sending port corresponding to the first kernel is controlled by combining the data volume already sent by the first kernel recorded in the first kernel itself, so that the first kernel of the sending end FPGA can combine the data volume already sent by the second kernel and the received data volume fed back by the second kernel recorded by itself to see whether the second kernel receives all the data volumes already sent, so that the data volume of the first kernel can be controlled according to the situation of the receiving end, and the data transmission of the sending end can be automatically controlled without causing data loss.
Referring to fig. 5, an embodiment of the present application discloses a specific data transmission control method, which is applied to a first kernel of a sender FPGA, and the method includes:
step S21: and sending a data frame to a second kernel of the receiving end FPGA, wherein the data frame comprises a frame request sequence number, and the frame request sequence number represents the number of data frames sent to the second kernel by the first kernel.
Step S22: and receiving an ACK response frame sent by the second kernel, wherein the ACK response frame comprises a receiving credit use field, a frame response sequence number and a receiving end buffer residual space size, the receiving credit use field represents the data quantity sent by the first kernel and received by the second kernel, and the frame response sequence number represents the data frame quantity sent by the first kernel and received by the second kernel.
The specific implementation manners of step S21 and step S22 may refer to the disclosure in the foregoing embodiments, and will not be described herein.
Step S23: and comparing the received credit use data in the received credit use field with the locally stored transmission credit consumption data.
After the first kernel receives the ACK response frame, it is further required to control the data flow of the local data transmission port according to the reception credit usage field, the frame response sequence number, the size of the remaining buffer space of the receiving end, and the locally stored transmission credit consumption data.
Specifically, the received credit use data in the received credit use field is compared with the locally stored transmission credit consumption data, so that whether the second kernel receives all the data transmitted by the first kernel can be judged.
Step S24: and if the receiving credit use data in the receiving credit use field is smaller than the locally stored sending credit consumption data, controlling the data flow of the local data sending port according to the frame response sequence number and the size of the residual buffer space of the receiving end.
If the received credit use data in the received credit use field is smaller than the locally stored transmission credit consumption data, the second kernel does not receive all the data sent by the first kernel, so that the data flow of the local data transmission port needs to be controlled according to the frame response sequence number and the buffer residual space size of the receiving end.
Specifically, it is required to determine, according to the frame response sequence number and the size of the remaining buffer space of the receiving end, a target data frame that is sent by the first kernel and not received by the second kernel; and re-sending the target data frame to the second kernel.
Specifically, the determining, according to the frame response sequence number and the size of the remaining buffer space of the receiving end, the target data frame that is sent by the first kernel and not received by the second kernel includes: determining a first target data frame which is sent by the first kernel and is not received in the second kernel according to the frame response sequence number; judging whether the size of the residual buffer space of the receiving end is smaller than or equal to a preset buffer space size threshold value; and if the size of the residual buffer space of the receiving end is smaller than or equal to a preset buffer space size threshold value, determining a second target data frame with the data quantity equal to the size of the residual buffer space of the receiving end from the first target data frame.
That is, it is determined, according to the frame response sequence number, which data frames sent by the first kernel are received by the second kernel, and then, by combining the frame request sequence number in the first kernel, it can be determined which data frames are sent by the first kernel but not received by the second kernel, and these data frames are used as the first target data frames. In the actual process, it is necessary to consider that the size of the remaining space of the receiving end buffer in the second kernel may not store all the first target data frames, so it is also necessary to determine whether the size of the remaining space of the receiving end buffer is smaller than or equal to a preset buffer space size threshold, and when the size of the remaining space of the receiving end buffer is smaller than or equal to the preset buffer space size threshold, it is indicated that the size of the remaining space of the receiving end buffer in the second kernel may not store all the first target data frames, so it is necessary to determine a second target data frame with a data amount equal to the size of the remaining space of the receiving end buffer from the first target data frame, and send the second target data frame to the second kernel again, and when the size of the remaining space of the receiving end buffer is larger than the preset buffer space size threshold, it is indicated that the size of the remaining space of the receiving end buffer in the second kernel may store all the first target data frames, so it is necessary to directly resend the first target data frames to the second kernel.
In an actual application, the determining, according to the frame response sequence number, the first target data frame that is sent by the first kernel and is not received by the second kernel includes: reading a first pointer value from a preset RAM by taking the frame response serial number as an address, wherein the pointer value of data corresponding to each frame request serial number is stored in the preset RAM by taking the frame request serial number as the address; comparing the first pointer value with a second pointer value of a preset FIFO; and if the first pointer value is inconsistent with the current second pointer value of a preset FIFO, taking the data from the data corresponding to the first pointer value to the data corresponding to the second pointer value in the preset FIFO as a first target data frame, wherein the preset FIFO is used for storing the data sent to the second kernel by the first kernel.
That is, a preset FIFO (First Input First Output, first-in first-out queue) and a RAM (random access memory ) are required, wherein the preset FIFO stores data that has been sent to the second kernel, and the preset RAM stores pointer values corresponding to respective data frames with the frame request sequence number as an address. For example, the data with the frame request serial number of 1 is stored in the preset FIFO at the positions of 1 to 100, the pointer value corresponding to the frame request serial number of 1 is 100, and 100 is stored in the storage space with the address of 1 in the preset RAM with 1 as the address. And storing the data with the frame request sequence number of 2 at the positions of 101 to 200 in the preset FIFO, wherein the pointer value corresponding to the frame request sequence number of 2 is 200, and storing 200 into the storage space with the address of 2 in the preset RAM by taking 2 as the address. Thus, a first pointer value can be read from a preset RAM according to the response frame sequence number, then the first pointer value is compared with a current second pointer value of a preset FIFO, if the first pointer value is inconsistent with the current second pointer value of the preset FIFO, the second kernel is indicated to not fully receive the data sent by the first kernel, and the part of data from the data corresponding to the first pointer value to the data corresponding to the second pointer value in the preset FIFO is required to be used as a first target data frame. And if the first pointer value is consistent with the current second pointer value of the preset FIFO, indicating that the second kernel receives all data sent by the first kernel.
After the first target data frame or the second target data frame is sent to the second kernel, a new data frame is sent to the second kernel until the data in the credit use field of the receiving end in the ACK response frame sent by the second kernel is equal to the sending credit consumption data stored in the first kernel, and the new data frame is the data which is not sent to the second kernel by the first kernel before.
Each path of kernel of each FPGA has a set of data transmission control mechanism, so that the interference is avoided, and the transmission bandwidth can be fully utilized. Performing flow control by using a link state represented by transmission credit consumption in a kernel of a transmitting end and reception credit usage of an ACK response frame of a receiving end; and comparing the frame request sequence number in the data frame with the frame response sequence number of the ACK response frame to ensure the accuracy of data transmission. Therefore, effective flow control and reliability transmission of each kernel are realized, and the processing efficiency of the FPGA heterogeneous acceleration platform algorithm is improved.
Referring to fig. 6, a schematic diagram of a data transmission control flow is shown. After the kernel of the transmitting end transmits the data frame to the kernel of the receiving end, the kernel of the receiving end determines whether to update the receiving credit use in the kernel of the receiving end (credit use in the figure), the remaining buffer space of the receiving end (Rx buffer space in the figure) and the frame response sequence number according to the frame request sequence number in the data frame, and then transmits an ACK response frame to the kernel of the transmitting end according to the result, and the kernel of the transmitting end determines whether to need data flow control such as data frame retransmission according to the data in the ACK response frame.
Referring to fig. 7, an embodiment of the present application discloses a data transmission control device, which is applied to a first kernel of a transmitting end FPGA, including:
a data frame sending module 11, configured to send a data frame to a second kernel of the receiving end FPGA, where the data frame includes a frame request sequence number, and the frame request sequence number indicates the number of data frames that the first kernel has sent to the second kernel;
an ACK response frame receiving module 12, configured to receive an ACK response frame sent by the second kernel, where the ACK response frame includes a reception credit usage field, a frame response sequence number, and a size of a remaining space of a buffer of a receiving end, where the reception credit usage field indicates an amount of data sent by the first kernel received by the second kernel, and the frame response sequence number indicates an amount of data frames sent by the first kernel received by the second kernel;
and the flow control module 13 is configured to control a data flow of a local data transmission port according to the received credit usage field, the frame response sequence number, the size of the remaining buffer space of the receiving end, and locally stored transmission credit consumption data, where the transmission credit consumption data indicates an amount of data that has been transmitted by the first kernel to the second kernel.
As can be seen, the method includes sending a data frame to a second kernel of a receiving end FPGA, where the data frame includes a frame request sequence number, where the frame request sequence number indicates a number of data frames that the first kernel has sent to the second kernel, and receiving an ACK response frame sent by the second kernel, where the ACK response frame includes a receive credit usage field, a frame response sequence number, and a size of a remaining space of a buffer of the receiving end, where the receive credit usage field indicates a number of data sent by the first kernel that the second kernel has received, and the frame response sequence number indicates a number of data frames sent by the first kernel that the second kernel has received, and then the data flow of a local data sending port may be controlled according to the receive credit usage field, the frame response sequence number, the size of remaining space of the buffer of the receiving end, and locally stored transmit credit consumption data, where the transmit credit consumption data indicates a number of data sent by the first kernel to the second kernel. In view of this, after the first kernel of the sending end FPGA sends the data frame to the second kernel of the receiving end FPGA, the first kernel of the sending end FPGA receives the ACK response frame returned by the second kernel of the receiving end FPGA, so that the data volume and the number of data frames sent by the second kernel already received by the first kernel can be obtained from the received ACK response frame, and then the data volume of the data sending port corresponding to the first kernel is controlled by combining the data volume already sent by the first kernel recorded in the first kernel itself, so that the first kernel of the sending end FPGA can combine the data volume already sent by the second kernel and the received data volume fed back by the second kernel recorded by itself to see whether the second kernel receives all the data volumes already sent, so that the data volume of the first kernel can be controlled according to the situation of the receiving end, and the data transmission of the sending end can be automatically controlled without causing data loss.
Specifically, the data frame sending module 11 is configured to:
adding 1 to the locally stored frame request sequence number to obtain a current frame request sequence number, and adding the current frame request sequence number to a data frame to be transmitted;
accumulating the number of data bytes in the data frame to be transmitted to the transmission credit consumption data;
and sending the data frame to be sent to a second kernel of a receiving end FPGA, so that after the second kernel receives the data frame, comparing a current frame request sequence number in the data frame with a locally stored expected frame sequence number, adding 1 to a frame response sequence number in the second kernel when the current frame request sequence number is consistent with the locally stored expected frame sequence number, and accumulating the number of bytes received by using data of the receiving credit in the second kernel, wherein the expected frame sequence number represents the frame request sequence number which the second kernel is expected to currently receive.
Further, the ACK response frame receiving module 12 is configured to:
receiving an ACK response frame sent by the second kernel after caching data corresponding to the data frame to be sent to a receiving end;
And/or receiving an ACK response frame sent by the second kernel according to a preset time interval.
Specifically, the flow control module 13 is configured to:
comparing the received credit usage data in the received credit usage field with locally stored transmit credit consumption data;
and if the receiving credit use data in the receiving credit use field is smaller than the locally stored sending credit consumption data, controlling the data flow of the local data sending port according to the frame response sequence number and the size of the residual buffer space of the receiving end.
Specifically, the flow control module 13 is configured to:
determining a target data frame which is sent by the first kernel and is not received in the second kernel according to the frame response sequence number and the size of the residual buffer space of the receiving end;
and re-sending the target data frame to the second kernel.
Specifically, the flow control module 13 is configured to:
determining a first target data frame which is sent by the first kernel and is not received in the second kernel according to the frame response sequence number;
judging whether the size of the residual buffer space of the receiving end is smaller than or equal to a preset buffer space size threshold value;
And if the size of the residual buffer space of the receiving end is smaller than or equal to a preset buffer space size threshold value, determining a second target data frame with the data quantity equal to the size of the residual buffer space of the receiving end from the first target data frame.
Specifically, the flow control module 13 is configured to:
reading a first pointer value from a preset RAM by taking the frame response serial number as an address, wherein the pointer value of data corresponding to each frame request serial number is stored in the preset RAM by taking the frame request serial number as the address;
comparing the first pointer value with a second pointer value of a preset FIFO;
and if the first pointer value is inconsistent with the current second pointer value of a preset FIFO, taking the data from the data corresponding to the first pointer value to the data corresponding to the second pointer value in the preset FIFO as a first target data frame, wherein the preset FIFO is used for storing the data sent to the second kernel by the first kernel.
Further, referring to fig. 8, the embodiment of the present application further discloses an FPGA, which includes: a processing unit 21 and a storage unit 22.
Wherein the storage unit 22 is configured to store a computer program; the processing unit 21 is configured to execute the computer program to implement the data transmission control method disclosed in the foregoing embodiment.
The specific process of the data transmission control method may refer to the corresponding content disclosed in the foregoing embodiment, and will not be described herein.
Further, the embodiment of the application also discloses a computer readable storage medium for storing a computer program, wherein the computer program is executed by a processor to implement the data transmission control method disclosed in any of the previous embodiments.
The specific process of the data transmission control method may refer to the corresponding content disclosed in the foregoing embodiment, and will not be described herein.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, so that the same or similar parts between the embodiments are referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software modules may be disposed in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
Finally, it is further noted that relational terms such as first and second are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a list of processes, methods, articles, or apparatus that comprises other elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above describes in detail a data transmission control method, device, FPGA, and medium provided by the present application, and specific examples are applied to illustrate the principles and embodiments of the present application, where the above description of the embodiments is only for helping to understand the method and core idea of the present application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.
Claims (8)
1. The data transmission control method is characterized by being applied to a first kernel of a sending end FPGA and comprising the following steps:
transmitting a data frame to a second kernel of a receiving end FPGA, wherein the data frame comprises a frame request sequence number, and the frame request sequence number represents the number of data frames transmitted to the second kernel by the first kernel;
receiving an ACK response frame sent by the second kernel, wherein the ACK response frame comprises a receiving credit use field, a frame response sequence number and a receiving end buffer residual space size, the receiving credit use field represents the data quantity sent by the first kernel and received by the second kernel, and the frame response sequence number represents the data frame quantity sent by the first kernel and received by the second kernel;
controlling the data flow of a local data transmission port according to the receiving credit use field, the frame response sequence number, the size of the residual space of the receiving end buffer memory and the locally stored transmitting credit consumption data, wherein the transmitting credit consumption data represents the data quantity transmitted to the second kernel by the first kernel;
determining a first target data frame which is sent by the first kernel and is not received in the second kernel according to the frame response sequence number;
Judging whether the size of the residual buffer space of the receiving end is smaller than or equal to a preset buffer space size threshold value;
if the size of the residual buffer space of the receiving end is smaller than or equal to a preset buffer space size threshold, determining a second target data frame with the data quantity equal to the size of the residual buffer space of the receiving end from the first target data frame;
the determining, according to the frame response sequence number, the first target data frame that is sent by the first kernel and not received by the second kernel includes:
reading a first pointer value from a preset RAM by taking the frame response serial number as an address, wherein the pointer value of data corresponding to each frame request serial number is stored in the preset RAM by taking the frame request serial number as the address;
comparing the first pointer value with a second pointer value of a preset FIFO;
and if the first pointer value is inconsistent with the current second pointer value of a preset FIFO, taking the data from the data corresponding to the first pointer value to the data corresponding to the second pointer value in the preset FIFO as a first target data frame, wherein the preset FIFO is used for storing the data sent to the second kernel by the first kernel.
2. The method for controlling data transmission according to claim 1, wherein the sending the data frame to the second kernel of the receiving end FPGA includes:
adding 1 to the locally stored frame request sequence number to obtain a current frame request sequence number, and adding the current frame request sequence number to a data frame to be transmitted;
accumulating the number of data bytes in the data frame to be transmitted to the transmission credit consumption data;
and sending the data frame to be sent to a second kernel of a receiving end FPGA, so that after the second kernel receives the data frame, comparing a current frame request sequence number in the data frame with a locally stored expected frame sequence number, adding 1 to a frame response sequence number in the second kernel when the current frame request sequence number is consistent with the locally stored expected frame sequence number, and accumulating the number of bytes received by using data of the receiving credit in the second kernel, wherein the expected frame sequence number represents the frame request sequence number which the second kernel is expected to currently receive.
3. The data transmission control method according to claim 2, wherein the receiving the ACK response frame sent by the second kernel includes:
Receiving an ACK response frame sent by the second kernel after caching data corresponding to the data frame to be sent to a receiving end;
and/or receiving an ACK response frame sent by the second kernel according to a preset time interval.
4. A data transmission control method according to any one of claims 1 to 3, wherein said controlling the data traffic of the local data transmission port according to the reception credit usage field, the frame response sequence number, the reception-side buffer remaining space size, and the locally-stored transmission credit consumption data includes:
comparing the received credit usage data in the received credit usage field with locally stored transmitted credit consumption data;
and if the receiving credit use data in the receiving credit use field is smaller than the locally stored sending credit consumption data, controlling the data flow of the local data sending port according to the frame response sequence number and the size of the residual buffer space of the receiving end.
5. The method of claim 4, wherein the controlling the data traffic of the local data transmission port according to the frame response sequence number and the size of the remaining buffer space of the receiving end comprises:
Determining a target data frame which is sent by the first kernel and is not received in the second kernel according to the frame response sequence number and the size of the residual buffer space of the receiving end;
and re-sending the target data frame to the second kernel.
6. The data transmission control device is characterized in that the first kernel applied to the sending end FPGA comprises:
the data frame sending module is used for sending data frames to a second kernel of the receiving end FPGA, wherein the data frames comprise frame request sequence numbers, and the frame request sequence numbers represent the number of the data frames sent to the second kernel by the first kernel;
an ACK response frame receiving module, configured to receive an ACK response frame sent by the second kernel, where the ACK response frame includes a receiving credit usage field, a frame response sequence number, and a size of a remaining space of a buffer of a receiving end, where the receiving credit usage field indicates a data amount sent by the first kernel and received by the second kernel, and the frame response sequence number indicates a data frame amount sent by the first kernel and received by the second kernel;
the flow control module is used for controlling the data flow of a local data transmission port according to the receiving credit use field, the frame response sequence number, the residual space size of the buffer memory of the receiving end and the locally stored transmitting credit consumption data, wherein the transmitting credit consumption data represents the data quantity transmitted to the second kernel by the first kernel;
Wherein the device is further for: determining a first target data frame which is sent by the first kernel and is not received in the second kernel according to the frame response sequence number; judging whether the size of the residual buffer space of the receiving end is smaller than or equal to a preset buffer space size threshold value; if the size of the residual buffer space of the receiving end is smaller than or equal to a preset buffer space size threshold, determining a second target data frame with the data quantity equal to the size of the residual buffer space of the receiving end from the first target data frame; reading a first pointer value from a preset RAM by taking the frame response serial number as an address, wherein the pointer value of data corresponding to each frame request serial number is stored in the preset RAM by taking the frame request serial number as the address; comparing the first pointer value with a second pointer value of a preset FIFO; and if the first pointer value is inconsistent with the current second pointer value of a preset FIFO, taking the data from the data corresponding to the first pointer value to the data corresponding to the second pointer value in the preset FIFO as a first target data frame, wherein the preset FIFO is used for storing the data sent to the second kernel by the first kernel.
7. An FPGA, comprising:
a storage unit and a processing unit;
wherein the storage unit is used for storing a computer program;
the processing unit is configured to execute the computer program to implement the data transmission control method of any one of claims 1 to 5.
8. A computer-readable storage medium storing a computer program, wherein the computer program when executed by a processor implements the data transmission control method according to any one of claims 1 to 5.
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