CN112202446B - Phase synchronization device and method - Google Patents

Phase synchronization device and method Download PDF

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Publication number
CN112202446B
CN112202446B CN201910612126.7A CN201910612126A CN112202446B CN 112202446 B CN112202446 B CN 112202446B CN 201910612126 A CN201910612126 A CN 201910612126A CN 112202446 B CN112202446 B CN 112202446B
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signal
trigger
signals
phase synchronization
delayer
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CN112202446A (en
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苏建明
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Beijing Sanzhong Technology Co ltd
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Beijing Sanzhong Technology Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/101—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

The application discloses a phase synchronization device and a phase synchronization method, wherein the device comprises a first trigger and a second trigger, wherein the receiving end of the first trigger is connected with a first signal source, the clock signal end of the first trigger is connected with a second signal source, the receiving end of the second trigger is connected with the first signal source, and the clock signal end of the second trigger is connected with the second signal source, so that on one hand, the condition of system performance reduction caused by different phases of two signals is avoided, and the working performance of a system is ensured; on the other hand, components such as a crystal oscillator and a filter are not required to be arranged to additionally generate square waves as clock control signals, so that the purchase of the components is reduced, and the cost of signal processing is reduced.

Description

Phase synchronization device and method
Technical Field
The present application relates to the field of communications technologies, and in particular, to a phase synchronization apparatus and method, an antenna array transmitter of a cellular network, an antenna array receiver of a cellular network, and a wireless multi-antenna array electronic device.
Background
The radio communication device needs to generate a stable operating frequency for proper operation. Generally, the frequency is generated by using a crystal oscillator, and since the crystal oscillator only allows signals with the same resonance frequency to pass through, the crystal oscillator can generate very accurate frequency, and the size of the frequency depends on the size and the characteristics of the crystal, and the signals generated by the crystal oscillator are used as clock signals.
In a time division duplex system, in order to reduce power consumption, a phase-locked loop needs to be closed when the system is not in operation, and the system is opened when the system is in operation, so that the frequency can be locked, and the system is stable after each time of switching, but the phase is not guaranteed to be the same each time, the phase difference of 180 degrees appears randomly, the phase difference of two signals can cause beam pointing deviation and gain reduction in a phased array or multi-antenna system, the baseband data can be influenced to be out of synchronization, error code even high-order modulation and demodulation failure is caused, and the performance of the system is seriously influenced.
Disclosure of Invention
In view of the above, the embodiments of the present application provide a phase synchronization apparatus and method, an antenna array transmitter of a cellular network, an antenna array receiver of a cellular network, and a wireless multi-antenna array electronic device, so as to solve the technical defects existing in the prior art.
The embodiment of the application provides a phase synchronization device, which comprises a first trigger and a second trigger, wherein the receiving end of the first trigger is connected with a first signal source, the clock signal end of the first trigger is connected with a second signal source, the receiving end of the second trigger is connected with the first signal source, and the clock signal end of the second trigger is connected with the second signal source.
The embodiment of the application also discloses a phase synchronization method, which comprises the following steps:
Receiving a first signal and a second signal to be processed, wherein the first signal and the second signal are square wave signals with the same frequency and different phases;
inputting the two first signals to signal receiving ends of the first trigger and the second trigger;
inputting two second signals to clock signal ends of the first trigger and the second trigger;
the output ends of the first trigger and the second trigger respectively output third signals and fourth signals with the same frequency and the same phase.
The embodiment of the application also discloses an antenna array transmitter of the cellular network, which comprises the phase synchronization device.
The embodiment of the application also discloses an antenna array receiver of the cellular network, which comprises the phase synchronization device.
The embodiment of the application also discloses wireless multi-antenna array electronic equipment, which comprises the phase synchronization device.
Compared with the prior art, the application has the technical effects that: the device carries out phase synchronization processing on two square wave signals with the same frequency and different phases, the receiving ends of the first trigger and the second trigger receive a first signal output by a first signal source, the clock signal ends of the first trigger and the second trigger receive a second signal output by a second signal source, the second signal is directly used as a clock control signal to be respectively input into the first trigger and the second trigger, the output ends of the first trigger and the second trigger respectively output signals with the same frequency and the same phase, on one hand, the condition of system performance reduction caused by different phases of the two signals is avoided, and the phase synchronization among a plurality of pieces of equipment is rapidly realized in a time division system; on the other hand, components such as a crystal oscillator and a filter are not required to be arranged to additionally generate square waves as clock control signals, so that the purchase of the components is reduced, and the cost of signal processing is reduced.
Drawings
FIG. 1 is a schematic diagram of a phase synchronizer according to the present application;
FIG. 2a is a schematic diagram of waveforms of the first, second, third, and fourth signals according to the present application;
FIG. 2b is a schematic diagram of waveforms of the third and fourth signals for processing the first and second signal outputs according to the present application;
FIG. 3 is a flow chart illustrating a phase synchronization method according to an embodiment of the application;
fig. 4 is a flowchart of a phase synchronization method according to another embodiment of the application.
In the reference numerals, 1-a first signal source; 2-a second signal source; 11-a first flip-flop; 12-a second trigger, 21-a first delayer; 22-a second delay; 31-a first buffer; 32-a second buffer; 40-frequency multiplier.
Detailed Description
The following describes specific embodiments of the present application with reference to the drawings.
In this document, "upper", "lower", "front", "rear", "left", "right", and the like are used merely to indicate relative positional relationships between the relevant portions, and do not limit the absolute positions of the relevant portions.
Herein, "first", "second", etc. are used only for distinguishing one another, and do not denote any order or importance, but rather denote a prerequisite of presence.
Herein, "equal," "same," etc. are not strictly mathematical and/or geometric limitations, but also include deviations that may be appreciated by those skilled in the art and allowed by fabrication or use, etc.
Unless otherwise indicated, numerical ranges herein include not only the entire range within both of its endpoints, but also the several sub-ranges contained therein.
Referring to fig. 1 and 2, a phase synchronization device includes a first flip-flop 11 and a second flip-flop 12, where a receiving end of the first flip-flop 11 is connected to a first signal source 1, a clock signal end of the first flip-flop 11 is connected to a second signal source 2, a receiving end of the second flip-flop 12 is connected to the first signal source 1, and a clock signal end of the second flip-flop 12 is connected to the second signal source 2.
The first signal source 1 and the second signal source 2 respectively generate a first signal and a second signal, the first signal and the second signal are square wave signals with the same frequency and the same phase, namely, the device carries out phase synchronization processing on the two square wave signals with the same frequency and the same phase, the receiving ends of the first trigger 11 and the second trigger 12 are used for receiving the first signal output by the first signal source 1, the clock signal ends of the first trigger 11 and the second trigger 12 are used for receiving the second signal output by the second signal source 2, and as the second signal is the square wave signal, the second signal is directly used as a clock control signal and is respectively input to the first trigger 11 and the second trigger 12, and the output ends of the first trigger 11 and the second trigger 12 respectively output the signals with the same frequency and the same phase; on the other hand, components such as a crystal oscillator and a filter are not required to be arranged to additionally generate square waves as clock control signals, so that the purchase of the components is reduced, and the cost of signal processing is reduced.
The first and second flip-flops 11, 12 of the present application are edge flip-flops, the secondary state of which is dependent only on the state of the input signal at the time when the falling or rising edge of the clock pulse arrives, irrespective of the state of the input signal of the other flip-flop at the time. Therefore, the edge trigger greatly improves the working reliability and enhances the anti-interference capability.
The phase synchronization device of the application further comprises a first delay device 21 and a second delay device 22, wherein the output end of the first delay device 21 is connected with the receiving end of the first trigger 11, the output end of the second delay device 22 is connected with the receiving end of the second trigger 12, and the receiving ends of the first delay device 21 and the second delay device 22 are connected with the first signal source 1.
By arranging the first delayers 21 and 22, the first delayers 21 and 22 respectively delay the two first signals, the two first signals are respectively input into the first trigger 11 and the second trigger 12 in a staggered time, the dead zone of the two first signals input into the first trigger 11 and the second trigger 12 is prevented, the first signals and the second signals can be ensured to be in phase synchronization stably, and the performance of the system is improved.
The receiving ends of the first and second delays 21 and 22 are respectively connected with the signal output end of the first buffer 31, and the receiving end of the first buffer 31 is connected with the first signal source 1.
The first buffer 31 can amplify the first signals, so that not only the strength of the two paths of first signals output by the first buffer 31 is ensured, but also the synchronous transmission of the two first signals is ensured.
The phase synchronization device of the present application further includes a second buffer 32, clock signal ends of the first and second flip-flops 11 and 12 are respectively connected to a signal output end of the second buffer 32, and a receiving end of the second buffer 32 is connected to the second signal source 2.
The second buffer 32 may be a zero-delay buffer, the second buffer 32 fans out one clock control signal into a plurality of clock control signals, and makes the outputs have zero delay and very low skew, and the second buffer 32 increases the synchronism of the circuit clock in a one-to-many manner, so that the synchronous transmission of two second signals serving as clock control signals is ensured.
The receiving end of the second buffer 32 is connected to the signal output end of the frequency multiplier 40, and the receiving end of the frequency multiplier 40 is connected to the second signal source 2.
The frequency multiplier 40 is set, for example, the input frequency is f 1, the output frequency is f 0＝nf1, the coefficient n is 1/2, or 2, the coefficient n of the second signal after frequency multiplication shown in fig. 2a and 2b is set to 1/2, of course, the coefficient n may be set according to the actual signal processing working condition, and the frequency of the second signal is generally increased by two times by the frequency multiplier 40, so as to improve the speed of outputting the same-frequency and same-phase signals of the first and second triggers 11 and 12, and further improve the performance of the system.
The output of the third and fourth signals obtained by the processing of the device is shown in fig. 2a, the delayed first signal is used as the input signals of the first and second triggers 11 and 12, the second signal is used as the clock control signals of the first and second triggers 11 and 12 after frequency multiplication, and the first and second triggers 11 and 12 process the delayed first signal based on the frequency-multiplied second signal and output the third and fourth signals.
The first and second flip-flops 11 and 12 according to the present application process the delayed first signal based on the multiplied second signal, as shown in fig. 2b, and will be described in detail.
Triggering the jump of the first signal after delay at each rising edge of the second signal, and maintaining the state after the jump of the first signal by a high level signal after the rising edge; each falling edge of the second signal and the low level signal following the falling edge maintain the state of the first signal input after the delay,
In the interval from t 0 to t 1, the second signal serving as the clock signal comprises a falling edge and a low-level signal after the falling edge, the first trigger and the second trigger receive the clock signal, and the third signal and the fourth signal output by the first trigger and the second trigger maintain the input state of the first signal after delay;
In the interval from t 1 to t 2, the second signal as the clock signal includes a rising edge and a high level signal after the rising edge, the rising edge of the second signal triggers the transition of the first signal after the delay, the high level signal after the rising edge maintains the state after the transition of the first signal, and the third and fourth signals output by the first and second flip-flops are in a low level state, as shown in fig. 2 b.
In the interval t 0 to t 2, the output of the third and fourth signals is one cycle, and the output of the third and fourth signals in the interval t2 to t4 is the same as the output of the third and fourth signals in the interval t 0 to t 2, as shown in fig. 2 b.
Fig. 3 shows a schematic flow chart of a method of phase synchronization according to an embodiment of the application, comprising steps 302 to 308.
Step 302: and receiving a first signal and a second signal to be processed, wherein the first signal and the second signal are square wave signals with the same frequency and different phases.
Step 304: two first signals are input to the signal receiving ends of the first and second flip-flops 11 and 12.
Step 306: two second signals are input to clock signal terminals of the first and second flip-flops 11 and 12.
Step 308: the output ends of the first trigger 11 and the second trigger 12 respectively output third signals and fourth signals with the same frequency and the same phase.
The method carries out phase synchronization processing on two square wave signals with the same frequency and different phases, receives a first signal output by a first signal source 1 through receiving ends of a first trigger 11 and a second trigger 12, receives a second signal output by a second signal source 2 through clock signal ends of the first trigger 11 and the second trigger 12, directly inputs the second signal as a clock control signal to the first trigger 11 and the second trigger 12 respectively, and outputs a third signal and a fourth signal with the same frequency and the same phase through output ends of the first trigger 11 and the second trigger 12 respectively, so that on one hand, the condition of system performance degradation caused by different phases of the two signals is avoided, and the working performance of a system is ensured; on the other hand, components such as a crystal oscillator and a filter are not required to be arranged to additionally generate square waves as clock control signals, so that the purchase of the components is reduced, and the cost of signal processing is reduced.
Fig. 4 shows a schematic flow chart of a method of phase synchronization according to another embodiment of the application, comprising steps 402 to 412.
Step 402: and receiving a first signal and a second signal to be processed, wherein the first signal and the second signal are square wave signals with the same frequency and different phases.
Step 404: and converting the first signals into two first signals, and respectively carrying out delay processing on the two first signals.
The time of inputting the two first signals to the first trigger 11 and the second trigger 12 is staggered, so that the condition that dead zones occur when the two first signals are input to the first trigger 11 and the second trigger 12 is prevented, the first signals and the second signals can be ensured to be in phase synchronization stably, and the performance of the system is improved.
Step 406: the frequency of the second signal is doubled, converting the second signal into two second signals.
The frequency of the second signal can be increased by two times to increase the speed of the output co-frequency and co-phase signals of the first and second flip-flops 11, 12, further improving the performance of the system.
Step 408: two first signals are input to the signal receiving ends of the first and second flip-flops 11 and 12.
Step 410: two second signals are input to clock signal terminals of the first and second flip-flops 11 and 12.
Step 412: the output ends of the first trigger 11 and the second trigger 12 respectively output third signals and fourth signals with the same frequency and the same phase.
An embodiment of the present application further provides an antenna array transmitter of a cellular network, including a phase synchronization device as described above.
An embodiment of the present application further provides an antenna array receiver of a cellular network, including a phase synchronization device as described above.
An embodiment of the present application further provides a wireless multi-antenna array electronic device, which includes the phase synchronization device as described above.
The device is suitable for various wireless multi-antenna communication systems, reduces the beam directivity deviation in the array antenna, improves the gain in the array antenna, and reduces the baseband desynchronization risk in the multi-input multi-output communication system.
The foregoing is a schematic solution of the antenna array transmitter of the cellular network, the antenna array receiver of the cellular network, and the wireless multi-antenna array electronic device of the present embodiment. It should be noted that, the technical solutions of the above-mentioned technical solutions and the technical solutions of the phase synchronization device belong to the same conception, and the details of the above-mentioned technical solutions, which are not described in detail, can be referred to the description of the technical solutions of the phase synchronization device.
While the preferred embodiments and examples of the present application have been described in detail with reference to the accompanying drawings, the present application is not limited to the above-described embodiments and examples, and various changes may be made within the knowledge of those skilled in the art without departing from the spirit of the present application.

Claims (9)

1. A phase synchronizing device, characterized by: the circuit comprises a first trigger and a second trigger (11 and 12), wherein a receiving end of the first trigger (11) is connected with a first signal source (1), a clock signal end of the first trigger (11) is connected with a second signal source (2), a receiving end of the second trigger (12) is connected with the first signal source (1), and a clock signal end of the second trigger (12) is connected with the second signal source (2), wherein the first signal source (1) and the second signal source (2) are configured to respectively generate a first signal and a second signal, and the first signal and the second signal are square wave signals with the same frequency and different phases;
The first and second flip-flops (11, 12) are configured to receive the first signal and the second signal, process the first signal based on the second signal, and output third and fourth signals of the same frequency and phase;
The phase synchronization device further comprises a first delayer (21) and a second delayer (22), wherein the output end of the first delayer (21) is connected with the receiving end of the first trigger (11), the output end of the second delayer (22) is connected with the receiving end of the second trigger (12), the receiving ends of the first delayer (21) and the second delayer (22) are connected with the first signal source (1), and the first delayer (21) and the second delayer (22) respectively input two first signals to the time staggering of the first trigger (11) and the second trigger (12) so as to prevent dead zone conditions of the first signals and the second triggers (11) and (12).
2. The phase synchronization device according to claim 1, wherein: the receiving ends of the first delayer (21) and the second delayer (22) are respectively connected with the output end of the first buffer (31), and the receiving end of the first buffer (31) is connected with the first signal source (1).
3. The phase synchronization device according to any one of claims 1 or 2, wherein: the circuit further comprises a second buffer (32), clock signal ends of the first trigger and the second trigger (11, 12) are respectively connected with an output end of the second buffer (32), and a receiving end of the second buffer (32) is connected with a second signal source (2).
4. A phase synchronizing device according to claim 3, characterized in that: the receiving end of the second buffer (32) is connected with the output end of the frequency multiplier (40), and the receiving end of the frequency multiplier (40) is connected with the second signal source (2).
5. A method of phase synchronization, characterized by: the phase synchronization device of any one of claims 1-4, configured to receive a first signal and a second signal to be processed, where the first signal and the second signal are square wave signals that are out of phase with each other at the same frequency;
inputting two first signals to signal receiving ends of a first trigger and a second trigger (11 and 12);
Inputting two second signals to clock signal ends of the first trigger and the second trigger (11, 12);
The output ends of the first trigger (11) and the second trigger (12) respectively output third signals and fourth signals with the same frequency and the same phase.
6. The method according to claim 5, wherein before inputting two of the first signals to the signal receiving ends of the first and second flip-flops (11, 12), further comprising:
Converting the first signal into two first signals;
respectively carrying out delay processing on the two first signals;
before inputting the two second signals to the clock signal ends of the first flip-flop (11) and the second flip-flop (12), the method further comprises:
doubling the frequency of the second signal;
the second signal is converted into two second signals.
7. An antenna array transmitter for a cellular network, characterized by: comprising a phase synchronization device according to any one of claims 1 to 4.
8. An antenna array receiver for a cellular network, comprising: comprising a phase synchronization device according to any one of claims 1 to 4.
9. A wireless multi-antenna array electronic device, characterized in that: comprising a phase synchronization device according to any one of claims 1 to 4.
CN201910612126.7A 2019-07-08 2019-07-08 Phase synchronization device and method Active CN112202446B (en)

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