CN112199235A

CN112199235A - Electronic equipment and starting method

Info

Publication number: CN112199235A
Application number: CN202011069280.3A
Authority: CN
Inventors: 刘红
Original assignee: Lenovo Beijing Ltd
Current assignee: Lenovo Beijing Ltd
Priority date: 2020-09-30
Filing date: 2020-09-30
Publication date: 2021-01-08

Abstract

The embodiment of the application discloses electronic equipment and a starting method, wherein the electronic equipment comprises: the first storage area is used for storing basic input and output system files; the second storage area is at least used for storing the backup file of the basic input and output system; the embedded controller is used for correspondingly updating the basic input and output system files and the basic input and output system backup files to the second storage area or the first storage area; a processor, configured to read and execute the bios file or the updated bios file from the first storage area; wherein the first storage area and the second storage area are located in the same memory or different memories connected with the embedded controller.

Description

Electronic equipment and starting method

Technical Field

The present application relates to computer technology, and relates to, but is not limited to, an electronic device and a booting method.

Background

In the related art, after a basic input/output system file for starting the electronic device is damaged, the file cannot be completely and automatically restored, so that the electronic device cannot be successfully started.

Disclosure of Invention

In view of this, an embodiment of the present application provides an electronic device and a booting method.

In a first aspect, an embodiment of the present application provides an electronic device, where the device includes: the first storage area is used for storing basic input and output system files; the second storage area is at least used for storing the backup file of the basic input and output system; the embedded controller is used for correspondingly updating the basic input and output system files and the basic input and output system backup files to the second storage area or the first storage area; a processor, configured to read and execute the bios file or the updated bios file from the first storage area; wherein the first storage area and the second storage area are located in the same memory or different memories connected with the embedded controller.

In a second aspect, an embodiment of the present application provides a starting method, including: in the starting process, detecting that a basic input and output system file in a first storage area is damaged, and updating a basic input and output system backup file in a second storage area to the first storage area by an embedded controller of the electronic equipment so that a processor of the electronic equipment can read and execute the updated basic input and output system file from the first storage area; wherein the first storage area and the second storage area are located in the same memory or different memories connected with the embedded controller.

In a third aspect, an embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the steps in any one of the boot methods in the embodiment of the present application.

In the embodiment of the application, because the bios files stored in the first storage area and the bios backup files stored in the second storage area may be damaged, when it is detected that one of the two storage areas is damaged, the other storage area is used for updating in time to improve the security of file storage and ensure the successful start of the electronic device.

Drawings

Fig. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure;

fig. 2a is a schematic structural diagram of another electronic device according to an embodiment of the present disclosure;

FIG. 2b is a schematic diagram of the electronic device shown in FIG. 2 a;

fig. 3a is a schematic structural diagram of another electronic device according to an embodiment of the present application;

FIG. 3b is a schematic diagram of the electronic device shown in FIG. 3 a;

fig. 4a is a schematic structural diagram of another electronic device according to an embodiment of the present application;

FIG. 4b is a schematic diagram of the electronic device shown in FIG. 4 a;

FIG. 5a is a schematic flowchart of a startup method according to an embodiment of the present application;

fig. 5b is a schematic flowchart of another startup method according to the embodiment of the present application.

Detailed Description

The technical solution of the present application is further elaborated below with reference to the drawings and the embodiments.

Fig. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure, and as shown in fig. 1, the electronic device includes:

a first storage area 101 for storing bios files;

a second storage area 102 at least for storing bios backup files;

the embedded controller 103 is configured to correspondingly update the bios file and the bios backup file to the second storage area 102 or the first storage area 101;

a processor 104, configured to read and execute the bios file or the updated bios file from the first storage area 101.

Wherein the first storage area 101 and the second storage area 102 are located in the same memory or different memories connected to the Embedded Controller (EC) 103; the embedded controller 103 may be connected to the memory through one interface or two interfaces, the embedded controller 103 may be connected to the memory through its own interface or an expansion interface, the expansion interface may be an interface provided by a GPIO extender (General-purpose-output/input) expander, and the expansion interface includes a serial interface, a parallel interface, a universal serial bus interface, a fire wire interface, and the like; therefore, when one or more memories are provided, the embedded controller and the memories can be flexibly connected in a diversified mode.

The Memory may be an SPI ROM (Serial Peripheral interface Read-Only Memory), the Basic Input Output System file (BIOS) may be a set of programs that are fixed to a Serial Peripheral interface Read-Only Memory on the electronic device, and the programs store Basic Input and Output programs of the electronic device, a post-power-on self-test program, and a System self-start program, and the BIOS is used to provide a bottom layer and direct hardware setting and control for the electronic device; the basic input and output system backup file is a backup file of the basic input and output system file; when the computer is started, the embedded controller 103 detects the integrity and security of the bios file, and when the bios file is determined to be damaged, the embedded controller 103 may update the bios backup file to the first storage area 101; similarly, after the normal operation of the system after the system is started, the embedded controller 103 may update the bios file to the second storage area 102 when the bios backup file is damaged.

The processor 104 may be a FCH (Fusion controller hub) designed and manufactured for AMD (ultra-wisdom semiconductor corporation), and the south bridge may complete the booting of the electronic device by reading and executing the updated bios file from the first storage area 101.

In the embodiment of the present application, because the bios files stored in the first storage area 101 and the bios backup files stored in the second storage area 102 may be damaged, when it is detected that one of the two is damaged, the other one of the two is used for updating in time during the booting process, so as to improve the security of file storage and ensure the successful start of the electronic device.

Fig. 2a is a schematic structural diagram of an electronic device according to an embodiment of the present application, and referring to fig. 2a, a first storage area and a second storage area are located in different memories, and the embedded controller is connected to the memories through two interfaces, where the electronic device includes:

a first storage area 201 for storing bios files;

a second storage area 202 at least for storing bios backup files;

the embedded controller 203 is configured to correspondingly update the bios file and the bios backup file to the second storage area 202 or the first storage area 201;

a processor 204, configured to read and execute the bios file or the updated bios file from the first storage area 201.

The first storage area 201 is located in a first storage SPI0 connected to the embedded controller 203, the second storage area 202 is located in a second storage SPI1 connected to the embedded controller 203, and the storage capacities of the first storage SPI0 and the second storage SPI1 may be 32 MB; the first memory SPI0 has a first interface 205, and the second memory SPI1 has a second interface 206; the embedded controller 203 is provided with a fourth interface 207 and a fifth interface 208, the fourth interface 207 is connected with the first interface 205 to form a first channel 209, and the fifth interface 208 is connected with the second interface 206 to form a second channel 210; the embedded controller 203 can access the first storage area 201 through the first channel 209 and/or can access the second storage area 202 through the second channel 210; at least one of the fourth interface 207 and the fifth interface 208 is an extended interface of the embedded controller; the fourth Interface 207 may be a Fast Serial Port (FSPI), and the fifth Interface 208 may be a Secure Support Provider Interface (SSPI).

In one embodiment, referring to fig. 2a, the electronic device further includes a storage area 212, where the storage area 212 stores an embedded controller backup file EC, so that when the firmware of the embedded controller stored in the internal area 211 of the embedded controller is damaged, the embedded controller backup file EC can be restored; the inner area 211 may be an embedded flash of the embedded controller 203; in addition, the embedded controller backup file EC may also be stored in the second storage area 202 together with the basic input output system backup file.

In one embodiment, during the startup process of the electronic device, first, the embedded controller 203 verifies the own firmware in its embedded flash memory 211 and the embedded controller backup file in the storage area 212 on the second memory SPI1, and in case that the embedded controller 203 detects that the own firmware is damaged, reads the embedded controller backup file in the storage area 212 on the second memory SPI1 through the second channel 210 and writes the embedded controller backup file into the embedded flash memory 211.

Next, the embedded controller 203 verifies the bios file in the first storage area 201 on the first storage SPI0 and the bios backup file in the second storage area 202 on the second storage SPI1, and in the case where it is detected that the bios file stored in the first storage area 201 on the first storage SPI0 is damaged, the embedded controller 203 reads the bios backup file in the second storage area 202 on the second storage SPI1 through the second channel 210 and writes the bios backup file in the first storage area 201 through the first channel 209 to update the bios file.

In another embodiment, during the startup process of the electronic device, first, the embedded controller 203 verifies the own firmware in its embedded flash memory 211 and the embedded controller backup file in the storage area 212 on the second memory SPI1, and in case that the embedded controller 203 detects that the embedded controller backup file is damaged, reads the own firmware in its embedded flash memory 211 and writes the own firmware in the storage area 212 through the second channel 210.

Next, the embedded controller 203 verifies the bios file in the first storage area 201 on the first storage SPI0 and the bios backup file in the second storage area 202 on the second storage SPI1, and in the case where the embedded controller 203 detects that the bios backup file stored in the second storage area 202 on the SPI1 is corrupted, the embedded controller 203 reads the bios file in the first storage area 201 on the first storage SPI0 through the first channel 209 and writes the bios file in the second storage area 202 through the second channel 210 to update the bios backup file.

In addition, the first memory SPI0 further has

storage areas

213, 215, and 217, the storage area 213 is used for storing a PSP L2FW file, the storage area 215 is used for storing a WiFi Dash file, and the storage area 217 is used for storing an ECFW for flash file; the storage capacity of the first storage area 201 may be 12MB, the storage capacity of the second storage area 202 may be 8MB, and the storage capacities of the storage areas 212 to 216 may be 256KB, 5MB, 8MB, and 8MB in this order.

Correspondingly, the second memory SPI1 further has

storage areas

214 and 216, the storage area 214 is used for storing a backup file of a PSP L2FW file, the storage area 216 is used for storing a backup file of a WiFi Dash file, and the second memory SPI1 further has a storage area (not shown in the figure) for storing a backup file of an ECFW for flash file.

In addition, the processor 204 is provided with an eighth interface 218, the eighth interface 218 is connected to the first interface 205 through a multi-way switch 219, the eighth interface 218 is connected to the first interface 205 to form a fourth channel 220, the multi-way switch 219 is a switch for controlling the fourth channel 220 and the first channel 209, and the multi-way switch 219 is used for selecting one channel from the fourth channel 220 and the first channel 209 as required.

In one embodiment, the processor 204 is provided with a ninth Interface 221, the embedded controller 203 is provided with a tenth Interface 222, the ninth Interface 221 and the tenth Interface 222 are connected to form a fifth channel 223, the processor 204 can receive an RSMRST # signal released by the embedded controller 203 through the fifth channel 223, and the tenth Interface 222 may be an Enhanced Serial Peripheral Interface (eSPI) or a Low Pin Count (LPC).

The embedded controller 203 is further configured to release the "RSMRST # signal" in case of verifying the self firmware in the embedded flash memory 211, the embedded controller backup file in the storage area 212 on the second memory SPI1, the bios file in the first storage area 201 on the first memory SPI0, and the bios backup file in the second storage area 202 on the second memory SPI1, both successfully (both files are not corrupted or are updated after being corrupted); the processor 204 is configured to read and execute the bios file from the first storage area 201 when the "RSMRST # signal" is received through the fifth channel 223.

Fig. 2b is a schematic diagram of the electronic device shown in fig. 2a, and referring to fig. 2a and 2b, the fourth interface 207 may be an FSPI interface, which may include pin FMISO, pin FMOSI, pin FSCK, and pin FCE #; fifth interface 208 may be an SSPI interface, which may include pin SMISO, pin smiosi, pin SSCK, pin SSCE #; the eighth interface 218 may include pins SPI _ D3, SPI _ D2, SPI _ D1, SPI _ D0, SPI _ CLK, SPI _ CE #.

In the embodiment of the present application, by respectively storing the bios file and the bios backup file in the first memory SPI0 and the second memory SPI1, and enabling the processor 204 to read and execute the bios file or the updated bios file from the first storage area, since the processor 204 cannot directly access the second memory, the bios backup file can be isolated, and the security of the bios backup file can be further ensured in case that the first storage area, even the first memory, is damaged; in addition, the backup files of the embedded controller and the self firmware of the embedded controller, the backup files of the PSP L2FW file and the PSP L2FW file, the backup files of the WiFi Dash file and the WiFi Dash file, and the backup files of the ECFW for flash file and the ECFW for flash file are respectively stored in different memories, so that the backup files are isolated, and the safety of the backup files such as the backup files of the embedded controller can be further ensured.

Fig. 3a is a schematic structural diagram of an electronic device according to an embodiment of the present application, and referring to fig. 3a, a first storage area and a second storage area are located in different memories, and the embedded controller is connected to the memories through an interface, where the electronic device includes:

a first storage area 301 for storing bios files;

a second storage area 302 at least for storing bios backup files;

the embedded controller 303 is configured to correspondingly update the bios file and the bios backup file to the second storage area 302 or the first storage area 301;

a processor 304, configured to read and execute the bios file or the updated bios file from the first storage area 301.

The first storage area 301 is located in a first storage SPI0 connected to the embedded controller 303, the second storage area 302 is located in a second storage SPI1 connected to the embedded controller 303, and the storage capacities of the first storage SPI0 and the second storage SPI1 may be 32 MB; the embedded controller 303 is provided with a sixth interface 307, the sixth interface 307 is connected with the first interface 305 to form a first channel 308, and the sixth interface 307 is connected with the second interface 306 to form a second channel 309; the embedded controller 303 can access the first storage area 301 through the first channel 308 and/or can access the second storage area 302 through the second channel 309; the sixth interface is connected to the first interface 305 and the second interface 306 through a multiplexer 310; the multiplexer may be a MUX (multiplexer).

In one embodiment, referring to fig. 3a, the electronic device further includes a storage area 312, where the storage area 312 stores an embedded controller backup file EC, so that when the firmware of the embedded controller stored in the internal area 311 of the embedded controller is damaged, the embedded controller backup file EC can be restored; the inner area 311 may be an embedded flash memory eflash of the embedded controller 303.

In one embodiment, during the startup process of the electronic device, first, the embedded controller 303 verifies the own firmware in the embedded flash memory 311 thereof and the embedded controller backup file in the storage area 312 on the second memory SPI1, and in case that the embedded controller 303 detects that the own firmware is damaged, reads the embedded controller backup file in the storage area 312 on the second memory SPI1 through the second channel 309 and writes the embedded controller backup file in the embedded flash memory 311.

Next, the embedded controller 303 verifies the bios file in the first storage area 301 on the first storage SPI0 and the bios backup file in the second storage area 302 on the second storage SPI1, and in the case where the embedded controller 303 detects that the bios file stored in the first storage area 301 on the first storage SPI0 is damaged, the embedded controller 303 reads the bios backup file in the second storage area 302 on the second storage SPI1 through the second channel 309 and writes the bios backup file in the first storage area 301 through the first channel 308 to update the bios file.

In another embodiment, during the startup process of the electronic device, first, the embedded controller 303 verifies the own firmware in its embedded flash memory 311 and the embedded controller backup file in the storage area 312 on the second memory SPI1, and in case that the embedded controller 303 detects that the embedded controller backup file is damaged, reads the own firmware in its embedded flash memory 311 and writes the own firmware in the storage area 312 through the second channel 309.

Next, the embedded controller 303 verifies the bios file in the first storage area 301 on the first storage SPI0 and the bios backup file in the second storage area 302 on the second storage SPI1, and in the case where the embedded controller 303 detects that the bios backup file stored in the second storage area 302 on the SPI1 is corrupted, the embedded controller 303 reads the bios file in the first storage area 301 on the first storage SPI0 through the first channel 308 and writes the bios file in the second storage area 302 through the second channel 309 to update the bios backup file.

In addition, the first memory SPI0 further has

storage areas

313, 315, and 317, the storage area 313 is used for storing a PSP L2FW file, the storage area 315 is used for storing a WiFi Dash file, and the storage area 317 is used for storing an ECFW for flash file; the storage capacity of the first storage region 301 may be 12MB, the storage capacity of the second storage region 302 may be 8MB, and the storage capacities of the storage regions 312 to 316 may be 256KB, 5MB, 8MB, and 8MB in this order.

Correspondingly, the second memory SPI1 further has

storage areas

314 and 316, the storage area 314 is used for storing a backup file of the PSP L2FW file, the storage area 316 is used for storing a backup file of the WiFi Dash file, and the second memory SPI1 further has a storage area (not shown in the figure) for storing a backup file of the ECFW for flash file.

In addition, the processor 304 is provided with an eighth interface 318, the eighth interface 318 is connected to the first interface 305 through a multi-way switch 319, the eighth interface 318 is connected to the first interface 305 to form a fourth channel 320, the multi-way switch 319 is a switch for controlling the fourth channel 320 and the first channel 308, and the multi-way switch 319 is used for selecting one channel from the fourth channel 320 and the first channel 308 as required.

In one embodiment, the processor 304 is provided with a ninth Interface 321, the embedded controller 303 is provided with a tenth Interface 322, the ninth Interface 321 and the tenth Interface 322 are connected to form a fifth channel 323, the processor 304 can receive an RSMRST # signal released by the embedded controller 303 through the fifth channel 323, and the tenth Interface 322 may be an Enhanced Serial Peripheral Interface (eSPI) or a Low Pin Count (LPC).

The embedded controller 303 is further configured to release the "RSMRST # signal" in case of verifying the self firmware in the embedded flash memory 311, the embedded controller backup file in the storage area 312 on the second memory SPI1, the bios file in the first storage area 301 on the first memory SPI0, and the bios backup file in the second storage area 302 on the second memory SPI1, both being verified successfully (both files are not corrupted or both updated after being corrupted); the processor 304 is configured to read and execute the bios file from the first storage area 301 when the "RSMRST # signal" is received through the fifth channel 323.

Fig. 3b is a schematic diagram of the electronic device shown in fig. 3a, and referring to fig. 3a and 3b, the sixth interface 307 may be an FSPI interface, which may include pin FMISO, pin FMOSI, pin FSCK, and pin FCE #; the eighth interface 318 may include pins SPI _ D3, SPI _ D2, SPI _ D1, SPI _ D0, SPI _ CLK, SPI _ CE #.

In the embodiment of the present application, by respectively storing the bios file and the bios backup file in the first memory SPI0 and the second memory SPI1, and enabling the processor 304 to read and execute the bios file or the updated bios file from the first storage area, since the processor 304 cannot directly access the second memory, the bios backup file can be isolated, and the security of the bios backup file can be further ensured in case that the first storage area, even the first memory, is damaged; in addition, because the general input/output port of the embedded controller 303 is limited, the embedded controller 303 can only provide one interface when using the multi-way switch, can save the cost, because the multi-way switch separates the reading and writing of the data, can guarantee the safety of the data, because some interfaces transmit the speed of the data slower, need longer time to write the data into the memorizer or read the data from the memorizer through such interface, therefore, can pass the cooperation between the interface that the transmission data speed of the multi-way switch and embedded controller 303 is faster, improve the speed that the data are written into the memorizer or read from the memorizer, provide the renewal speed of the data, even make the data can be recovered faster; the embedded controller backup file and the firmware of the embedded controller, the PSP L2FW file backup file and the PSP L2FW file, the WiFi Dash file backup file and the WiFi Dash file, and the ECFW for flash file backup file and the ECFW for flash file are respectively stored in different memories, so that the backup files are isolated, and the safety of the embedded controller backup files and other backup files can be further ensured.

Fig. 4a is a schematic structural diagram of an electronic device according to an embodiment of the present application, and referring to fig. 4a, a first storage area and a second storage area are located in a same memory, and the embedded controller is connected to the memory through an interface, where the electronic device includes:

a first storage area 401 for storing bios files;

a second storage area 402 at least for storing bios backup files;

the embedded controller 403 is configured to correspondingly update the bios file and the bios backup file to the second storage area 402 or the first storage area 401;

a processor 404, configured to read and execute the bios file or the updated bios file from the first storage area 401.

Wherein the electronic device has a third memory SPI0, and the storage capacity of the second memory SPI0 may be 32 MB; the first memory area 401 and the second memory area 402 are both located in the third memory SPI0, which has a third interface 405.

The embedded controller 403 is provided with a seventh interface 406, the seventh interface 406 is connected with the third interface 405 to form a third channel 407, and the embedded controller 403 can access the first storage area 401 and the second storage area 402 through the third channel 407; the seventh interface 406 may be a self interface or an expansion interface.

In one embodiment, referring to fig. 4a, the electronic device further includes a storage area 409, where the storage area 409 stores an embedded controller backup file EC, so that when the firmware of the embedded controller stored in the internal area 408 of the embedded controller is damaged, the electronic device can be restored based on the embedded controller backup file; the internal area 408 may be an embedded flash memory eflash of the embedded controller 403.

In one embodiment, during the startup process of the electronic device, first, the embedded controller 403 verifies the own firmware in its embedded flash memory 408 and the embedded controller backup file in the storage area 409 on the second memory SPI1, and in case that the embedded controller 403 detects that the own firmware is damaged, reads the embedded controller backup file in the storage area 409 on the third memory SPI0 through the third channel 407 and writes the embedded controller backup file into the embedded flash memory 408.

Next, the embedded controller 403 verifies the bios file in the first storage area 401 on the third storage SPI0 and the bios backup file in the second storage area 402 on the third storage SPI0, and in the case where the embedded controller 403 detects that the bios file stored in the first storage area 401 on the third storage SPI0 is damaged, the embedded controller 403 reads the bios backup file in the second storage area 402 on the third storage SPI0 through the third channel 407 and writes the bios backup file in the first storage area 401 through the third channel 407 to update the bios file.

In another embodiment, during the startup process of the electronic device, first, the embedded controller 403 verifies the self-firmware in its embedded flash memory 408 and the embedded controller backup file in the storage area 409 on the third memory SPI0, and in case that the embedded controller 403 detects that the embedded controller backup file is damaged, reads the self-firmware in its embedded flash memory 408 and writes the self-firmware in the storage area 409 through the third channel 407.

Next, the embedded controller 403 verifies the bios file in the first storage area 401 on the third storage SPI0 and the bios backup file in the second storage area 402 on the third storage SPI0, and in the case where the embedded controller 403 detects that the bios backup file stored in the second storage area 402 on the third storage SPI0 is damaged, the embedded controller 403 reads the bios file in the first storage area 401 on the third storage SPI0 through the third channel 407 and writes the bios file in the second storage area 202 through the third channel 407 to update the bios backup file.

In addition, the first memory SPI0 further has a storage area 410 thereon, and the storage area 410 is used for storing an ECFW for flash file; the first memory SPI0 further has a storage area (not shown in the figure) for storing a backup file of the ECFW for flash file; the storage capacity of the first storage region 401 may be 12MB, the storage capacity of the second storage region 402 may be 7MB, and the storage capacity of the storage region 409 may be 256 KB.

In addition, the processor 404 is provided with an eighth interface 411, the eighth interface 411 is connected to the third interface 405 through a multi-way switch 412, the eighth interface 411 and the third interface 405 are connected to form a sixth channel 413, the multi-way switch 412 is a switch for controlling the sixth channel 413 and the third channel 407, the multi-way switch 412 may be a MOS switch, and the multi-way switch 412 is used for selecting one channel from the sixth channel 413 and the third channel 407 as required.

In one embodiment, the processor 404 is provided with a ninth Interface 414, the embedded controller 403 is provided with a tenth Interface 415, the ninth Interface 414 and the tenth Interface 415 are connected to form a fifth channel 416, the processor 404 can receive an RSMRST # signal released by the embedded controller 403 through the fifth channel 416, and the tenth Interface 415 may be an Enhanced Serial Peripheral Interface (eSPI) or a Low Pin Count (LPC).

The embedded controller 403 is further configured to release the "RSMRST # signal" in case of verifying the self firmware in the embedded flash memory 411, the embedded controller backup file in the storage area 409 on the second memory SPI1, the bios file in the first storage area 401 on the first memory SPI0, and the bios backup file in the second storage area 402 on the second memory SPI1, both successfully (both files are not corrupted or are updated after being corrupted); the processor 404 is configured to read and execute the bios file from the first storage area 401 when the "RSMRST # signal" is received through the fifth channel 416.

Fig. 4b is a schematic diagram of the electronic device shown in fig. 4a, and referring to fig. 4a and 4b, the seventh interface 406 may be an FSPI interface, which may include pin FMISO, pin FMOSI, pin FSCK, and pin FCE #; the eighth interface 411 may include pins SPI _ D3, SPI _ D2, SPI _ D1, SPI _ D0, SPI _ CLK, SPI _ CE #.

In the embodiment of the application, the basic input and output system file and the basic input and output system backup file can be stored in the same memory by expanding the SPI ROM, so that the cost is saved, and the other one can be used for updating in time when the damage of one party is detected in the starting process, so that the safety of file storage is improved, and the successful starting of the electronic equipment can be ensured.

Fig. 5a is a schematic flowchart of a starting method according to an embodiment of the present application, and referring to fig. 5a, the method includes:

step 502 a: in the starting process, detecting that a basic input and output system file in a first storage area is damaged, and updating a basic input and output system backup file in a second storage area to the first storage area by an embedded controller of the electronic equipment so that a processor of the electronic equipment can read and execute the updated basic input and output system file from the first storage area;

wherein the first storage area and the second storage area are located in the same memory or different memories connected with the embedded controller.

In one embodiment, in the case of detecting the self-firmware damage, the embedded controller updates the self-firmware based on the embedded controller backup file in the second storage area.

The first storage area may store not only a Basic Input Output System (BIOS) file, but also PSP L2FW, WiFi Dash, ECFW for flash, and the like.

The embodiment of the present application further provides a starting method, where the method includes steps 602 to 608:

step 602: in the starting process, the embedded controller detects the firmware of the embedded controller;

step 604: under the condition that the self firmware is detected to be damaged, the embedded controller updates the self firmware based on the embedded controller backup file in the second storage area;

step 606: the embedded controller detects a basic input and output system file of a first storage area;

step 608: under the condition that the basic input and output system file of a first storage area is detected to be damaged, an embedded controller of the electronic equipment updates the basic input and output system backup file of a second storage area to the first storage area, so that a processor of the electronic equipment can read and execute the updated basic input and output system file from the first storage area.

The embodiment of the present application further provides a starting method, where the method includes steps 702 to 704:

step 702: in the starting process, the embedded controller detects the firmware of the embedded controller and the basic input and output system file of the first storage area;

step 704: and under the condition that the self firmware and the basic input and output system file are detected to be damaged, the embedded controller updates the self firmware based on the embedded controller backup file in the second storage area, and updates the basic input and output system backup file in the second storage area to the first storage area, so that a processor of the electronic equipment can read and execute the updated basic input and output system file from the first storage area.

An embodiment of the present application further provides a starting method, which is applied to the electronic device, where the method includes steps 802 to 806:

step 802: in the starting process, under the condition that the self firmware is detected to be damaged, the embedded controller updates the self firmware based on the embedded controller backup file in the second storage area;

step 804: detecting that a basic input and output system file in a first storage area is damaged, and updating a basic input and output system backup file in a second storage area to the first storage area by an embedded controller of the electronic equipment;

step 806: after the verification of the basic input and output system file is completed or the updating of the basic input and output system file or the firmware of the embedded controller is completed, the embedded controller releases a specific signal, and the specific signal can enable the processor to read and execute the updated basic input and output system file from the first storage area.

Wherein the specific signal may be an RSMRST # signal, which may be used to inform the processor 3045 that the VSB and 3VSB standby voltages are normal.

Fig. 5b is a starting method of an electronic device according to an embodiment of the present application, where the method includes steps S501b to S506 b:

step S501 b: when the electronic equipment is in the power-off state of S5, pressing a power-on key by a user to start the electronic equipment;

step S502 b: the EC detects whether a basic input/output system file BIOS stored in a first storage area of the electronic equipment and a self firmware EC stored in an embedded flash memory of the EC are correct, if not, the step S503b is executed, and if so, the step S505b is executed;

step S503 b: the EC reads a basic input output system backup file from a second storage area of the electronic device;

step S504 b: the EC writes the basic input output system backup file into the first storage area so as to update the basic input output system file;

step S505 b: the EC releases the RSMRST # signal;

step S506 b: and the processor of the electronic equipment reads the updated basic input and output system file of the first storage area to complete system startup of the electronic equipment.

In the embodiment of the application, the BIOS file and the EC file can be automatically updated through the BIOS backup file and the EC backup file respectively under the condition that the BIOS file and the EC file are damaged, and a user does not need to participate in any operation.

An embodiment of the present application further provides an electronic device, referring to fig. 3a, including a first memory SPI0, a second memory SPI1, an embedded controller 303, and a processor 304, where:

the SPI0 is also called a main memory, the SPI1 is also called a backup memory, the processor 304 cannot directly access the SPI1 backup memory, the BIOS of the basic input output system file is stored in the first storage area 301 of the SPI0, the BIOS of the basic input output system backup file is stored in the second storage area 302 of the SPI1, and in addition, the backup file of the PSP L2 firmware, the backup file of the Wifi Dash file, the backup file of the embedded controller, and the like are also stored in the

other storage areas

314, 316, and 312 of the SPI1, respectively.

The embedded controller 303 may access SPI0 or SPI1 through a data selector (mux) 310, which may be used to isolate SPI0 or SPI1 in the case where the electronic device is in S0 normal operating state.

In the event that a file corruption is found, the embedded controller 303 will copy the backup file from the SPI1 to the SPI0 before power on, which will restart the system after copying the backup file.

In this embodiment of the application, the processor 304 may not directly access the second memory SPI1, the backup files stored in the SPI1 may be isolated, so as to ensure the security of the backup files, and the SPI1 stores the backup files of the PSP L2 firmware, the backup files of the Wifi Dash file, the backup files of the embedded controller, and the like, in addition to the backup files of the basic input output system, so as to further ensure the security of the backup files, and improve the comprehensiveness and richness of the backup files.

In one embodiment, when the embedded controller detects a file corruption, the embedded controller will overwrite the backup file into the SPI0 with the backup file in the SPI1 before power on.

Wherein, the bios file in SPI0 will be overwritten by bios backup file in SPI1 with the help of embedded controller 303, and the system will be started by updated bios file in SPI 0; the embedded controller 303 will detect if its own internal firmware crashes and copy the embedded controller backup file from the SPI1 to the embedded controller's internal random access memory 311 before booting.

The starting process of the electronic device may include the following steps 11 to 16:

step 11: the embedded controller verifies the firmware of the embedded controller in an eflash embedded flash memory of the embedded controller; in case of failure of the verification, executing step 12, and in case of success of the verification, executing step 13;

step 12: the embedded controller loads an embedded controller backup file through a private SPI path 309;

step 13: the embedded controller verifies the basic input output system file at SPI0 through shared SPI path 308; in case of failure of the verification, step 14 is executed, and in case of success of the verification, step 15 is executed;

step 14: the embedded controller uses the basic input and output system backup file to cover the basic input and output system file through a private SPI path 309 and a shared SPI path 308;

the embedded controller 303 can be controlled to communicate with the SPI main memory SPI0 and the backup memory by turning on and off the embedded controller bus switch MUX.

Step 15: the EC releases the RSMRST # signal;

the RSMRST # signal may be a signal for informing the processor 3045 that the VSB and 3VSB standby voltages are normal, among others.

Step 16: processor 304 reads the updated bios file (platform secure boot) from SPI0 main memory.

The file recovery process of the electronic device may include the following steps 21 to 23:

step 21: the embedded controller 303 reads the backup file in the SPI1 backup memory through the private SPI path 309;

step 22: the embedded controller 303 writes the backup file to the SPI0 primary memory over the shared SPI path 308.

Step 23: in the case of a complete file being written, the embedded controller will release the RSMRST # signal.

An embodiment of the present application further provides an electronic device, referring to fig. 2a, including a first memory SPI0, a second memory SPI1, an embedded controller 203, and a processor 204, where:

the SPI0 is also called a main memory, the SPI1 is also called a backup memory, the processor 204 cannot directly access the SPI1 backup memory, the BIOS of the BIOS is stored in the first storage area 201 of the SPI0, the BIOS of the BIOS is stored in the second storage area 202 of the SPI1, and in addition, the backup file of the PSP L2 firmware, the backup file of the Wifi Dash file, the backup file of the embedded controller, and the like are also stored in the

other storage areas

214, 216, and 212 of the SPI1, respectively.

Wherein, the bios file in SPI0 will be overwritten by bios backup file in SPI1 with the help of embedded controller 203, and the system will be started by updated bios file in SPI 0; the embedded controller 203 will detect if its own internal firmware crashes and copy the embedded controller backup files from the SPI1 to the embedded controller's internal random access memory before booting.

The startup process of the electronic device may include the following steps 31 to 36:

step 31: the embedded controller verifies the firmware of the embedded controller in an eflash embedded flash memory of the embedded controller; if the verification fails, step 32 is executed, and if the verification succeeds, step 33 is executed;

step 32: the embedded controller loads an embedded controller backup file through an SSPI path 210;

step 33: the embedded controller verifies the bios file at SPI0 through FSPI path 209; if the verification fails, step 34 is executed, and if the verification succeeds, step 35 is executed;

step 34: the embedded controller overwrites the bios file with the bios backup file through the SSPI path 210;

step 35: the EC releases the RSMRST # signal;

Step 36: the processor 204 reads the updated bios file (platform secure boot) from the SPI0 main memory.

The file recovery process of the electronic device may include the following steps 41 to 43:

step 41: the embedded controller 203 reads the backup file in the SPI1 backup memory through the SSPI path 210;

step 42: the embedded controller 203 writes the backup file to the SPI0 primary memory over the FSPI path 209.

Step 43: in the case of writing a complete file, the embedded controller 203 releases the RSMRST # signal.

An embodiment of the present application further provides an electronic device, referring to fig. 4a, including a third memory SPI0, an embedded controller 403, and a processor 404, where:

a basic input output system file BIOS is stored in a first storage area 401 in the SPI0, a basic input output system backup file BIOS is stored in a second storage area 402 in the SPI0, and an embedded controller backup file is stored in a storage area 409 of the SPI 0; the embedded controller 403 will recover the bios file and the embedded controller's own firmware once detecting a crash; the memory size of the SPI0 can be adjusted to 32 MB.

The starting process of the electronic device may include the following steps 51 to 56:

step 51: the embedded controller verifies the firmware of the embedded controller in an eflash embedded flash memory of the embedded controller; in case of a failure of the verification, step 52 is executed, and in case of a success of the verification, step 53 is executed;

step 52: the embedded controller loads the embedded controller backup file through the fourth channel 413;

step 53: the embedded controller verifies the bios file at SPI0 through fourth channel 413; in the case of a failure of the verification, step 54 is executed, and in the case of a success of the verification, step 55 is executed;

step 54: the embedded controller overwrites the bios file with the bios backup file through the fourth channel 413;

step 55: the EC releases the RSMRST # signal;

the RSMRST # signal may be a signal for informing the processor 4045 that the VSB and 3VSB standby voltages are normal, among others.

Step 56: the processor 404 reads the updated bios file (platform secure boot) from the SPI0 memory.

The file recovery process of the electronic device may include the following steps 61 to 63:

step 61: the embedded controller 403 reads the backup file in the first storage area 401 of the SPI0 through the fourth channel 413;

step 62: the embedded controller 403 writes the backup file in the second storage area 402 of the SPI0 through the fourth channel 413.

And step 63: in the case of writing a complete file, the embedded controller 403 releases the RSMRST # signal.

Based on the foregoing embodiments, an embodiment of the present application provides a starting apparatus, where the apparatus includes units and modules included in the units, and the starting apparatus may be implemented by a processor in an electronic device; of course, the implementation can also be realized through a specific logic circuit; in implementation, the processor may be a Central Processing Unit (CPU), a Microprocessor (MPU), a Digital Signal Processor (DSP), a Field Programmable Gate Array (FPGA), or the like.

It should be noted that, in the embodiment of the present application, if the above-mentioned starting method is implemented in the form of a software functional module and is sold or used as a stand-alone product, it may also be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present application may be essentially implemented or a part contributing to the related art may be embodied in the form of a software product stored in a storage medium, and including a plurality of instructions for enabling an electronic device (which may be a mobile phone, a tablet computer, a desktop computer, a personal digital assistant, a navigator, a digital phone, a video phone, a television, a sensing device, etc.) to execute all or part of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read Only Memory (ROM), a magnetic disk, or an optical disk. Thus, embodiments of the present application are not limited to any specific combination of hardware and software.

Correspondingly, the present application provides a computer-readable storage medium, on which a computer program is stored, which, when executed by a processor, implements the steps in the boot method provided in the above embodiments.

Here, it should be noted that: the above description of the storage medium and method embodiments, similar to the above description of the apparatus embodiments, has similar advantageous effects as the apparatus embodiments. For technical details not disclosed in the embodiments of the storage medium and method of the present application, reference is made to the description of the embodiments of the apparatus of the present application for understanding.

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described device embodiments are merely illustrative, for example, the division of the unit is only a logical functional division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the coupling, direct coupling or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between the devices or units may be electrical, mechanical or other forms.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units; can be located in one place or distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment. In addition, all functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may be separately regarded as one unit, or two or more units may be integrated into one unit; the integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.

Those of ordinary skill in the art will understand that: all or part of the steps for realizing the method embodiments can be completed by hardware related to program instructions, the program can be stored in a computer readable storage medium, and the program executes the steps comprising the method embodiments when executed; and the aforementioned storage medium includes: various media that can store program codes, such as a removable Memory device, a Read Only Memory (ROM), a magnetic disk, or an optical disk. Alternatively, the integrated units described above in the present application may be stored in a computer-readable storage medium if they are implemented in the form of software functional modules and sold or used as independent products. Based on such understanding, the technical solutions of the embodiments of the present application may be essentially implemented or a part contributing to the related art may be embodied in the form of a software product stored in a storage medium, and including a plurality of instructions for enabling a computer device (which may be a mobile phone, a tablet computer, a desktop computer, a personal digital assistant, a navigator, a digital phone, a video phone, a television, a sensing device, etc.) to execute all or part of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a removable storage device, a ROM, a magnetic or optical disk, or other various media that can store program code.

The methods disclosed in the several method embodiments provided in the present application may be combined arbitrarily without conflict to obtain new method embodiments. Features disclosed in several of the product embodiments provided in the present application may be combined in any combination to yield new product embodiments without conflict. The features disclosed in the several method or apparatus embodiments provided in the present application may be combined arbitrarily, without conflict, to arrive at new method embodiments or apparatus embodiments.

The above description is only for the embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. An electronic device, comprising:

the first storage area is used for storing basic input and output system files;

the second storage area is at least used for storing the backup file of the basic input and output system;

the embedded controller is used for correspondingly updating the basic input and output system files and the basic input and output system backup files to the second storage area or the first storage area;

a processor, configured to read and execute the bios file or the updated bios file from the first storage area;

2. The electronic device of claim 1, the embedded controller is connected to the memory through one or two interfaces; or the like, or, alternatively,

the embedded controller is connected with the memory through a self interface or an expansion interface.

3. The electronic device of claim 2, comprising a first memory and a second memory, the first memory area located in the first memory and the second memory area located in the second memory, the first memory having a first interface and the second memory having a second interface;

the embedded controller is provided with a fourth interface and a fifth interface, the fourth interface is connected with the first interface to form a first channel, and the fifth interface is connected with the second interface to form a second channel; or the like, or, alternatively,

the embedded controller is provided with a sixth interface, the sixth interface is connected with the first interface to form a first channel, and the sixth interface is connected with the second interface to form a second channel; or the like, or, alternatively,

the embedded controller can access the first storage area through the first channel and/or can access the second storage area through the second channel.

4. The electronic device of claim 3, wherein at least one of the fourth interface and the fifth interface is an extended interface of the embedded controller; or the like, or, alternatively,

the sixth interface is connected with the first interface and the second interface through a multi-way switch.

5. The electronic device of claim 2, having a third memory, the first and second storage areas each being located in the third memory, the third memory having a third interface;

the embedded controller is provided with a seventh interface, the seventh interface is connected with the third interface to form a third channel, and the embedded controller can access the first storage area and the second storage area through the third channel.

6. The electronic device of any one of claims 1 to 5, the second storage area further storing an embedded controller backup file to enable recovery based on the embedded controller backup file when the firmware of the embedded controller is damaged.

7. The electronic device of any of claims 1-5, the processor provided with an eighth interface;

under the condition that the first storage area is located in a first memory and the second storage area is located in a second memory, the eighth interface is connected with the first interface of the first memory to form a fourth channel, so that the processor can access the first storage area through the fourth channel; or the like, or, alternatively,

in a case where the first storage area and the second storage area are both located in a third memory, the eighth interface is connected to a third interface of the third memory to form a sixth channel, so that the processor can access the first storage area through the sixth channel.

8. A startup method applied to the electronic device according to any one of claims 1 to 7, comprising:

in the starting process, detecting that a basic input and output system file in a first storage area is damaged, and updating a basic input and output system backup file in a second storage area to the first storage area by an embedded controller of the electronic equipment so that a processor of the electronic equipment can read and execute the updated basic input and output system file from the first storage area;

9. The method of claim 8, further comprising:

and under the condition that the self firmware is detected to be damaged, the embedded controller updates the self firmware based on the embedded controller backup file in the second storage area.

10. The method of claim 9, further comprising:

after the verification of the basic input and output system file is completed or the updating of the basic input and output system file or the firmware of the embedded controller is completed, the embedded controller releases a specific signal, and the specific signal can enable the processor to read and execute the updated basic input and output system file from the first storage area.