CN112187193A - Power amplifying circuit - Google Patents
Power amplifying circuit Download PDFInfo
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- CN112187193A CN112187193A CN202011030819.4A CN202011030819A CN112187193A CN 112187193 A CN112187193 A CN 112187193A CN 202011030819 A CN202011030819 A CN 202011030819A CN 112187193 A CN112187193 A CN 112187193A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
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Abstract
One embodiment of the present invention discloses a power amplifying circuit, including: a signal amplification unit and a direct current bias unit; the signal amplification unit is used for amplifying an input radio frequency signal and outputting the amplified radio frequency signal; and the direct current bias unit is used for outputting bias voltage to the signal amplification unit. The invention provides high output power on the basis of realizing the amplification of the radio frequency signal, reduces the power consumption of the circuit and improves the efficiency of the power amplification circuit.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a power amplifying circuit.
Background
With the semiconductor technology and process becoming mature, monolithic microwave integrated circuits are continuously developed, wherein, radio frequency GaAs chips have been widely applied to systems such as radar, radio astronomy, electronic warfare, remote sensing and remote control, and are key circuits of communication systems.
The amplifier is mainly applied to a receiving and transmitting channel of a communication system, provides certain gain, realizes amplification of microwave signals, sends the signals to a next-stage circuit, two ends of the amplifier are directly connected with other chips, 50-ohm impedance matching is required to be realized, and the amplifier circuits used in most products at present have the defects of high power consumption and low efficiency.
Disclosure of Invention
Accordingly, the present invention addresses the above-mentioned problems by providing a power amplification circuit comprising
The signal amplification unit is used for amplifying the input radio frequency signal and outputting the amplified radio frequency signal;
and the direct current bias unit is used for outputting bias voltage to the signal amplification unit.
In a specific embodiment, the signal amplifying unit includes:
first to eighth capacitors, first to eleventh inductors, first to third resistors, and first to third enhancement type field effect transistors;
wherein the content of the first and second substances,
the first end of the first capacitor is connected with the signal input end;
the second end of the first capacitor is connected with the first end of the first inductor, and the second end of the first inductor is grounded;
a first end of the second capacitor is connected with a second end of the first capacitor;
a first terminal of the third capacitor is connected to a second terminal of the second capacitor;
a first end of the first resistor is connected to a first end of the third capacitor, and a second end of the first resistor is connected to a second end of the third capacitor;
the grid electrode of the first enhancement mode field effect transistor is connected with the second end of the third capacitor, the drain electrode of the first enhancement mode field effect transistor is connected with the first end of the third inductor, and the source electrode of the first enhancement mode field effect transistor is connected with the first end of the second inductor;
a second end of the second inductor is grounded;
a second end of the third inductor is connected with a first end of the fourth inductor;
a first end of the fourth capacitor is connected with a second end of the third inductor, and a second end of the fourth capacitor is grounded;
the source electrode of the second enhancement mode field effect transistor is connected with the second end of the fourth inductor, and the drain electrode of the second enhancement mode field effect transistor is connected with the first end of the fifth inductor;
a second end of the fifth inductor is connected with a first end of the sixth inductor;
a second end of the sixth inductor receives a voltage;
a first end of the fifth capacitor is connected with a first end of the sixth inductor, and a second end of the fifth capacitor is connected with a first end of a second resistor;
a second end of the second resistor is connected to a first end of the sixth capacitor;
a gate of the third enhancement mode field effect transistor is connected with the second end of the sixth capacitor, a source of the third enhancement mode field effect transistor is grounded, and a drain of the third enhancement mode field effect transistor is connected with the first end of the seventh inductor;
a first end of the third resistor is connected to a first end of the sixth capacitor, and a second end of the third resistor is connected to a second end of the sixth capacitor;
a second end of the seventh inductor is connected with a first end of the eighth inductor;
a second end of the eighth inductor receives a voltage;
a first end of the ninth inductor is connected with a first end of the eighth inductor; a second end of the ninth inductor is connected with a first end of the seventh capacitor;
a second end of the seventh capacitor is connected with a first end of the eleventh inductor;
a first end of the tenth inductor is connected with a second end of the seventh capacitor; a second end of the tenth inductor is connected with a first end of the eighth capacitor;
a second terminal of the eighth capacitor is grounded;
a second end of the eleventh inductor is connected to a signal output terminal.
In a specific embodiment, the dc bias unit includes:
fourth to ninth resistors, fourth to sixth enhancement type field effect transistors, and a ninth capacitor;
wherein the content of the first and second substances,
a first end of the fifth resistor receives a voltage, and a second end of the fifth resistor is respectively connected with a first end of the fourth resistor and a gate of the second enhancement mode field effect transistor to provide a gate voltage for the second enhancement mode field effect transistor;
a second end of the fourth resistor is connected with a grid electrode and a drain electrode of a fourth enhancement mode field effect transistor;
the source electrode of the fourth enhancement mode field effect transistor is grounded;
a first end of the seventh resistor receives a voltage, and a second end of the seventh resistor is respectively connected with a first end of the sixth resistor and a first end of the first resistor to provide a gate voltage for the first enhancement mode field effect transistor;
a second end of the sixth resistor is connected with a grid electrode and a drain electrode of the fifth enhancement mode field effect transistor;
the source electrode of the fifth enhancement mode field effect transistor is grounded;
a first end of the ninth resistor receives a voltage, and a second end of the ninth resistor is respectively connected with a first end of the eighth resistor and a first end of the third resistor to provide a gate voltage for the third enhancement mode field effect transistor;
a second end of the eighth resistor is connected with a grid electrode and a drain electrode of the sixth enhancement mode field effect transistor;
the source electrode of the sixth enhancement mode field effect transistor is grounded;
the first end of the ninth capacitor receives a voltage and the second end of the ninth capacitor is grounded.
In a specific embodiment, the first enhancement mode field effect transistor in the signal amplification unit and the fifth enhancement mode field effect transistor in the direct current bias unit together form a current input-voltage output type negative feedback.
In a specific embodiment, the third enhancement mode field effect transistor in the signal amplification unit and the sixth enhancement mode field effect transistor in the direct current bias unit together form a current input-voltage output type negative feedback.
In a specific embodiment, the first enhancement mode field effect transistor, the third inductor, the fourth inductor and the second enhancement mode field effect transistor together form a cascode structure.
In a specific embodiment, the eighth inductor, the seventh inductor and the ninth inductor form a T-type matching network to expand the circuit bandwidth.
In a specific embodiment, the third capacitor and the first resistor form a gain compensation circuit structure.
In a specific embodiment, the sixth capacitor and the third resistor form a gain compensation circuit structure.
The invention has the following beneficial effects:
the invention provides high output power on the basis of realizing the amplification of the radio frequency signal, reduces the power consumption of the circuit and improves the efficiency of the power amplification circuit.
Drawings
In order to more clearly illustrate the embodiments of the present application or the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are one embodiment of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 shows a block diagram of a power amplifying circuit according to an embodiment of the present invention.
Fig. 2 shows a circuit diagram of a power amplifying circuit according to an embodiment of the present invention.
Detailed Description
In order to make the technical solution of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and examples. The present invention will be described in detail with reference to specific examples, but the present invention is not limited to these examples. Variations and modifications may be made by those skilled in the art without departing from the principles of the invention and should be considered within the scope of the invention.
Fig. 1 shows a block diagram of a power amplifying circuit according to an embodiment of the present invention.
As can be seen from fig. 1, the power amplification circuit includes a signal amplification unit and a dc bias unit.
VDD is shown as the input of the operating voltage, RFinSignal input for radio frequency signals, RFOUTIs the signal output end of the radio frequency signal.
Specifically, the signal amplification unit is mainly used for amplifying the radio-frequency signal input by the signal input end, outputting the amplified radio-frequency signal through the signal output end, and the direct current bias unit outputs the bias voltage to the signal amplification unit based on the working voltage of the input end of the VDD end.
Fig. 2 shows a circuit diagram of a power amplifying circuit according to an embodiment of the present invention.
As can be seen from fig. 2, the signal amplification unit includes:
first to eighth capacitors C1 to C8, first to eleventh inductors L1 to L11, first to third resistors R1 to R3, and first to third enhancement type field effect transistors M1 to M3;
wherein the content of the first and second substances,
a first terminal of the first capacitor C1 and a signal input terminal RFinConnecting;
the second end of the first capacitor C1 is connected with the first end of the first inductor L1, and the second end of the first inductor L1 is grounded GND;
a first terminal of the second capacitor C2 is connected with a second terminal of the first capacitor C1;
a first terminal of the third capacitor C3 is connected with a second terminal of the second capacitor C2;
a first end of the first resistor R1 is connected with a first end of the third capacitor C3, a second end of the first resistor R1 is connected with a second end of the third capacitor C3;
the gate of the first enhancement mode field effect transistor M1 is connected to the second end of the third capacitor C3, the drain of the first enhancement mode field effect transistor M1 is connected to the first end of the third inductor L3, and the source of the first enhancement mode field effect transistor M1 is connected to the first end of the second inductor L2;
a second end of the second inductor L2 is grounded GND;
a second end of the third inductor L3 is connected with a first end of the fourth inductor L4;
a first end of the fourth capacitor C4 is connected with a second end of the third inductor L3, and a second end of the fourth capacitor C4 is grounded to GND;
the source of the second enhancement mode field effect transistor M2 is connected to the second end of the fourth inductor L4, and the drain of the second enhancement mode field effect transistor M2 is connected to the first end of the fifth inductor L5;
a second end of the fifth inductor L5 is connected with a first end of the sixth inductor L6;
a second end of the sixth inductor L6 receives the voltage VDD;
a first end of the fifth capacitor C5 is connected with a first end of the sixth inductor L6, a second end of the fifth capacitor C5 is connected with a first end of a second resistor R2;
a second end of the second resistor R2 is connected with a first end of the sixth capacitor C6;
the gate of the third enhancement mode field effect transistor M3 is connected with the second end of the sixth capacitor C6, the source of the third enhancement mode field effect transistor M3 is grounded GND, and the drain of the third enhancement mode field effect transistor M3 is connected with the first end of the seventh inductor L7;
a first end of the third resistor R3 is connected with a first end of the sixth capacitor C6, and a second end of the third resistor R3 is connected with a second end of the sixth capacitor C6;
a second end of the seventh inductor L7 is connected with a first end of the eighth inductor L8;
a second end of the eighth inductor L8 receives a voltage VDD;
a first end of the ninth inductor L9 is connected with a first end of the eighth inductor L8; a second end of the ninth inductor L9 is connected with a first end of the seventh capacitor C7;
a second end of the seventh capacitor C7 is connected with a first end of the eleventh inductor L11;
a first end of the tenth inductor L10 is connected with a second end of the seventh capacitor C7; a second end of the tenth inductor L10 is connected with a first end of the eighth capacitor C8;
a second terminal of the eighth capacitor C8 is grounded GND;
a second end of the eleventh inductor L11 and a signal output terminal RFOUTAnd (4) connecting.
The DC bias unit includes:
fourth to ninth resistors R4 to R9, fourth to sixth enhancement type field effect transistors M4 to M6 and
a ninth capacitor C9;
wherein the content of the first and second substances,
a first end of the fifth resistor R5 receives the voltage VDD, and a second end of the fifth resistor R5 is respectively connected to a first end of the fourth resistor R4 and the gate of the second enhancement mode field effect transistor M2 to provide a gate voltage to the second enhancement mode field effect transistor M2;
a second end of the fourth resistor R4 is connected with the gate and the drain of a fourth enhancement mode field effect transistor M4;
the source of the fourth enhancement mode field effect transistor M4 is grounded GND;
a first end of the seventh resistor R7 receives the voltage VDD, and a second end of the seventh resistor R7 is connected to a first end of the sixth resistor R6 and a first end of the first resistor R1, respectively, to provide a gate voltage for the first enhancement mode field effect transistor M1;
a second end of the sixth resistor R6 is connected with the gate and the drain of a fifth enhancement mode field effect transistor M5;
the source of the fifth enhancement mode field effect transistor M5 is grounded GND;
a first end of the ninth resistor R9 receives the voltage VDD, and a second end of the ninth resistor R9 is connected to a first end of the eighth resistor R8 and a first end of the third resistor R3, respectively, to provide a gate voltage for the third enhancement mode field effect transistor M3;
a second end of the eighth resistor R8 is connected with the gate and the drain of a sixth enhancement mode field effect transistor M6;
the source of the sixth enhancement mode field effect transistor M6 is grounded GND;
the first terminal of the ninth capacitor C9 receives the voltage VDD, and the second terminal of the ninth capacitor C9 is grounded GND.
Wherein the content of the first and second substances,
in the signal amplification unit, the first capacitor C1 can play a role of isolating direct current, and removing the influence of the direct current term of the previous stage circuit on the amplification circuit.
As can be seen from the above description of the circuit connection relationship, the third capacitor C3 is connected in parallel with the first resistor R1, so as to form a gain compensation circuit structure, improve the circuit stability, and improve the high-frequency gain performance of the circuit.
Similarly, as can be seen from the above description of the circuit connection relationship, the sixth capacitor C6 and the third resistor R3 are connected in parallel, so as to form a gain compensation circuit structure, improve the stability of the circuit, and improve the high-frequency gain performance of the circuit.
The eighth inductor L8, the seventh inductor L7, and the ninth inductor L9 form a T-type matching network to extend the circuit bandwidth.
The first enhancement mode field effect transistor M1, the third inductor L3, the fourth inductor L4 and the second enhancement mode field effect transistor M2 together form a cascode structure, so as to improve output impedance and gain.
As can be seen from the above description of the circuit connection relationship, in the dc bias unit, the second terminal of the sixth resistor R6 is connected to the gate and the drain of the fifth enhancement mode field effect transistor M5, the source of the fifth enhancement mode field effect transistor M5 is connected to the ground GND, the gate and the drain of the fifth enhancement mode field effect transistor M5 are shorted, and the source is grounded, so that the fifth enhancement mode field effect transistor M5 is equivalent to a resistance of 1/gm.
The first enhancement mode field effect transistor M1 in the signal amplification unit and the fifth enhancement mode field effect transistor M5 in the direct current bias unit jointly form a current input-voltage output type negative feedback, when transconductance of the first enhancement mode field effect transistor M1 and transconductance of the fifth enhancement mode field effect transistor M5 are influenced by process, voltage and temperature (PVT) factors, the fifth enhancement mode field effect transistor M5 can change the bias voltage of the first enhancement mode field effect transistor M1 through the negative feedback, so that influences caused by transconductance changes of the first enhancement mode field effect transistor M1 in a part of signal amplification units are counteracted, and influences of the process, voltage and temperature (PVT) factors on the performance of the amplification circuit are reduced.
Similarly, the third enhancement mode fet M3 in the signal amplification unit and the sixth enhancement mode fet M6 in the dc bias unit together form a current input-voltage output type negative feedback, and when the transconductance of the third enhancement mode fet M3 and the sixth enhancement mode fet M6 is affected by process, voltage and temperature (PVT) factors, the sixth enhancement mode fet M6 can change the bias voltage of the third enhancement mode fet M3 through the negative feedback, so as to cancel the effect of the change of the transconductance of the third enhancement mode fet M3 in a part of the signal amplification units, and reduce the effect of the process, voltage and temperature (PVT) factors on the performance of the amplification circuit.
It should be understood that the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention, and it will be obvious to those skilled in the art that other variations or modifications may be made on the basis of the above description, and all embodiments may not be exhaustive, and all obvious variations or modifications may be included within the scope of the present invention.
Claims (9)
1. A power amplification circuit, characterized in that the circuit comprises
The signal amplification unit is used for amplifying the input radio frequency signal and outputting the amplified radio frequency signal;
and the direct current bias unit is used for outputting bias voltage to the signal amplification unit.
2. The circuit according to claim 1, wherein the signal amplification unit comprises:
first to eighth capacitors, first to eleventh inductors, first to third resistors, and first to third enhancement type field effect transistors;
wherein the content of the first and second substances,
the first end of the first capacitor is connected with the signal input end;
the second end of the first capacitor is connected with the first end of the first inductor, and the second end of the first inductor is grounded;
a first end of the second capacitor is connected with a second end of the first capacitor;
a first terminal of the third capacitor is connected to a second terminal of the second capacitor;
a first end of the first resistor is connected to a first end of the third capacitor, and a second end of the first resistor is connected to a second end of the third capacitor;
the grid electrode of the first enhancement mode field effect transistor is connected with the second end of the third capacitor, the drain electrode of the first enhancement mode field effect transistor is connected with the first end of the third inductor, and the source electrode of the first enhancement mode field effect transistor is connected with the first end of the second inductor;
a second end of the second inductor is grounded;
a second end of the third inductor is connected with a first end of the fourth inductor;
a first end of the fourth capacitor is connected with a second end of the third inductor, and a second end of the fourth capacitor is grounded;
the source electrode of the second enhancement mode field effect transistor is connected with the second end of the fourth inductor, and the drain electrode of the second enhancement mode field effect transistor is connected with the first end of the fifth inductor;
a second end of the fifth inductor is connected with a first end of the sixth inductor;
a second end of the sixth inductor receives a voltage;
a first end of the fifth capacitor is connected with a first end of the sixth inductor, and a second end of the fifth capacitor is connected with a first end of a second resistor;
a second end of the second resistor is connected to a first end of the sixth capacitor;
a gate of the third enhancement mode field effect transistor is connected with the second end of the sixth capacitor, a source of the third enhancement mode field effect transistor is grounded, and a drain of the third enhancement mode field effect transistor is connected with the first end of the seventh inductor;
a first end of the third resistor is connected to a first end of the sixth capacitor, and a second end of the third resistor is connected to a second end of the sixth capacitor;
a second end of the seventh inductor is connected with a first end of the eighth inductor;
a second end of the eighth inductor receives a voltage;
a first end of the ninth inductor is connected with a first end of the eighth inductor; a second end of the ninth inductor is connected with a first end of the seventh capacitor;
a second end of the seventh capacitor is connected with a first end of the eleventh inductor;
a first end of the tenth inductor is connected with a second end of the seventh capacitor; a second end of the tenth inductor is connected with a first end of the eighth capacitor;
a second terminal of the eighth capacitor is grounded;
a second end of the eleventh inductor is connected to a signal output terminal.
3. The circuit of claim 2, wherein the dc bias unit comprises:
fourth to ninth resistors, fourth to sixth enhancement type field effect transistors, and a ninth capacitor;
wherein the content of the first and second substances,
a first end of the fifth resistor receives a voltage, and a second end of the fifth resistor is respectively connected with a first end of the fourth resistor and a gate of the second enhancement mode field effect transistor to provide a gate voltage for the second enhancement mode field effect transistor;
a second end of the fourth resistor is connected with a grid electrode and a drain electrode of a fourth enhancement mode field effect transistor;
the source electrode of the fourth enhancement mode field effect transistor is grounded;
a first end of the seventh resistor receives a voltage, and a second end of the seventh resistor is respectively connected with a first end of the sixth resistor and a first end of the first resistor to provide a gate voltage for the first enhancement mode field effect transistor;
a second end of the sixth resistor is connected with a grid electrode and a drain electrode of the fifth enhancement mode field effect transistor;
the source electrode of the fifth enhancement mode field effect transistor is grounded;
a first end of the ninth resistor receives a voltage, and a second end of the ninth resistor is respectively connected with a first end of the eighth resistor and a first end of the third resistor to provide a gate voltage for the third enhancement mode field effect transistor;
a second end of the eighth resistor is connected with a grid electrode and a drain electrode of the sixth enhancement mode field effect transistor;
the source electrode of the sixth enhancement mode field effect transistor is grounded;
the first end of the ninth capacitor receives a voltage and the second end of the ninth capacitor is grounded.
4. The circuit of claim 3, wherein the first enhancement mode FET in the signal amplifying unit and the fifth enhancement mode FET in the DC bias unit together form a current-input-voltage-output type negative feedback.
5. The circuit of claim 3, wherein the third enhancement mode FET in the signal amplifying unit and the sixth enhancement mode FET in the DC bias unit together form a current-input-voltage-output type negative feedback.
6. The circuit of claim 2, wherein the first enhancement mode field effect transistor, the third inductor, the fourth inductor, and the second enhancement mode field effect transistor together form a cascode structure.
7. The circuit of claim 2, wherein the eighth inductor, the seventh inductor, and the ninth inductor form a T-type matching network to extend the circuit bandwidth.
8. The circuit of claim 2, wherein the third capacitor and the first resistor form a gain compensation circuit structure.
9. The circuit of claim 2, wherein the sixth capacitor and third resistor form a gain compensation circuit structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011030819.4A CN112187193A (en) | 2020-09-27 | 2020-09-27 | Power amplifying circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011030819.4A CN112187193A (en) | 2020-09-27 | 2020-09-27 | Power amplifying circuit |
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| CN112187193A true CN112187193A (en) | 2021-01-05 |
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| CN101944883A (en) * | 2010-08-24 | 2011-01-12 | 上海集成电路研发中心有限公司 | Low-noise amplifier |
| CN109391236A (en) * | 2018-10-29 | 2019-02-26 | 北京无线电测量研究所 | A kind of signal amplification circuit and millimeter-wave signal amplifying circuit |
| CN110138345A (en) * | 2019-05-15 | 2019-08-16 | 北京无线电测量研究所 | A kind of wideband amplification circuit |
| US20200144978A1 (en) * | 2018-11-07 | 2020-05-07 | Korea Advanced Institute Of Science And Technology | Wideband variable gain amplifier with low phase variation |
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2020
- 2020-09-27 CN CN202011030819.4A patent/CN112187193A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101944883A (en) * | 2010-08-24 | 2011-01-12 | 上海集成电路研发中心有限公司 | Low-noise amplifier |
| CN109391236A (en) * | 2018-10-29 | 2019-02-26 | 北京无线电测量研究所 | A kind of signal amplification circuit and millimeter-wave signal amplifying circuit |
| US20200144978A1 (en) * | 2018-11-07 | 2020-05-07 | Korea Advanced Institute Of Science And Technology | Wideband variable gain amplifier with low phase variation |
| CN110138345A (en) * | 2019-05-15 | 2019-08-16 | 北京无线电测量研究所 | A kind of wideband amplification circuit |
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