CN112185959A - 一种与GaN HEMT电力电子器件单片集成的CMOS反相器及制备方法 - Google Patents
一种与GaN HEMT电力电子器件单片集成的CMOS反相器及制备方法 Download PDFInfo
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Abstract
本发明涉及一种与GaN HEMT电力电子器件单片集成的CMOS反相器及制备方法,该CMOS反相器包括:衬底、复合缓冲层、沟道层、复合势垒层、P‑InGaN层、PMOS源电极、PMOS漏电极、PMOS绝缘介质层54、PMOS栅电极、NMOS源电极、NMOS漏电极、NMOS绝缘介质层、NMOS栅电极和互联金属。该CMOS反相器在复合势垒层上制备P‑InGaN层,可以产生空穴,耗尽复合势垒层和沟道层之间的二维电子气,与复合势垒层的界面处形成二维空穴气,从而形成PMOS的导电沟道,提高了PMOS器件的输出电流。
Description
技术领域
本发明属于半导体器件技术领域,具体涉及一种与GaN HEMT电力电子器件单片集成的CMOS反相器及制备方法。
背景技术
基于III族氮化物的高电子迁移率晶体管(HEMT)由于其良好的材料性能和优异的品质因数而被广泛应用于电力电器件之中。GaN体系的材料,即三族氮化物材料,具有一系列优异的物理特性,包括禁带宽度大、临界击穿电场高、迁移率高、电子饱和速度高,另外三族氮化物材料极化系数比较高,导致三族氮化物异质结界面的二维电子气浓度很高,这些优异的材料特性使GaN高电子迁移率晶体管(HEMT)具有高击穿电压、低导通电阻、低栅电荷、高开关速度、高能量转换效率等优异性能,成为面向电动汽车、电网、高铁、消费电子电源模块等领域应用的核心器件。
常关型GaN HEMT器件结构通常通过栅极下面***一层p型氮化物材料而实现,此p型氮化物材料可以为p-GaN、p-InGaN或p-AlGaN。另外一方面,电力电子***小型化的趋势对单片集成CMOS驱动电路的GaN电力电子器件提出了迫切需求。但是,传统方法需要分立SiCMOS驱动电路模块,增加了***体积和***设计的复杂度,因此与GaN HEMT电力电子器件单片集成的GaN CMOS驱动电路具有重要意义。文献中报道过通过利用常关型GaN HEMT的p-GaN栅极材料实现PMOS,但是p-GaN的p型杂质浓度电离能较高,空穴浓度较低,空穴迁移率也比较低,造成p-GaN的PMOS输出电流较低。
发明内容
为了解决现有技术中存在的上述问题,本发明提供了一种与GaN HEMT电力电子器件单片集成的CMOS反相器及制备方法。本发明要解决的技术问题通过以下技术方案实现:
本发明实施例提供了一种与GaN HEMT电力电子器件单片集成的CMOS反相器,包括:
衬底;
复合缓冲层,位于所述衬底上;
沟道层,位于所述复合缓冲层上;
复合势垒层,位于所述沟道层上;
P-InGaN层,位于所述复合势垒层上;
PMOS源电极,位于所述P-InGaN层上;
PMOS漏电极,位于所述P-InGaN层上;
PMOS绝缘介质层,一端覆盖所述PMOS源电极的一部分,另一端覆盖所述PMOS漏电极的一部分,且形成底部嵌入所述P-InGaN层中的凹槽结构;
PMOS栅电极,位于所述PMOS绝缘介质层上;
NMOS源电极,嵌入所述P-InGaN层中且位于所述复合势垒层上;
NMOS漏电极,嵌入所述P-InGaN层中且位于所述复合势垒层上;
NMOS绝缘介质层,位于所述NMOS源电极和所述NMOS漏电极之间的所述P-InGaN层上且覆盖部分所述NMOS源电极和部分所述NMOS漏电极;
NMOS栅电极,位于所述NMOS绝缘介质层上;
互联金属,一端覆盖所述PMOS漏电极的一部分,另一端覆盖所述NMOS源电极的一部分,且形成嵌入所述P-InGaN层、所述复合势垒层和所述沟道层的隔离凹槽。
在本发明的一个实施例中,所述复合缓冲层包括成核层、过渡层、核心缓冲层和背势垒层,其中,
所述成核层位于所述衬底上,所述过渡层位于所述成核层上,所述核心缓冲层位于所述过渡层上,所述背势垒层位于所述核心缓冲层上。
在本发明的一个实施例中,所述复合势垒层包括隔离层、核心势垒层和帽层,其中,所述隔离层位于所述沟道层上,所述核心势垒层位于所述隔离层上,所述帽层位于所述核心势垒层上。
在本发明的一个实施例中,所述P-InGaN层的材料包括Mg掺杂的InGaN层,其中,Mg的掺杂浓度为1017-1020cm-3,所述P-InGaN层的厚度为5-150nm。
在本发明的一个实施例中,所述PMOS源电极、所述PMOS漏电极、所述NMOS源电极、所述NMOS漏电极的材料均包括钛、铝、镍、金、钽中的一种或多种,厚度均为10-500nm。
在本发明的一个实施例中,所述PMOS栅电极包括栅头和栅脚,其中,所述栅脚位于所述PMOS绝缘介质层的凹槽结构中,所述栅头位于所述PMOS绝缘介质层上和所述栅脚上,
所述栅头的宽度大于所述PMOS源电极和所述PMOS漏电极之间的距离;
所述PMOS栅电极的高度为50-800nm。
在本发明的一个实施例中,所述NMOS栅电极的宽度大于所述NMOS源电极和所述NMOS漏电极之间的间距;
所述NMOS栅电极的高度为50-800nm。
在本发明的一个实施例中,还包括P+-InGaN层,所述P+-InGaN层位于所述P-InGaN层上。
在本发明的一个实施例中,所述P+-InGaN层的材料包括Mg掺杂的InGaN层,其中,Mg的掺杂浓度为1017-1020cm-3,所述P+-InGaN层的厚度为1-20nm。
本发明的另一实施例提供了一种与GaN HEMT电力电子器件单片集成的CMOS反相器的制备方法,包括步骤:
S1、在衬底上依次外延生长复合缓冲层、沟道层和复合势垒层;
S2、在所述复合势垒层上外延生长P-InGaN层;
S3、刻蚀所述P-InGaN层、所述复合势垒层和部分所述沟道层,形成互联金属凹槽;
S4、刻蚀所述互联金属凹槽一侧的所述P-InGaN层,形成NMOS源电极凹槽和NMOS漏电极凹槽;
S5、在所述NMOS源电极凹槽和所述NMOS漏电极凹槽中淀积电极金属,形成NMOS源电极和NMOS漏电极;
S6、在所述互联金属凹槽另一侧的所述P-InGaN层上淀积电极金属,形成PMOS源电极和PMOS漏电极;
S7、刻蚀所述P-InGaN层的一部分,形成PMOS栅电极凹槽;
S8、在所述NMOS源电极和所述NMOS漏电极之间的所述P-InGaN层上、部分所述NMOS源电极上、部分所述NMOS漏电极上、所述PMOS栅电极凹槽中、部分所述PMOS源电极和部分所述PMOS漏电极上生长绝缘介质材料,形成PMOS绝缘介质层和NMOS绝缘介质层;其中,所述PMOS绝缘介质层的一端覆盖所述PMOS源电极的一部分,另一端覆盖所述PMOS漏电极的一部分,且形成底部嵌入所述P-InGaN层中的凹槽结构;所述NMOS绝缘介质层位于所述NMOS源电极和所述NMOS漏电极之间的所述P-InGaN层上且覆盖部分所述NMOS源电极和部分所述NMOS漏电极;
S9、在所述PMOS绝缘介质层和所述NMOS绝缘介质层上生长栅电极金属,形成PMOS栅电极和NMOS栅电极,其中,所述PMOS栅电极的宽度大于所述PMOS源电极和所述PMOS漏电极之间的距离,所述NMOS栅电极的宽度大于所述NMOS源电极和所述NMOS漏电极之间的距离;
S10、在所述互联金属凹槽中生长互联金属。
与现有技术相比,本发明的有益效果:
1、本发明的CMOS反相器在复合势垒层上制备P-InGaN层,可以产生空穴,耗尽复合势垒层和沟道层之间的二维电子气,与复合势垒层的界面处形成二维空穴气,形成PMOS的导电沟道,提高了PMOS器件的输出电流。
2、本发明的CMOS反相器中,将NMOS源电极和NMOS漏电极分别形成在P-InGaN层的凹槽中,然后将NMOS栅电极形成在NMOS源电极和NMOS漏电极之间,并且将PMOS源电极和PMOS漏电极形成在P-InGaN层上,然后将PMOS栅电极形成在PMOS源电极和PMOS漏电极之间的凹槽结构中,最大程度上减小了NMOS器件和PMOS器件中栅电极与源电极之间的间距以及栅电极与漏电极之间的间距,从而减小了器件的导通电阻,提升了器件的频率性能;同时,使得NMOS器件和PMOS器件中栅电极金属表面与栅电极的栅头金属之间、漏电极金属表面与栅电极的栅头金属之间在垂直方向上保持了较大的距离,减小了器件的寄生电容,抑制了栅源和栅漏寄生电容对器件工作频率的负面影响。
附图说明
图1为本发明实施例提供的一种与GaN HEMT电力电子器件单片集成的CMOS反相器的结构示意图;
图2为本发明实施例提供的另一种与GaN HEMT电力电子器件单片集成的CMOS反相器的结构示意图;
图3a-图3j本发明实施例提供的一种与GaN HEMT电力电子器件单片集成的CMOS反相器的制备方法的过程示意图。
具体实施方式
下面结合具体实施例对本发明做进一步详细的描述,但本发明的实施方式不限于此。
实施例一
请参见图1,图1为本发明实施例提供的一种与GaN HEMT电力电子器件单片集成的CMOS反相器的结构示意图。
该CMOS反相器包括:衬底1、复合缓冲层2、沟道层3、复合势垒层4、P-InGaN层5、PMOS源电极51、PMOS漏电极52、PMOS绝缘介质层54、PMOS栅电极53、NMOS源电极71、NMOS漏电极72、NMOS绝缘介质层74、NMOS栅电极73和互联金属6。
具体地,复合缓冲层2位于衬底1上;沟道层3位于复合缓冲层2上;复合势垒层4位于沟道层3上;P-InGaN层5位于复合势垒层4上。其中,复合缓冲层2、沟道层3和复合势垒层4均为三族氮化物外延层。
在一个具体实施例中,衬底1的材料包括高阻硅、半绝缘碳化硅、半绝缘蓝宝石、半绝缘金刚石、半绝缘氮化铝中的一种或多种;衬底1的厚度为50-1500μm。当衬底1的材料选用高阻硅时,其电阻率为1000-30000Ωcm,晶向为<111>。
在一个具体实施例中,复合缓冲层2包括成核层21、过渡层22和核心缓冲层23,其中,成核层21位于衬底1上,过渡层22位于成核层21上,核心缓冲层23位于过渡层22上。具体地,成核层21的材料可以为AlN,成核层21的厚度为50-300nm;过渡层22的材料可以是多层不同组分的铝镓氮AlGaN,也可以为氮化铝AlN/氮化镓GaN超晶格层,过渡层22的厚度是0.5-1.5μm;核心缓冲层23的材料包括氮化镓GaN、铝镓氮AlGaN、氮化铝AlN中的一种或多种,核心缓冲层23的厚度是0.5-2μm。
在一个具体实施例中,复合缓冲层2包括成核层21、过渡层22、核心缓冲层23和背势垒层24,其中,成核层21位于衬底1上,过渡层22位于成核层21上,核心缓冲层23位于过渡层22上,背势垒层24位于核心缓冲层23上。具体地,成核层21、过渡层22、核心缓冲层23的材料和厚度请参见上述描述;背势垒层24的材料包括铝镓氮AlGaN、铟镓氮InGaN、氮化铝AlN中的一种或多种,背势垒层24的厚度为2-100nm。
在一个具体实施例中,沟道层3的材料包括非故意掺杂氮化镓GaN、铟镓氮InGaN、氮化铝AlN、铝镓氮AlGaN中的一种或多种,沟道层3的厚度为10-500nm。
在一个具体实施例中,复合势垒层4包括核心势垒层42,核心势垒层42位于沟道层3上,其材料包括铝镓氮AlGaN、铟铝氮InAlN、氮化铝AlN中的一种或多种;当核心势垒层42材料为铝镓氮AlGaN时,铝Al的含量为0.2-0.4,其厚度为10-20nm;当核心势垒层42材料为铟铝氮InAlN,铟In的含量为0.1-0.2,其厚度5-30nm;当核心势垒层42材料为氮化铝AlN时,其厚度为2-10nm。
在一个具体实施例中,复合势垒层4包括隔离层41和核心势垒层42,其中,隔离层41位于沟道层3上,核心势垒层42位于隔离层41上。隔离层42的材料可以AlN,厚度为0.5-1.5nm。
在一个具体实施例中,复合势垒层4包括隔离层41、核心势垒层42和帽层43,其中,隔离层41位于沟道层3上,核心势垒层42位于隔离层41上,帽层43位于核心势垒层42上。
在一个具体实施例中,P-InGaN层5的材料包括Mg掺杂的InGaN层,其中,铟In的含量为0.08,镓Ga的含量为0.92,Mg的掺杂浓度为1017-1020cm-3,P-InGaN层5的厚度为5-150nm。
具体地,PMOS源电极51位于P-InGaN层5上;PMOS漏电极52位于P-InGaN层5上;PMOS绝缘介质层54的一端覆盖PMOS源电极51的一部分,另一端覆盖PMOS漏电极52的一部分,且形成底部嵌入P-InGaN层5中的凹槽结构;PMOS栅电极53位于PMOS绝缘介质层54上。PMOS源电极51、PMOS漏电极52、PMOS栅电极53形成PMOS器件;在P-InGaN层5和复合势垒层4的界面处形成二维空穴气,主要作为PMOS的导电沟道。
可以理解的是,在PMOS源电极51和PMOS漏电极52之间的P-InGaN层5被刻蚀掉一部分形成凹槽,PMOS绝缘介质层54在该凹槽中也形成凹槽结构,凹槽结构的底部位于刻蚀后的P-InGaN层5上,凹槽结构的一侧面与P-InGaN层5的侧面、PMOS源电极51的侧面接触,凹槽结构的另一侧面与P-InGaN层5的侧面、PMOS漏电极52的侧面接触。
在一个具体实施例中,PMOS栅电极53包括栅头531和栅脚532,其中,栅脚532位于PMOS绝缘介质层54的凹槽结构中,栅头531位于PMOS绝缘介质层54上和栅脚532上;栅头531的宽度大于PMOS源电极51和PMOS漏电极52之间的距离,即栅头531比较宽,栅脚532比较细,栅头531宽度应足够覆盖PMOS绝缘介质层54的凹槽。PMOS栅电极53为金属电极,或者氧化物/金属电极,高度为50-800nm。
NMOS源电极71嵌入P-InGaN层5中且位于复合势垒层4上;NMOS漏电极72嵌入P-InGaN层5中且位于复合势垒层4上;NMOS绝缘介质层74位于NMOS源电极71和NMOS漏电极72之间的P-InGaN层5上且覆盖部分NMOS源电极71和部分NMOS漏电极72;NMOS栅电极73位于NMOS绝缘介质层74上。NMOS源电极71、NMOS漏电极72、NMOS栅电极73形成NMOS器件;在沟道层3与复合势垒层4之间的截面处形成二维电子气,主要作为NMOS器件的导电沟道。
可以理解的是,NMOS源电极71和NMOS漏电极72在下方具有NMOS源极凹槽和NMOS漏电极凹槽,在NMOS源电极凹槽处和NMOS漏电极凹槽处的P-InGaN层5被去除,NMOS源极凹槽和NMOS漏电极凹槽中填充NMOS源电极金属和NMOS漏电极金属,从而形成NMOS源电极71和NMOS漏电极72。具体地,NMOS源极凹槽和NMOS漏电极凹槽的深度均为30-200nm。
在一个具体实施例中,NMOS栅电极73的宽度大于NMOS源电极71和NMOS漏电极72之间的间距,即NMOS栅电极73的栅头宽度覆盖NMOS绝缘介质层74的沟道。NMOS栅电极73为金属电极,或者氧化物/金属电极,高度为50-800nm。
在一个具体实施例中,PMOS源电极51、PMOS漏电极52、NMOS源电极71、NMOS漏电极72的材料均包括钛、铝、镍、金、钽中的一种或多种,例如,PMOS源电极51、PMOS漏电极52、NMOS源电极71、NMOS漏电极72的料是钛/铝/镍/金电极,或钛/铝电极,或钽/铝电极;PMOS源电极51、PMOS漏电极52、NMOS源电极71、NMOS漏电极72的厚度均为10-500nm。
在一个具体实施例中,PMOS绝缘介质层54和NMOS绝缘介质层74的厚度均为50-150nm。
具体的,互联金属6一端覆盖PMOS漏电极52的一部分,另一端覆盖NMOS源电极71的一部分,且形成嵌入P-InGaN层5、复合势垒层4和沟道层3的隔离凹槽。
可以理解的是,P-InGaN层5、复合势垒层4的中间部分被完全刻蚀掉,形成两部分,用来分别制作NMOS器件和PMOS器件,沟道层3被刻蚀掉一部分,从而形成凹槽,互联金属6在该凹槽中形成凹槽结构,其底部位于沟道层3上,一侧面与沟道层3的侧面、复合势垒层4的侧面、P-InGaN层5的侧面、PMOS漏电极52的侧面接触,另一侧面与沟道层3的侧面、复合势垒层4的侧面、P-InGaN层5的侧面、NMOS源电极71的侧面接触。
在一个具体实施例中,互联金属6的厚度为20-50nm。互联金属6下,由P-InGaN层5、复合势垒层4和沟道层3形成的隔离凹槽的深度为200-400nm。
进一步地,PMOS源电极51通过金属连线连接电源端VDD,PMOS栅电极53和NMOS栅电极73通过金属连线连接入输入端VIN,PMOS漏电极52和NMOS源电极71通过互联金属6连接至输出端VOUT,NMOS漏电极72通过金属连线连接至接地端GND。
请参见图2,图2为本发明实施例提供的另一种与GaN HEMT电力电子器件单片集成的CMOS反相器的结构示意图,该CMOS反相器包括:衬底1、复合缓冲层2、沟道层3、复合势垒层4、P-InGaN层5、P+-InGaN层8、PMOS源电极51、PMOS漏电极52、PMOS绝缘介质层54、PMOS栅电极53、NMOS源电极71、NMOS漏电极72、NMOS绝缘介质层74、NMOS栅电极73和互联金属6。
其中,P+-InGaN层8位于P-InGaN层5上。P+-InGaN层8的材料包括Mg掺杂的InGaN层,其中,Mg的掺杂浓度为1017-1020cm-3,P+-InGaN层8的厚度为1-20nm。
相应地,在PMOS器件中,在PMOS源电极51和PMOS漏电极52之间的P+-InGaN层8被刻蚀掉,并且P-InGaN层5被刻蚀掉一部分形成凹槽,PMOS绝缘介质层54在该凹槽中也形成凹槽结构,凹槽结构的底部位于刻蚀后的P-InGaN层5上,凹槽结构的一侧面与P-InGaN层5的侧面、P+-InGaN层8的侧面、PMOS源电极51的侧面接触,凹槽结构的另一侧面与P-InGaN层5的侧面、P+-InGaN层8的侧面、PMOS漏电极52的侧面接触。在NMOS器件中,NMOS源电极71和NMOS漏电极72在下方具有NMOS源极凹槽和NMOS漏电极凹槽,在NMOS源电极凹槽处和NMOS漏电极凹槽处的P+-InGaN层8和P-InGaN层5被去除,NMOS源极凹槽和NMOS漏电极凹槽中填充NMOS源电极金属和NMOS漏电极金属,从而形成NMOS源电极71和NMOS漏电极72。
本实施例的CMOS反相器在复合势垒层上制备P-InGaN层,可以产生空穴,耗尽复合势垒层和沟道层之间的二维电子气,与复合势垒层的界面处形成二维空穴气,从而形成PMOS的导电沟道,提高了PMOS器件的输出电流。
本实施例的CMOS反相器中,将NMOS源电极和NMOS漏电极分别形成在P-InGaN层的凹槽中,然后将NMOS栅电极形成在NMOS源电极和NMOS漏电极之间,并且将PMOS源电极和PMOS漏电极形成在P-InGaN层上,然后将PMOS栅电极形成在PMOS源电极和PMOS漏电极之间的凹槽结构中,最大程度上减小了NMOS器件和PMOS器件中栅电极与源电极之间的间距以及栅电极与漏电极之间的间距,从而减小了器件的导通电阻,提升了器件的频率性能;同时,使得NMOS器件和PMOS器件中栅电极金属表面与栅电极的栅头金属之间、漏电极金属表面与栅电极的栅头金属之间在垂直方向上保持了较大的距离,减小了器件的寄生电容,抑制了栅源和栅漏寄生电容对器件工作频率的负面影响。
本实施例所形成的器件结构具有与现有GaN HEMT电力电子器件材料结构和制作工艺兼容、器件开态电流高、导通电阻低、开关速度高、器件工作频率高、阈值电压稳定性好的优点,其在减小源漏间距、降低晶体管的接入电阻的同时,保持了较小的源极和栅极之间寄生电容、漏极和栅极之间的寄生电容,从而提高了器件的频率响应特性,可应用于微波、毫米波和太赫兹的氮化镓器件、电路、芯片和***等领域。
实施例二
在实施例一的基础上,请参见图3a-图3j,图3a-图3j本发明实施例提供的一种与GaN HEMT电力电子器件单片集成的CMOS反相器的制备方法的过程示意图。该制备方法包括步骤:
S1、在衬底1上依次外延生长复合缓冲层2、沟道层3和复合势垒层4,请参见图3a。
具体地,复合缓冲层2、沟道层3和复合势垒层4均为三族氮化物外延层。
S2、在复合势垒层4上外延生长P-InGaN层5,请参见图3b。
具体地,P-InGaN层5的材料包括Mg掺杂的InGaN层,其中,铟In的含量为0.08,镓Ga的含量为0.92,Mg的掺杂浓度为1017-1020cm-3,P-InGaN层5的厚度为5-150nm。
S3、刻蚀P-InGaN层5、复合势垒层4和部分沟道层3,形成互联金属凹槽60,请参加图3c。
具体地,在P-InGaN层5表面旋涂光刻胶,使用光刻机对金属互联区域进行曝光和显影,以露出金属互联区域;然后对金属互联区域的P-InGaN层5、复合势垒层4和部分沟道层3进行刻蚀,形成互联金属凹槽60。
S4、刻蚀互联金属凹槽60一侧的P-InGaN层5,形成NMOS源电极凹槽710和NMOS漏电极凹槽720,请参见图3d。
具体地,在P-InGaN层表面旋涂光刻胶,使用光刻机对NMOS源电极区域和NMOS漏电极区域进行曝光和显影,以露出NMOS源电极区域和NMOS漏电极区域;然后,以光刻胶为掩模,刻蚀NMOS源电极区域和NMOS漏电极区域的P-InGaN层5,形成源电极凹槽710和漏电极凹槽720。
S5、在NMOS源电极凹槽710和NMOS漏电极凹槽720中淀积电极金属,形成NMOS源电极71和NMOS漏电极72,请参见图3e。
具体地,NMOS源电极凹槽和NMOS漏电极凹槽的深度均为30-200nm。
S6、在互联金属凹槽60另一侧的P-InGaN层5上淀积电极金属,形成PMOS源电极51和PMOS漏电极52,请参见图3f。
具体地,在P-AlGaN层5表面旋涂光刻胶,使用光刻机对PMOS源电极区域和PMOS漏电极区域进行曝光和显影,然后以光刻胶为掩模在PMOS源电极区域和PMOS漏电极区域分别淀积PMOS源电极金属和PMOS漏电极金属,形成PMOS源电极51和PMOS漏电极52。
S7、刻蚀P-InGaN层5的一部分,形成PMOS栅电极凹槽530,请参见图3g。
具体地,以PMOS源电极51和PMOS漏电极52为掩膜,刻蚀P-InGaN层5的一部分,在PMOS源电极51和PMOS漏电极52之间在形成PMOS栅电极凹槽530。
S8、在NMOS源电极71和NMOS漏电极72之间的P-InGaN层5上、部分NMOS源电极71上、部分NMOS漏电极72上、PMOS栅电极凹槽530中、部分PMOS源电极51和部分PMOS漏电极52上生长绝缘介质材料,形成PMOS绝缘介质层54和NMOS绝缘介质层74;其中,PMOS绝缘介质层54的一端覆盖PMOS源电极51的一部分,另一端覆盖PMOS漏电极52的一部分,且形成底部嵌入P-InGaN层5中的凹槽结构;NMOS绝缘介质层74位于NMOS源电极71和NMOS漏电极72之间的P-InGaN层5上且覆盖部分NMOS源电极71和部分NMOS漏电极72,请参见图3h。
具体地,首先,在器件表面生长氧化绝缘层;然后涂光刻胶,使用光刻机对PMOS绝缘介质层区域和NMOS绝缘介质层区域以外的光刻胶进行曝光和显影,使得PMOS绝缘介质层区域和NMOS绝缘介质层区域以外区域的氧化绝缘层暴露出来,并将暴露出来的氧化绝缘层刻蚀移除,从而形成PMOS绝缘介质层54和NMOS绝缘介质层74。
S9、在PMOS绝缘介质层54和NMOS绝缘介质层74上生长栅电极金属,形成PMOS栅电极53和NMOS栅电极73,其中,PMOS栅电极53的宽度大于PMOS源电极51和PMOS漏电极52之间的距离,NMOS栅电极73的宽度大于NMOS源电极71和NMOS漏电极72之间的距离,请参见图3i。
S10、在互联金属凹槽60中生长互联金属6,请参见图3j。
具体地,在互联金属凹槽60中生长互联金属6,使互联金属6一端覆盖PMOS漏电极52的一部分,另一端覆盖NMOS源电极71的一部分,且形成嵌入P-InGaN层5、复合势垒层4和沟道层3的隔离凹槽;并通过金属连线将PMOS源电极51引出作为电源端VDD,PMOS栅电极53、NMOS栅电极73引出作为输入端VIN,PMOS漏电极52、NMOS源电极71引出作为输出端VOUT,NMOS漏电极72引出作为接地端GND。
然后在器件表面生长钝化层9,对器件进行保护,从而完成器件的制备,制备得到的器件结构请参见实施例一的图1,本实施例不再赘述。
进一步地,当采用实施例一中图2的包括P+-InGaN层8的CMOS反相器结构时,在制备互联金属6、PMOS绝缘介质层54、NMOS源电极71、NMOS漏电极72时,需要将相应的P+-InGaN层8刻蚀掉,从而形成包括P+-InGaN层8的CMOS反相器。
本实施例的制备方法不使用重掺杂三族氮化物材料再生长技术,制造工艺简单,工艺成本比较低。
本实施例的CMOS反相器在复合势垒层上制备P-InGaN层,可以产生空穴,耗尽复合势垒层和沟道层之间的二维电子气,与复合势垒层的界面处形成二维空穴气,从而形成PMOS的导电沟道,提高了PMOS器件的输出电流。
以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明,不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说,在不脱离本发明构思的前提下,还可以做出若干简单推演或替换,都应当视为属于本发明的保护范围。
Claims (10)
1.一种与GaN HEMT电力电子器件单片集成的CMOS反相器,其特征在于,包括:
衬底(1);
复合缓冲层(2),位于所述衬底(1)上;
沟道层(3),位于所述复合缓冲层(2)上;
复合势垒层(4),位于所述沟道层(3)上;
P-InGaN层(5),位于所述复合势垒层(4)上;
PMOS源电极(51),位于所述P-InGaN层(5)上;
PMOS漏电极(52),位于所述P-InGaN层(5)上;
PMOS绝缘介质层(54),一端覆盖所述PMOS源电极(51)的一部分,另一端覆盖所述PMOS漏电极(52)的一部分,且形成底部嵌入所述P-InGaN层(5)中的凹槽结构;
PMOS栅电极(53),位于所述PMOS绝缘介质层(54)上;
NMOS源电极(71),嵌入所述P-InGaN层(5)中且位于所述复合势垒层(4)上;
NMOS漏电极(72),嵌入所述P-InGaN层(5)中且位于所述复合势垒层(4)上;
NMOS绝缘介质层(74),位于所述NMOS源电极(71)和所述NMOS漏电极(72)之间的所述P-InGaN层(5)上且覆盖部分所述NMOS源电极(71)和部分所述NMOS漏电极(72);
NMOS栅电极(73),位于所述NMOS绝缘介质层(74)上;
互联金属(6),一端覆盖所述PMOS漏电极(52)的一部分,另一端覆盖所述NMOS源电极(71)的一部分,且形成嵌入所述P-InGaN层(5)、所述复合势垒层(4)和所述沟道层(3)的隔离凹槽。
2.如权利要求1所述的与GaN HEMT电力电子器件单片集成的CMOS反相器,其特征在于,所述复合缓冲层(2)包括成核层(21)、过渡层(22)、核心缓冲层(23)和背势垒层(24),其中,
所述成核层(21)位于所述衬底(1)上,所述过渡层(22)位于所述成核层(21)上,所述核心缓冲层(23)位于所述过渡层(22)上,所述背势垒层(24)位于所述核心缓冲层(23)上。
3.如权利要求1所述的与GaN HEMT电力电子器件单片集成的CMOS反相器,其特征在于,所述复合势垒层(4)包括隔离层(41)、核心势垒层(42)和帽层(43),其中,所述隔离层(41)位于所述沟道层(3)上,所述核心势垒层(42)位于所述隔离层(41)上,所述帽层(43)位于所述核心势垒层(42)上。
4.如权利要求1所述的与GaN HEMT电力电子器件单片集成的CMOS反相器,其特征在于,所述P-InGaN层(5)的材料包括Mg掺杂的InGaN层,其中,Mg的掺杂浓度为1017-1020cm-3,所述P-InGaN层(5)的厚度为5-150nm。
5.如权利要求1所述的与GaN HEMT电力电子器件单片集成的CMOS反相器,其特征在于,所述PMOS源电极(51)、所述PMOS漏电极(52)、所述NMOS源电极(71)、所述NMOS漏电极(72)的材料均包括钛、铝、镍、金、钽中的一种或多种,厚度均为10-500nm。
6.如权利要求1所述的与GaN HEMT电力电子器件单片集成的CMOS反相器,其特征在于,所述PMOS栅电极(53)包括栅头(531)和栅脚(532),其中,所述栅脚(532)位于所述PMOS绝缘介质层(54)的凹槽结构中,所述栅头(531)位于所述PMOS绝缘介质层(54)上和所述栅脚(532)上,
所述栅头(531)的宽度大于所述PMOS源电极(51)和所述PMOS漏电极(52)之间的距离;
所述PMOS栅电极(53)的高度为50-800nm。
7.如权利要求1所述的与GaN HEMT电力电子器件单片集成的CMOS反相器,其特征在于,所述NMOS栅电极(73)的宽度大于所述NMOS源电极(71)和所述NMOS漏电极(72)之间的间距;
所述NMOS栅电极(73)的高度为50-800nm。
8.如权利要求1所述的与GaN HEMT电力电子器件单片集成的CMOS反相器,其特征在于,还包括P+-InGaN层(8),所述P+-InGaN层(8)位于所述P-InGaN层(5)上。
9.如权利要求8所述的与GaN HEMT电力电子器件单片集成的CMOS反相器,其特征在于,所述P+-InGaN层(8)的材料包括Mg掺杂的InGaN层,其中,Mg的掺杂浓度为1017-1020cm-3,所述P+-InGaN层(8)的厚度为1-20nm。
10.一种与GaN HEMT电力电子器件单片集成的CMOS反相器的制备方法,其特征在于,包括步骤:
S1、在衬底(1)上依次外延生长复合缓冲层(2)、沟道层(3)和复合势垒层(4);
S2、在所述复合势垒层(4)上外延生长P-InGaN层(5);
S3、刻蚀所述P-InGaN层(5)、所述复合势垒层(4)和部分所述沟道层(3),形成互联金属凹槽(60);
S4、刻蚀所述互联金属凹槽(60)一侧的所述P-InGaN层(5),形成NMOS源电极凹槽(710)和NMOS漏电极凹槽(720);
S5、在所述NMOS源电极凹槽(710)和所述NMOS漏电极凹槽(720)中淀积电极金属,形成NMOS源电极(71)和NMOS漏电极(72);
S6、在所述互联金属凹槽(60)另一侧的所述P-InGaN层(5)上淀积电极金属,形成PMOS源电极(51)和PMOS漏电极(52);
S7、刻蚀所述P-InGaN层(5)的一部分,形成PMOS栅电极凹槽(530);
S8、在所述NMOS源电极(71)和所述NMOS漏电极(72)之间的所述P-InGaN层(5)上、部分所述NMOS源电极(71)上、部分所述NMOS漏电极(72)上、所述PMOS栅电极凹槽(530)中、部分所述PMOS源电极(51)和部分所述PMOS漏电极(52)上生长绝缘介质材料,形成PMOS绝缘介质层(54)和NMOS绝缘介质层(74);其中,所述PMOS绝缘介质层(54)的一端覆盖所述PMOS源电极(51)的一部分,另一端覆盖所述PMOS漏电极(52)的一部分,且形成底部嵌入所述P-InGaN层(5)中的凹槽结构;所述NMOS绝缘介质层(74)位于所述NMOS源电极(71)和所述NMOS漏电极(72)之间的所述P-InGaN层(5)上且覆盖部分所述NMOS源电极(71)和部分所述NMOS漏电极(72);
S9、在所述PMOS绝缘介质层(54)和所述NMOS绝缘介质层(74)上生长栅电极金属,形成PMOS栅电极(53)和NMOS栅电极(73),其中,所述PMOS栅电极(53)的宽度大于所述PMOS源电极(51)和所述PMOS漏电极(52)之间的距离,所述NMOS栅电极(73)的宽度大于所述NMOS源电极(71)和所述NMOS漏电极(72)之间的距离;
S10、在所述互联金属凹槽(60)中生长互联金属(6)。
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