CN112185903A - Electronic package and manufacturing method thereof - Google Patents

Electronic package and manufacturing method thereof Download PDF

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Publication number
CN112185903A
CN112185903A CN201910624358.4A CN201910624358A CN112185903A CN 112185903 A CN112185903 A CN 112185903A CN 201910624358 A CN201910624358 A CN 201910624358A CN 112185903 A CN112185903 A CN 112185903A
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CN
China
Prior art keywords
layer
electronic
leads
package
electronic component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201910624358.4A
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Chinese (zh)
Inventor
唐绍祖
马伯豪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Publication of CN112185903A publication Critical patent/CN112185903A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

An electronic package and its manufacturing method, locate the electronic component on the bearing member by way of covering crystal, and then wrap up the electronic component with the packaging layer, and through the operation of levelling, remove some materials of the packaging layer, some materials of the electronic component and some materials of the bearing member, in order to reduce the whole thickness of the electronic package.

Description

Electronic package and manufacturing method thereof
Technical Field
The present invention relates to a semiconductor packaging process, and more particularly, to an electronic package and a method for fabricating the same.
Background
Currently, there are many technologies applied in the field of Chip packaging, such as flip Chip packaging processes, such as Chip Scale Package (CSP), Direct Chip Attached Package (DCA), or Multi-Chip Module Package (MCM), or three-dimensional stacking and integrating of chips into a three-dimensional integrated circuit (3D IC).
Referring to fig. 1, a Quad Flat No lead (QFN) type semiconductor package 1 is known, in which a semiconductor chip 11 is flip-chip mounted on a leadframe 10 via a plurality of solder bumps 110, and then the semiconductor chip 11, the leadframe 10 and the solder bumps 110 are encapsulated by an encapsulant 12, followed by dicing, such that Side surfaces (Side surfaces) and Bottom surfaces (Bottom surfaces) of the leads 100 of the leadframe 10 are exposed from the encapsulant 12, and the Bottom surfaces of the leads 100 are flush with the Bottom Surface of the encapsulant 12.
On the other hand, in order to meet the thinning requirement, the thickness d of the semiconductor chip 11 needs to be reduced, and then the semiconductor chip 11 is mounted on the lead frame 10.
However, under the requirement of a small package volume with a small number of multi-contacts (I/O), especially when the overall thickness t of the semiconductor package 1 is less than 0.3 mm, the required thickness d of the semiconductor chip 11 is very small, so when the semiconductor chip 11 is mounted on the leadframe 10, the semiconductor package 1 is easily pressed to generate a crack (crack), which results in poor reliability of the semiconductor package 1.
Therefore, how to overcome the above-mentioned problems of the prior art has become an issue to be solved.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention provides an electronic package and a method for fabricating the same, so as to reduce the overall thickness of the electronic package.
The electronic package of the present invention includes: a carrier having a plurality of leads; an electronic element which is combined on the bearing piece and electrically connected with the plurality of leads; and the packaging layer is formed on the bearing piece and covers the electronic element, wherein the packaging layer is defined with a first surface and a second surface which are opposite, one surface of the electronic element is flush with the first surface of the packaging layer, and the guide pins are flush with the second surface of the packaging layer.
The invention also provides a manufacturing method of the electronic packaging piece, which comprises the following steps: combining an electronic element on a bearing piece with a plurality of leads, and enabling the electronic element to be electrically connected with the leads; forming a packaging layer on the bearing piece to enable the packaging layer to wrap the electronic element; and removing part of the material of the packaging layer, part of the material of the electronic element and part of the material of the bearing piece to enable the packaging layer to define a first surface and a second surface which are opposite, so that one surface of the electronic element is flush with the first surface of the packaging layer, and one surface of the guide pin is flush with the second surface of the packaging layer.
In the foregoing manufacturing method, a portion of the material of the encapsulation layer, a portion of the material of the electronic component, and a portion of the material of the carrier are removed by polishing.
The above method further comprises performing singulation.
In the electronic package and the method for fabricating the same, the carrier is a lead frame.
In an embodiment, the electronic component has an active surface and an inactive surface opposite to each other, the active surface of the electronic component is disposed on the leads through the conductive bumps, and the inactive surface is flush with the first surface of the package layer.
In an embodiment, the package layer defines a side surface adjacent to the first surface and the second surface, and a portion of the surface of the lead is exposed out of the side surface of the package layer.
In the electronic package and the method for manufacturing the same, the electronic element is exposed on the first surface of the package layer.
The electronic package and the method for manufacturing the same further include an insulating layer disposed on the second surface of the package layer and having a plurality of openings exposing the leads.
The electronic package and the method for manufacturing the same further include an acting element disposed on the electronic element and the first surface of the package layer. The package structure further includes an insulating layer disposed on the second surface of the package layer and having a plurality of openings exposing the leads, for example, the active element is made of the same material as the insulating layer. Alternatively, the material of the acting element is a polymer as a protective layer.
In view of the above, in the electronic package and the method for manufacturing the same of the present invention, the thickness of the carrier and the thickness of the encapsulation layer are reduced by aligning the upper surface of the electronic component with the first surface of the encapsulation layer and aligning the lower surfaces of the leads with the second surface of the encapsulation layer, so that compared with the prior art, the electronic package manufactured by the method of the present invention has an overall thickness meeting the requirement of thinning and can avoid the electronic component from being cracked.
Drawings
Fig. 1 is a schematic cross-sectional view of a conventional semiconductor package.
Fig. 2A to 2D are schematic cross-sectional views illustrating a method for fabricating an electronic package according to the present invention.
Description of the symbols
1 semiconductor package
10 lead frame
100,200 guide pin
11 semiconductor chip
110 solder bump
12 packaging colloid
2 electronic package
20 load bearing member
20a first side
20b second side
21 electronic component
21a action surface
21b non-active surface
210 electrode pad
211 conductive bump
22 encapsulation layer
22a first surface
22b second surface
22c side surface
23 insulating layer
230 open pore
24 acting element
A crystal-placing part
B external connection part
d, h, h1, h2, r, t thickness.
Detailed Description
The following description of the embodiments of the present invention is provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein.
It should be understood that the structures, ratios, sizes, and the like shown in the drawings and described in the specification are only used for understanding and reading the contents disclosed in the specification, and are not used for limiting the conditions under which the present invention can be implemented, so that the present invention has no technical significance, and any structural modifications, ratio relationship changes or size adjustments should still fall within the scope of the technical contents disclosed in the present invention without affecting the efficacy and the achievable purpose of the present invention. In addition, the terms "first", "second", "upper", "lower" and "a" as used in the present specification are for the sake of clarity only, and are not intended to limit the scope of the present invention, and changes or modifications of the relative relationship may be made without substantial technical changes.
Fig. 2A to 2D are schematic cross-sectional views illustrating a method for manufacturing the electronic package 2 according to the present invention.
As shown in fig. 2A, a carrier 20 having a first side 20a and a second side 20b opposite to each other is provided.
In the present embodiment, the carrier 20 is a leadframe, which includes a plurality of separated leads 200, wherein the leads 200 define a chip-placing portion a and an external portion B adjacent to each other, and the chip-placing portion a is closer to the middle area than the external portion B.
As shown in fig. 2B, at least one electronic component 21 is bonded to the first side 20a of the carrier 20. Next, an encapsulation layer 22 is formed on the first side 20a of the carrier 20 to encapsulate the electronic element 21 and expose the second side 20b of the carrier 20.
The electronic component 21 is an active component, such as a semiconductor chip, a passive component, such as a resistor, a capacitor, or an inductor, or a combination thereof. In the present embodiment, the electronic component 21 is a semiconductor chip, which has an active surface 21a and an inactive surface 21b opposite to each other, and the active surface 21a has a plurality of electrode pads 210, so that the electronic component 21 is disposed on the die pad a of the leads 200 in a flip chip manner through a plurality of conductive bumps 211 (such as solder material or other conductive material) bonded to the electrode pads 210, so that the electronic component 21 is electrically connected to the leads 200.
In addition, the material forming the encapsulation layer 22 is Polyimide (PI), dry film (dry film), epoxy resin (epoxy), or encapsulation compound (molding compound), or other suitable insulating material.
As shown in fig. 2C, a portion of the material of the encapsulation layer 22, a portion of the material of the electronic component 21, and a portion of the material of the carrier 20 (the second side 20b) are removed, such that the non-active surface 21b of the electronic component 21 is exposed out of the encapsulation layer 22, and the second side 20b of the carrier 20 is still exposed out of the encapsulation layer 22.
In the present embodiment, a portion of the material of the encapsulation layer 22, a portion of the material of the inactive surface 21B of the electronic component 21, and a portion of the material of the second side 20B of the carrier 20 are removed along the predetermined removal region L shown in fig. 2B by a leveling operation (e.g., a grinding operation), such that the encapsulation layer 22 defines a first surface 22a and a second surface 22B opposite to each other, the inactive surface 21B of the electronic component 21 is flush with the first surface 22a of the encapsulation layer 22, and the leads 200 (or the second side 20B of the carrier 20) are flush with the second surface 22B of the encapsulation layer 22.
As shown in fig. 2D, singulation is performed along the cutting path S shown in fig. 2C to obtain the electronic package 2 with the leads 200 exposed on the side surface 22C of the package layer 22.
In the present embodiment, the electronic package 2 is of a quad flat no-lead (QFN) type, and the bottom and side surfaces of the leads 200 are flush with the second surface 22b and the side surface 22c of the package layer 22, so that solder materials (not shown) such as solder balls are formed on the exposed surfaces of the leads 200 for connecting to an electronic device (not shown) such as a circuit board or another circuit board.
In addition, an insulating layer 23, such as solder resist, may be formed on the second side 20b of the carrier 20 and the second surface 22b of the package layer 22 as required, wherein a plurality of openings 230 exposing portions of the leads 200 are formed, and solder material, such as solder balls, is formed on the leads 200 exposed in the openings 230 (not shown).
Furthermore, an acting element 24, such as a film, a heat sink or other structures, may be disposed on the first surface 22a of the encapsulation layer 22 and the non-acting surface 21b of the electronic element 21 as required to protect the electronic element 21 or provide heat dissipation for the electronic element 21. For example, the material of the acting element 24 can be Polymer (Polymer) as a protective layer; alternatively, the material of the acting element 24 and the insulating layer 23 can be the same.
Therefore, the method of the present invention removes a portion of the material of the package layer 22, a portion of the material of the electronic element 21, and a portion of the material of the second side 20b of the carrier 20 through leveling operation to reduce the thickness h1 of the carrier 20 and the thickness h2 of the package layer 22 (as shown in fig. 2C), so that the overall thickness h (as shown in fig. 2D) of the electronic package 2 obtained by the method of the present invention can meet the requirement of thinning, for example, the overall thickness h is only 0.135 mm.
In addition, the manufacturing method of the present invention first locates the electronic component 21 on the carrier 20, and then coats the electronic component 21 with the encapsulation layer 22, so that when removing part of the material of the encapsulation layer 22 and part of the material of the non-active surface 21b of the electronic component 21, the encapsulation layer 22 can disperse stress, so compared with the prior art, the manufacturing method of the present invention can not only thin the thickness r of the electronic component 21, but also avoid the problem of cracking of the electronic component 21.
The present invention also provides an electronic package 2 comprising: a carrier 20, an electronic component 21 and an encapsulation layer 22.
The carrier 20 is a lead frame, and includes a plurality of separated leads 200.
The electronic component 21 is combined on the carrier 20 and electrically connected to the leads 200.
The package layer 22 is formed on the carrier 20 and covers the electronic component 21, wherein the package layer 22 defines a first surface 22a and a second surface 22b opposite to each other, an upper surface of the electronic component 21 is flush with the first surface 22a of the package layer 22, and a lower surface of the lead 200 is flush with the second surface 22b of the package layer 22, so that the electronic component 21 and the lead 200 are exposed from the package layer 22.
In one embodiment, the electronic component 21 has an active surface 21a and an inactive surface 21b opposite to each other, and the active surface 21a is disposed on the leads 200 through a plurality of conductive bumps 211, and the inactive surface 21b is flush with the first surface 22a of the package layer 22.
In one embodiment, the package layer 22 defines a side surface 22c adjacent to the first and second surfaces 22a,22b, such that the leads 200 are exposed at the side surface 22c of the package layer 22.
In one embodiment, the electronic component 21 is exposed at the first surface 22a of the encapsulation layer 22.
In one embodiment, the electronic package 2 further includes an insulating layer 23 disposed on the second surface 22b of the package layer 22 and having a plurality of openings 230 exposing the leads 200.
In one embodiment, the electronic package 2 further includes an acting element 24 disposed on the electronic element 21 and the first surface 22a of the encapsulation layer 22. For example, the material of the acting element 24 is the same as the material of the insulating layer 23. Alternatively, the material of the acting element 24 is a polymer as a protective layer.
In summary, the electronic package and the manufacturing method thereof of the present invention reduce the overall thickness of the electronic package through the leveling process of the vertical polishing, thereby meeting the requirement of thinning and avoiding the problem of cracking of the electronic device.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify the above-described embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.

Claims (20)

1. An electronic package, comprising:
a carrier having a plurality of leads;
an electronic element which is combined on the bearing piece and electrically connected with the plurality of leads; and
and the packaging layer is formed on the bearing piece and covers the electronic element, wherein the packaging layer is defined with a first surface and a second surface which are opposite, one surface of the electronic element is flush with the first surface of the packaging layer, and one surface of the lead is flush with the second surface of the packaging layer.
2. The electronic package according to claim 1, wherein the carrier is a lead frame.
3. The electronic package according to claim 1, wherein the electronic component has an active surface and an inactive surface opposite to each other, the active surface of the electronic component is disposed on the leads via the conductive bumps, and the inactive surface is flush with the first surface of the package layer.
4. The electronic package of claim 1, wherein the encapsulation layer defines side surfaces adjacent to the first and second surfaces, and wherein portions of the surfaces of the leads are exposed at the side surfaces of the encapsulation layer.
5. The electronic package according to claim 1, further comprising an insulating layer disposed on the second surface of the encapsulation layer and having a plurality of openings exposing the leads.
6. The electronic package according to claim 1, further comprising an acting element disposed on the electronic component and the first surface of the encapsulation layer.
7. The electronic package according to claim 6, further comprising an insulating layer disposed on the second surface of the encapsulation layer and having a plurality of openings exposing the leads.
8. The electronic package of claim 7, wherein the acting element is made of the same material as the insulating layer.
9. The electronic package of claim 6, wherein the acting element is made of a polymer as a protective layer.
10. A method of fabricating an electronic package, comprising:
combining an electronic element on a bearing piece with a plurality of leads, and enabling the electronic element to be electrically connected with the leads;
forming a packaging layer on the bearing piece to enable the packaging layer to wrap the electronic element; and
removing part of the material of the packaging layer, part of the material of the electronic element and part of the material of the bearing piece to enable the packaging layer to define a first surface and a second surface which are opposite, so that one surface of the electronic element is flush with the first surface of the packaging layer, and one surface of the guide pin is flush with the second surface of the packaging layer.
11. The method of claim 10, wherein the carrier is a leadframe.
12. The method of claim 10, wherein the electronic component has an active surface and an inactive surface opposite to each other, the active surface of the electronic component is disposed on the leads via the conductive bumps, and the inactive surface is flush with the first surface of the package layer.
13. The method of claim 10, wherein the encapsulation layer defines side surfaces adjacent to the first and second surfaces, and a portion of the surface of the leads is exposed out of the side surfaces of the encapsulation layer.
14. The method of claim 10, further comprising disposing an insulating layer on the second surface of the encapsulation layer, wherein the insulating layer has a plurality of openings exposing the leads.
15. The method of claim 10, further comprising disposing a working element on the electronic component and the first surface of the encapsulation layer.
16. The method of claim 15, further comprising disposing an insulating layer on the second surface of the package layer, wherein the insulating layer has a plurality of openings exposing the leads.
17. The method of claim 16, wherein the acting element is made of the same material as the insulating layer.
18. The method of claim 15, wherein the material of the acting element is a polymer as a protective layer.
19. The method of claim 10, wherein a portion of the encapsulating layer, a portion of the electronic component, and a portion of the carrier are removed by grinding.
20. The method of claim 10, further comprising performing singulation operations.
CN201910624358.4A 2019-07-03 2019-07-11 Electronic package and manufacturing method thereof Pending CN112185903A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW108123412A TWI690039B (en) 2019-07-03 2019-07-03 Electronic package and manufacturing method thereof
TW108123412 2019-07-03

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Publication Number Publication Date
CN112185903A true CN112185903A (en) 2021-01-05

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Publication number Priority date Publication date Assignee Title
CN113675101B (en) 2021-10-20 2021-12-21 深圳新声半导体有限公司 Method for chip packaging and chip particles
CN113675102A (en) 2021-10-22 2021-11-19 深圳新声半导体有限公司 Method for chip packaging and chip particles

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CN109478544A (en) * 2015-07-10 2019-03-15 创研腾科技有限公司 General adhesive surface semiconductor packages

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TW463342B (en) * 2000-08-18 2001-11-11 Siliconware Precision Industries Co Ltd Flip-chip quad-flat nolead package
TWI490988B (en) * 2012-03-21 2015-07-01 Chipmos Technologies Inc Semiconductor package structure
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Publication number Priority date Publication date Assignee Title
US20080116580A1 (en) * 2006-11-17 2008-05-22 Siliconware Precision Industries Co., Ltd. Semiconductor package and fabrication method thereof
CN101335216A (en) * 2007-06-27 2008-12-31 矽品精密工业股份有限公司 Heat radiating type package construction and manufacturing method thereof
CN102683230A (en) * 2012-05-30 2012-09-19 天水华天科技股份有限公司 Quad flat no-lead multi-circle-arranged integrated circuit (IC) chip packaging part and production method thereof
CN103094240A (en) * 2012-12-15 2013-05-08 华天科技（西安）有限公司 High-density etched lead frame FCAAQFN package part and manufacture process thereof
CN106328545A (en) * 2015-07-02 2017-01-11 万国半导体(开曼)股份有限公司 Ultrathin chip double-surface exposed package structure of and manufacturing method thereof
CN109478544A (en) * 2015-07-10 2019-03-15 创研腾科技有限公司 General adhesive surface semiconductor packages

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TWI690039B (en) 2020-04-01

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